1 /* $NetBSD: ahd_pci.c,v 1.31 2009/09/26 14:44:11 tsutsui Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 49 * - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.31 2009/09/26 14:44:11 tsutsui Exp $"); 54 55 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 56 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 57 58 #include <dev/ic/aic79xx_osm.h> 59 #include <dev/ic/aic79xx_inline.h> 60 61 static inline uint64_t 62 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 63 { 64 uint64_t id; 65 66 id = subvendor 67 | (subdevice << 16) 68 | ((uint64_t)vendor << 32) 69 | ((uint64_t)device << 48); 70 71 return (id); 72 } 73 74 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 75 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 76 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 77 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 78 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 79 80 #define ID_AIC7901 0x800F9005FFFF9005ull 81 #define ID_AHA_29320A 0x8000900500609005ull 82 #define ID_AHA_29320ALP 0x8017900500449005ull 83 84 #define ID_AIC7901A 0x801E9005FFFF9005ull 85 #define ID_AHA_29320LP 0x8014900500449005ull 86 87 #define ID_AIC7902 0x801F9005FFFF9005ull 88 #define ID_AIC7902_B 0x801D9005FFFF9005ull 89 #define ID_AHA_39320 0x8010900500409005ull 90 #define ID_AHA_29320 0x8012900500429005ull 91 #define ID_AHA_29320B 0x8013900500439005ull 92 #define ID_AHA_39320_B 0x8015900500409005ull 93 #define ID_AHA_39320A 0x8016900500409005ull 94 #define ID_AHA_39320D 0x8011900500419005ull 95 #define ID_AHA_39320D_B 0x801C900500419005ull 96 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 97 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 98 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 99 #define ID_AIC7902_PCI_REV_A4 0x3 100 #define ID_AIC7902_PCI_REV_B0 0x10 101 #define SUBID_HP 0x0E11 102 103 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 104 105 #define DEVID_9005_TYPE(id) ((id) & 0xF) 106 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 107 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 108 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 109 110 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 111 112 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 113 114 #define SUBID_9005_TYPE(id) ((id) & 0xF) 115 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 116 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 117 118 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 119 120 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 121 122 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 123 #define SUBID_9005_SEEPTYPE_NONE 0x0 124 #define SUBID_9005_SEEPTYPE_4K 0x1 125 126 static ahd_device_setup_t ahd_aic7901_setup; 127 static ahd_device_setup_t ahd_aic7901A_setup; 128 static ahd_device_setup_t ahd_aic7902_setup; 129 static ahd_device_setup_t ahd_aic790X_setup; 130 131 static struct ahd_pci_identity ahd_pci_ident_table [] = 132 { 133 /* aic7901 based controllers */ 134 { 135 ID_AHA_29320A, 136 ID_ALL_MASK, 137 "Adaptec 29320A Ultra320 SCSI adapter", 138 ahd_aic7901_setup 139 }, 140 { 141 ID_AHA_29320ALP, 142 ID_ALL_MASK, 143 "Adaptec 29320ALP Ultra320 SCSI adapter", 144 ahd_aic7901_setup 145 }, 146 /* aic7901A based controllers */ 147 { 148 ID_AHA_29320LP, 149 ID_ALL_MASK, 150 "Adaptec 29320LP Ultra320 SCSI adapter", 151 ahd_aic7901A_setup 152 }, 153 /* aic7902 based controllers */ 154 { 155 ID_AHA_39320, 156 ID_ALL_MASK, 157 "Adaptec 39320 Ultra320 SCSI adapter", 158 ahd_aic7902_setup 159 }, 160 { 161 ID_AHA_39320_B, 162 ID_ALL_MASK, 163 "Adaptec 39320 Ultra320 SCSI adapter", 164 ahd_aic7902_setup 165 }, 166 { 167 ID_AHA_39320_B_DELL, 168 ID_ALL_IROC_MASK, 169 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 170 ahd_aic7902_setup 171 }, 172 { 173 ID_AHA_39320A, 174 ID_ALL_MASK, 175 "Adaptec 39320A Ultra320 SCSI adapter", 176 ahd_aic7902_setup 177 }, 178 { 179 ID_AHA_39320D, 180 ID_ALL_MASK, 181 "Adaptec 39320D Ultra320 SCSI adapter", 182 ahd_aic7902_setup 183 }, 184 { 185 ID_AHA_39320D_HP, 186 ID_ALL_MASK, 187 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 188 ahd_aic7902_setup 189 }, 190 { 191 ID_AHA_39320D_B, 192 ID_ALL_MASK, 193 "Adaptec 39320D Ultra320 SCSI adapter", 194 ahd_aic7902_setup 195 }, 196 { 197 ID_AHA_39320D_B_HP, 198 ID_ALL_MASK, 199 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 200 ahd_aic7902_setup 201 }, 202 /* Generic chip probes for devices we don't know 'exactly' */ 203 { 204 ID_AIC7901 & ID_9005_GENERIC_MASK, 205 ID_9005_GENERIC_MASK, 206 "Adaptec AIC7901 Ultra320 SCSI adapter", 207 ahd_aic7901_setup 208 }, 209 { 210 ID_AIC7901A & ID_DEV_VENDOR_MASK, 211 ID_DEV_VENDOR_MASK, 212 "Adaptec AIC7901A Ultra320 SCSI adapter", 213 ahd_aic7901A_setup 214 }, 215 { 216 ID_AIC7902 & ID_9005_GENERIC_MASK, 217 ID_9005_GENERIC_MASK, 218 "Adaptec AIC7902 Ultra320 SCSI adapter", 219 ahd_aic7902_setup 220 } 221 }; 222 223 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 224 225 #define DEVCONFIG 0x40 226 #define PCIXINITPAT 0x0000E000ul 227 #define PCIXINIT_PCI33_66 0x0000E000ul 228 #define PCIXINIT_PCIX50_66 0x0000C000ul 229 #define PCIXINIT_PCIX66_100 0x0000A000ul 230 #define PCIXINIT_PCIX100_133 0x00008000ul 231 #define PCI_BUS_MODES_INDEX(devconfig) \ 232 (((devconfig) & PCIXINITPAT) >> 13) 233 234 static const char *pci_bus_modes[] = 235 { 236 "PCI bus mode unknown", 237 "PCI bus mode unknown", 238 "PCI bus mode unknown", 239 "PCI bus mode unknown", 240 "PCI-X 101-133 MHz", 241 "PCI-X 67-100 MHz", 242 "PCI-X 50-66 MHz", 243 "PCI 33 or 66 MHz" 244 }; 245 246 #define TESTMODE 0x00000800ul 247 #define IRDY_RST 0x00000200ul 248 #define FRAME_RST 0x00000100ul 249 #define PCI64BIT 0x00000080ul 250 #define MRDCEN 0x00000040ul 251 #define ENDIANSEL 0x00000020ul 252 #define MIXQWENDIANEN 0x00000008ul 253 #define DACEN 0x00000004ul 254 #define STPWLEVEL 0x00000002ul 255 #define QWENDIANSEL 0x00000001ul 256 257 #define DEVCONFIG1 0x44 258 #define PREQDIS 0x01 259 260 #define LATTIME 0x0000ff00ul 261 262 static int ahd_check_extport(struct ahd_softc *ahd); 263 static void ahd_configure_termination(struct ahd_softc *ahd, 264 u_int adapter_control); 265 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 266 267 static int ahd_pci_test_register_access(struct ahd_softc *); 268 269 static int ahd_pci_intr(struct ahd_softc *); 270 271 static const struct ahd_pci_identity * 272 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 273 { 274 u_int64_t full_id; 275 const struct ahd_pci_identity *entry; 276 u_int i; 277 278 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 279 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 280 281 for (i = 0; i < ahd_num_pci_devs; i++) { 282 entry = &ahd_pci_ident_table[i]; 283 if (entry->full_id == (full_id & entry->id_mask)) 284 return (entry); 285 } 286 return (NULL); 287 } 288 289 static int 290 ahd_pci_probe(device_t parent, cfdata_t match, void *aux) 291 { 292 struct pci_attach_args *pa = aux; 293 const struct ahd_pci_identity *entry; 294 pcireg_t subid; 295 296 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 297 entry = ahd_find_pci_device(pa->pa_id, subid); 298 return entry != NULL ? 1 : 0; 299 } 300 301 static void 302 ahd_pci_attach(device_t parent, device_t self, void *aux) 303 { 304 struct pci_attach_args *pa = aux; 305 struct ahd_softc *ahd = device_private(self); 306 307 const struct ahd_pci_identity *entry; 308 309 uint32_t devconfig; 310 pcireg_t command; 311 int error; 312 pcireg_t subid; 313 uint16_t subvendor; 314 pcireg_t reg; 315 int ioh_valid, ioh2_valid, memh_valid; 316 pcireg_t memtype; 317 pci_intr_handle_t ih; 318 const char *intrstr; 319 struct ahd_pci_busdata *bd; 320 321 ahd->sc_dev = self; 322 ahd_set_name(ahd, device_xname(self)); 323 ahd->parent_dmat = pa->pa_dmat; 324 325 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 326 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 327 entry = ahd_find_pci_device(pa->pa_id, subid); 328 if (entry == NULL) 329 return; 330 331 /* Keep information about the PCI bus */ 332 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 333 if (bd == NULL) { 334 aprint_error("%s: unable to allocate bus-specific data\n", 335 ahd_name(ahd)); 336 return; 337 } 338 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 339 340 bd->pc = pa->pa_pc; 341 bd->tag = pa->pa_tag; 342 bd->func = pa->pa_function; 343 bd->dev = pa->pa_device; 344 345 ahd->bus_data = bd; 346 347 ahd->description = entry->name; 348 349 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 350 M_DEVBUF, M_NOWAIT); 351 if (ahd->seep_config == NULL) { 352 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 353 return; 354 } 355 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 356 357 LIST_INIT(&ahd->pending_scbs); 358 ahd_timer_init(&ahd->reset_timer); 359 ahd_timer_init(&ahd->stat_timer); 360 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 361 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 362 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 363 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 364 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 365 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 366 ahd->int_coalescing_stop_threshold = 367 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 368 369 if (ahd_platform_alloc(ahd, NULL) != 0) { 370 ahd_free(ahd); 371 return; 372 } 373 374 /* 375 * Record if this is an HP board. 376 */ 377 subvendor = PCI_VENDOR(subid); 378 if (subvendor == SUBID_HP) 379 ahd->flags |= AHD_HP_BOARD; 380 381 error = entry->setup(ahd, pa); 382 if (error != 0) 383 return; 384 385 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 386 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 387 ahd->chip |= AHD_PCI; 388 /* Disable PCIX workarounds when running in PCI mode. */ 389 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 390 } else { 391 ahd->chip |= AHD_PCIX; 392 } 393 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 394 395 memh_valid = ioh_valid = ioh2_valid = 0; 396 397 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 398 &bd->pcix_off, NULL)) { 399 if (ahd->chip & AHD_PCIX) 400 aprint_error_dev(self, 401 "warning: can't find PCI-X capability\n"); 402 ahd->chip &= ~AHD_PCIX; 403 ahd->chip |= AHD_PCI; 404 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 405 } 406 407 /* 408 * Map PCI Registers 409 */ 410 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 411 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 412 AHD_PCI_MEMADDR); 413 switch (memtype) { 414 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 415 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 416 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 417 memtype, 0, &ahd->tags[0], 418 &ahd->bshs[0], 419 NULL, NULL) == 0); 420 if (memh_valid) { 421 ahd->tags[1] = ahd->tags[0]; 422 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 423 /*offset*/0x100, 424 /*size*/0x100, 425 &ahd->bshs[1]); 426 if (ahd_pci_test_register_access(ahd) != 0) 427 memh_valid = 0; 428 } 429 break; 430 default: 431 memh_valid = 0; 432 aprint_error("%s: unknown memory type: 0x%x\n", 433 ahd_name(ahd), memtype); 434 break; 435 } 436 437 if (memh_valid) { 438 command &= ~PCI_COMMAND_IO_ENABLE; 439 pci_conf_write(pa->pa_pc, pa->pa_tag, 440 PCI_COMMAND_STATUS_REG, command); 441 } 442 #ifdef AHD_DEBUG 443 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, " 444 "shs0 0x%lx, shs1 0x%lx\n", 445 ahd_name(ahd), ahd->tags[0], ahd->tags[1], 446 ahd->bshs[0], ahd->bshs[1]); 447 #endif 448 } 449 450 if (command & PCI_COMMAND_IO_ENABLE) { 451 /* First BAR */ 452 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 453 PCI_MAPREG_TYPE_IO, 0, 454 &ahd->tags[0], &ahd->bshs[0], 455 NULL, NULL) == 0); 456 457 /* 2nd BAR */ 458 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 459 PCI_MAPREG_TYPE_IO, 0, 460 &ahd->tags[1], &ahd->bshs[1], 461 NULL, NULL) == 0); 462 463 if (ioh_valid && ioh2_valid) { 464 KASSERT(memh_valid == 0); 465 command &= ~PCI_COMMAND_MEM_ENABLE; 466 pci_conf_write(pa->pa_pc, pa->pa_tag, 467 PCI_COMMAND_STATUS_REG, command); 468 } 469 #ifdef AHD_DEBUG 470 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, " 471 "shs0 0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 472 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 473 #endif 474 475 } 476 477 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 478 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 479 return; 480 } 481 482 aprint_normal("\n"); 483 aprint_naive("\n"); 484 485 /* power up chip */ 486 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 487 pci_activate_null)) && error != EOPNOTSUPP) { 488 aprint_error_dev(self, "cannot activate %d\n", error); 489 return; 490 } 491 /* 492 * Should we bother disabling 39Bit addressing 493 * based on installed memory? 494 */ 495 if (sizeof(bus_addr_t) > 4) 496 ahd->flags |= AHD_39BIT_ADDRESSING; 497 498 /* 499 * If we need to support high memory, enable dual 500 * address cycles. This bit must be set to enable 501 * high address bit generation even if we are on a 502 * 64bit bus (PCI64BIT set in devconfig). 503 */ 504 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 505 uint32_t dvconfig; 506 507 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 508 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 509 dvconfig |= DACEN; 510 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig); 511 } 512 513 /* Ensure busmastering is enabled */ 514 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 515 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 516 reg | PCI_COMMAND_MASTER_ENABLE); 517 518 ahd_softc_init(ahd); 519 520 /* 521 * Map the interrupt routines 522 */ 523 ahd->bus_intr = ahd_pci_intr; 524 525 error = ahd_reset(ahd, /*reinit*/FALSE); 526 if (error != 0) { 527 ahd_free(ahd); 528 return; 529 } 530 531 if (pci_intr_map(pa, &ih)) { 532 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 533 ahd_free(ahd); 534 return; 535 } 536 intrstr = pci_intr_string(pa->pa_pc, ih); 537 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 538 if (ahd->ih == NULL) { 539 aprint_error("%s: couldn't establish interrupt", 540 ahd_name(ahd)); 541 if (intrstr != NULL) 542 aprint_error(" at %s", intrstr); 543 aprint_error("\n"); 544 ahd_free(ahd); 545 return; 546 } 547 if (intrstr != NULL) 548 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 549 intrstr); 550 551 /* Get the size of the cache */ 552 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 553 ahd->pci_cachesize *= 4; 554 555 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 556 /* See if we have a SEEPROM and perform auto-term */ 557 error = ahd_check_extport(ahd); 558 if (error != 0) 559 return; 560 561 /* Core initialization */ 562 error = ahd_init(ahd); 563 if (error != 0) 564 return; 565 566 /* 567 * Link this softc in with all other ahd instances. 568 */ 569 ahd_attach(ahd); 570 } 571 572 CFATTACH_DECL_NEW(ahd_pci, sizeof(struct ahd_softc), 573 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 574 575 /* 576 * Perform some simple tests that should catch situations where 577 * our registers are invalidly mapped. 578 */ 579 static int 580 ahd_pci_test_register_access(struct ahd_softc *ahd) 581 { 582 uint32_t cmd; 583 struct ahd_pci_busdata *bd = ahd->bus_data; 584 u_int targpcistat; 585 uint32_t pci_status1; 586 int error; 587 uint8_t hcntrl; 588 589 error = EIO; 590 591 /* 592 * Enable PCI error interrupt status, but suppress NMIs 593 * generated by SERR raised due to target aborts. 594 */ 595 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 596 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 597 cmd & ~PCI_COMMAND_SERR_ENABLE); 598 599 /* 600 * First a simple test to see if any 601 * registers can be read. Reading 602 * HCNTRL has no side effects and has 603 * at least one bit that is guaranteed to 604 * be zero so it is a good register to 605 * use for this test. 606 */ 607 hcntrl = ahd_inb(ahd, HCNTRL); 608 if (hcntrl == 0xFF) 609 goto fail; 610 611 /* 612 * Next create a situation where write combining 613 * or read prefetching could be initiated by the 614 * CPU or host bridge. Our device does not support 615 * either, so look for data corruption and/or flaged 616 * PCI errors. First pause without causing another 617 * chip reset. 618 */ 619 hcntrl &= ~CHIPRST; 620 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 621 while (ahd_is_paused(ahd) == 0) 622 ; 623 624 /* Clear any PCI errors that occurred before our driver attached. */ 625 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 626 targpcistat = ahd_inb(ahd, TARGPCISTAT); 627 ahd_outb(ahd, TARGPCISTAT, targpcistat); 628 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 629 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 630 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 631 ahd_outb(ahd, CLRINT, CLRPCIINT); 632 633 ahd_outb(ahd, SEQCTL0, PERRORDIS); 634 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 635 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 636 goto fail; 637 638 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 639 u_int trgpcistat; 640 641 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 642 trgpcistat = ahd_inb(ahd, TARGPCISTAT); 643 if ((trgpcistat & STA) != 0) 644 goto fail; 645 } 646 647 error = 0; 648 649 fail: 650 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 651 652 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 653 targpcistat = ahd_inb(ahd, TARGPCISTAT); 654 655 /* Silently clear any latched errors. */ 656 ahd_outb(ahd, TARGPCISTAT, targpcistat); 657 pci_status1 = pci_conf_read(bd->pc, bd->tag, 658 PCI_COMMAND_STATUS_REG); 659 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 660 pci_status1); 661 ahd_outb(ahd, CLRINT, CLRPCIINT); 662 } 663 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 664 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 665 return (error); 666 } 667 668 /* 669 * Check the external port logic for a serial eeprom 670 * and termination/cable detection contrls. 671 */ 672 static int 673 ahd_check_extport(struct ahd_softc *ahd) 674 { 675 struct vpd_config vpd; 676 struct seeprom_config *sc; 677 u_int adapter_control; 678 int have_seeprom; 679 int error; 680 681 sc = ahd->seep_config; 682 have_seeprom = ahd_acquire_seeprom(ahd); 683 if (have_seeprom) { 684 u_int start_addr; 685 686 /* 687 * Fetch VPD for this function and parse it. 688 */ 689 #ifdef AHD_DEBUG 690 printf("%s: Reading VPD from SEEPROM...", 691 ahd_name(ahd)); 692 #endif 693 /* Address is always in units of 16bit words */ 694 start_addr = ((2 * sizeof(*sc)) 695 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 696 697 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 698 start_addr, sizeof(vpd)/2, 699 /*bytestream*/TRUE); 700 if (error == 0) 701 error = ahd_parse_vpddata(ahd, &vpd); 702 #ifdef AHD_DEBUG 703 printf("%s: VPD parsing %s\n", 704 ahd_name(ahd), 705 error == 0 ? "successful" : "failed"); 706 #endif 707 708 #ifdef AHD_DEBUG 709 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 710 #endif 711 712 /* Address is always in units of 16bit words */ 713 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 714 715 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 716 start_addr, sizeof(*sc)/2, 717 /*bytestream*/FALSE); 718 719 if (error != 0) { 720 #ifdef AHD_DEBUG 721 printf("Unable to read SEEPROM\n"); 722 #endif 723 have_seeprom = 0; 724 } else { 725 have_seeprom = ahd_verify_cksum(sc); 726 #ifdef AHD_DEBUG 727 if (have_seeprom == 0) 728 printf ("checksum error\n"); 729 else 730 printf ("done.\n"); 731 #endif 732 } 733 ahd_release_seeprom(ahd); 734 } 735 736 if (!have_seeprom) { 737 u_int nvram_scb; 738 739 /* 740 * Pull scratch ram settings and treat them as 741 * if they are the contents of an seeprom if 742 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 743 * in SCB 0xFF. We manually compose the data as 16bit 744 * values to avoid endian issues. 745 */ 746 ahd_set_scbptr(ahd, 0xFF); 747 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 748 if (nvram_scb != 0xFF 749 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 750 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 751 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 752 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 753 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 754 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 755 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 756 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 757 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 758 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 759 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 760 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 761 uint16_t *sc_data; 762 int i; 763 764 ahd_set_scbptr(ahd, nvram_scb); 765 sc_data = (uint16_t *)sc; 766 for (i = 0; i < 64; i += 2) 767 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 768 have_seeprom = ahd_verify_cksum(sc); 769 if (have_seeprom) 770 ahd->flags |= AHD_SCB_CONFIG_USED; 771 } 772 } 773 774 #ifdef AHD_DEBUG 775 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 776 uint16_t *sc_data; 777 int i; 778 779 printf("%s: Seeprom Contents:", ahd_name(ahd)); 780 sc_data = (uint16_t *)sc; 781 for (i = 0; i < (sizeof(*sc)); i += 2) 782 printf("\n\t0x%.4x", sc_data[i]); 783 printf("\n"); 784 } 785 #endif 786 787 if (!have_seeprom) { 788 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 789 ahd->flags |= AHD_USEDEFAULTS; 790 error = ahd_default_config(ahd); 791 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 792 free(ahd->seep_config, M_DEVBUF); 793 ahd->seep_config = NULL; 794 } else { 795 error = ahd_parse_cfgdata(ahd, sc); 796 adapter_control = sc->adapter_control; 797 } 798 if (error != 0) 799 return (error); 800 801 ahd_configure_termination(ahd, adapter_control); 802 803 return (0); 804 } 805 806 static void 807 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 808 { 809 int error; 810 u_int sxfrctl1; 811 uint8_t termctl; 812 uint32_t devconfig; 813 struct ahd_pci_busdata *bd = ahd->bus_data; 814 815 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 816 devconfig &= ~STPWLEVEL; 817 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 818 devconfig |= STPWLEVEL; 819 #ifdef AHD_DEBUG 820 printf("%s: STPWLEVEL is %s\n", 821 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 822 #endif 823 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 824 825 /* Make sure current sensing is off. */ 826 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 827 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 828 } 829 830 /* 831 * Read to sense. Write to set. 832 */ 833 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 834 if ((adapter_control & CFAUTOTERM) == 0) { 835 if (bootverbose) 836 printf("%s: Manual Primary Termination\n", 837 ahd_name(ahd)); 838 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 839 if ((adapter_control & CFSTERM) != 0) 840 termctl |= FLX_TERMCTL_ENPRILOW; 841 if ((adapter_control & CFWSTERM) != 0) 842 termctl |= FLX_TERMCTL_ENPRIHIGH; 843 } else if (error != 0) { 844 if (bootverbose) 845 printf("%s: Primary Auto-Term Sensing failed! " 846 "Using Defaults.\n", ahd_name(ahd)); 847 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 848 } 849 850 if ((adapter_control & CFSEAUTOTERM) == 0) { 851 if (bootverbose) 852 printf("%s: Manual Secondary Termination\n", 853 ahd_name(ahd)); 854 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 855 if ((adapter_control & CFSELOWTERM) != 0) 856 termctl |= FLX_TERMCTL_ENSECLOW; 857 if ((adapter_control & CFSEHIGHTERM) != 0) 858 termctl |= FLX_TERMCTL_ENSECHIGH; 859 } else if (error != 0) { 860 if (bootverbose) 861 printf("%s: Secondary Auto-Term Sensing failed! " 862 "Using Defaults.\n", ahd_name(ahd)); 863 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 864 } 865 866 /* 867 * Now set the termination based on what we found. 868 */ 869 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 870 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 871 ahd->flags |= AHD_TERM_ENB_A; 872 sxfrctl1 |= STPWEN; 873 } 874 /* Must set the latch once in order to be effective. */ 875 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 876 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 877 878 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 879 if (error != 0) { 880 aprint_error("%s: Unable to set termination settings!\n", 881 ahd_name(ahd)); 882 } else { 883 if (bootverbose) { 884 printf("%s: Primary High byte termination %sabled\n", 885 ahd_name(ahd), 886 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 887 888 printf("%s: Primary Low byte termination %sabled\n", 889 ahd_name(ahd), 890 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 891 892 printf("%s: Secondary High byte termination %sabled\n", 893 ahd_name(ahd), 894 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 895 896 printf("%s: Secondary Low byte termination %sabled\n", 897 ahd_name(ahd), 898 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 899 } 900 } 901 return; 902 } 903 904 #define DPE 0x80 905 #define SSE 0x40 906 #define RMA 0x20 907 #define RTA 0x10 908 #define STA 0x08 909 #define DPR 0x01 910 911 static const char *split_status_source[] = 912 { 913 "DFF0", 914 "DFF1", 915 "OVLY", 916 "CMC", 917 }; 918 919 static const char *pci_status_source[] = 920 { 921 "DFF0", 922 "DFF1", 923 "SG", 924 "CMC", 925 "OVLY", 926 "NONE", 927 "MSI", 928 "TARG" 929 }; 930 931 static const char *split_status_strings[] = 932 { 933 "%s: Received split response in %s.\n", 934 "%s: Received split completion error message in %s\n", 935 "%s: Receive overrun in %s\n", 936 "%s: Count not complete in %s\n", 937 "%s: Split completion data bucket in %s\n", 938 "%s: Split completion address error in %s\n", 939 "%s: Split completion byte count error in %s\n", 940 "%s: Signaled Target-abort to early terminate a split in %s\n" 941 }; 942 943 static const char *pci_status_strings[] = 944 { 945 "%s: Data Parity Error has been reported via PERR# in %s\n", 946 "%s: Target initial wait state error in %s\n", 947 "%s: Split completion read data parity error in %s\n", 948 "%s: Split completion address attribute parity error in %s\n", 949 "%s: Received a Target Abort in %s\n", 950 "%s: Received a Master Abort in %s\n", 951 "%s: Signal System Error Detected in %s\n", 952 "%s: Address or Write Phase Parity Error Detected in %s.\n" 953 }; 954 955 static int 956 ahd_pci_intr(struct ahd_softc *ahd) 957 { 958 uint8_t pci_status[8]; 959 ahd_mode_state saved_modes; 960 u_int pci_status1; 961 u_int intstat; 962 u_int i; 963 u_int reg; 964 struct ahd_pci_busdata *bd = ahd->bus_data; 965 966 intstat = ahd_inb(ahd, INTSTAT); 967 968 if ((intstat & SPLTINT) != 0) 969 ahd_pci_split_intr(ahd, intstat); 970 971 if ((intstat & PCIINT) == 0) 972 return 0; 973 974 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 975 saved_modes = ahd_save_modes(ahd); 976 ahd_dump_card_state(ahd); 977 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 978 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 979 980 if (i == 5) 981 continue; 982 pci_status[i] = ahd_inb(ahd, reg); 983 /* Clear latched errors. So our interrupt deasserts. */ 984 ahd_outb(ahd, reg, pci_status[i]); 985 } 986 987 for (i = 0; i < 8; i++) { 988 u_int bit; 989 990 if (i == 5) 991 continue; 992 993 for (bit = 0; bit < 8; bit++) { 994 995 if ((pci_status[i] & (0x1 << bit)) != 0) { 996 static const char *s; 997 998 s = pci_status_strings[bit]; 999 if (i == 7/*TARG*/ && bit == 3) 1000 s = "%s: Signaled Target Abort\n"; 1001 printf(s, ahd_name(ahd), pci_status_source[i]); 1002 } 1003 } 1004 } 1005 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1006 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1007 1008 ahd_restore_modes(ahd, saved_modes); 1009 ahd_outb(ahd, CLRINT, CLRPCIINT); 1010 ahd_unpause(ahd); 1011 1012 return 1; 1013 } 1014 1015 static void 1016 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1017 { 1018 uint8_t split_status[4]; 1019 uint8_t split_status1[4]; 1020 uint8_t sg_split_status[2]; 1021 uint8_t sg_split_status1[2]; 1022 ahd_mode_state saved_modes; 1023 u_int i; 1024 pcireg_t pcix_status; 1025 struct ahd_pci_busdata *bd = ahd->bus_data; 1026 1027 /* 1028 * Check for splits in all modes. Modes 0 and 1 1029 * additionally have SG engine splits to look at. 1030 */ 1031 pcix_status = pci_conf_read(bd->pc, bd->tag, 1032 bd->pcix_off + PCI_PCIX_STATUS); 1033 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1034 ahd_name(ahd), pcix_status); 1035 1036 saved_modes = ahd_save_modes(ahd); 1037 for (i = 0; i < 4; i++) { 1038 ahd_set_modes(ahd, i, i); 1039 1040 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1041 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1042 /* Clear latched errors. So our interrupt deasserts. */ 1043 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1044 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1045 if (i > 1) 1046 continue; 1047 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1048 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1049 /* Clear latched errors. So our interrupt deasserts. */ 1050 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1051 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1052 } 1053 1054 for (i = 0; i < 4; i++) { 1055 u_int bit; 1056 1057 for (bit = 0; bit < 8; bit++) { 1058 1059 if ((split_status[i] & (0x1 << bit)) != 0) { 1060 static const char *s; 1061 1062 s = split_status_strings[bit]; 1063 printf(s, ahd_name(ahd), 1064 split_status_source[i]); 1065 } 1066 1067 if (i > 0) 1068 continue; 1069 1070 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1071 static const char *s; 1072 1073 s = split_status_strings[bit]; 1074 printf(s, ahd_name(ahd), "SG"); 1075 } 1076 } 1077 } 1078 /* 1079 * Clear PCI-X status bits. 1080 */ 1081 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1082 pcix_status); 1083 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1084 ahd_restore_modes(ahd, saved_modes); 1085 } 1086 1087 static int 1088 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1089 { 1090 1091 ahd->chip = AHD_AIC7901; 1092 ahd->features = AHD_AIC7901_FE; 1093 return (ahd_aic790X_setup(ahd, pa)); 1094 } 1095 1096 static int 1097 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1098 { 1099 1100 ahd->chip = AHD_AIC7901A; 1101 ahd->features = AHD_AIC7901A_FE; 1102 return (ahd_aic790X_setup(ahd, pa)); 1103 } 1104 1105 static int 1106 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1107 { 1108 1109 ahd->chip = AHD_AIC7902; 1110 ahd->features = AHD_AIC7902_FE; 1111 return (ahd_aic790X_setup(ahd, pa)); 1112 } 1113 1114 static int 1115 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1116 { 1117 u_int rev; 1118 1119 rev = PCI_REVISION(pa->pa_class); 1120 #ifdef AHD_DEBUG 1121 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1122 #endif 1123 if (rev < ID_AIC7902_PCI_REV_A4) { 1124 aprint_error("%s: Unable to attach to " 1125 "unsupported chip revision %d\n", ahd_name(ahd), rev); 1126 pci_conf_write(pa->pa_pc, pa->pa_tag, 1127 PCI_COMMAND_STATUS_REG, 0); 1128 return (ENXIO); 1129 } 1130 1131 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1132 if (rev < ID_AIC7902_PCI_REV_B0) { 1133 /* 1134 * Enable A series workarounds. 1135 */ 1136 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1137 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1138 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1139 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1140 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1141 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1142 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1143 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1144 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1145 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1146 | AHD_FAINT_LED_BUG; 1147 1148 1149 /* 1150 * IO Cell parameter setup. 1151 */ 1152 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1153 1154 if ((ahd->flags & AHD_HP_BOARD) == 0) 1155 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1156 } else { 1157 u_int devconfig1; 1158 1159 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1160 | AHD_NEW_DFCNTRL_OPTS; 1161 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1162 1163 /* 1164 * Some issues have been resolved in the 7901B. 1165 */ 1166 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1167 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1168 1169 /* 1170 * IO Cell parameter setup. 1171 */ 1172 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1173 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1174 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1175 1176 /* 1177 * Set the PREQDIS bit for H2B which disables some workaround 1178 * that doesn't work on regular PCI busses. 1179 * XXX - Find out exactly what this does from the hardware 1180 * folks! 1181 */ 1182 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1183 pci_conf_write(pa->pa_pc, pa->pa_tag, 1184 DEVCONFIG1, devconfig1|PREQDIS); 1185 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1186 } 1187 1188 return (0); 1189 } 1190