1 /* $NetBSD: ahd_pci.c,v 1.30 2009/09/05 12:59:24 tsutsui Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 49 * - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.30 2009/09/05 12:59:24 tsutsui Exp $"); 54 55 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 56 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 57 58 #include <dev/ic/aic79xx_osm.h> 59 #include <dev/ic/aic79xx_inline.h> 60 61 static inline uint64_t 62 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 63 { 64 uint64_t id; 65 66 id = subvendor 67 | (subdevice << 16) 68 | ((uint64_t)vendor << 32) 69 | ((uint64_t)device << 48); 70 71 return (id); 72 } 73 74 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 75 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 76 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 77 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 78 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 79 80 #define ID_AIC7901 0x800F9005FFFF9005ull 81 #define ID_AHA_29320A 0x8000900500609005ull 82 #define ID_AHA_29320ALP 0x8017900500449005ull 83 84 #define ID_AIC7901A 0x801E9005FFFF9005ull 85 #define ID_AHA_29320LP 0x8014900500449005ull 86 87 #define ID_AIC7902 0x801F9005FFFF9005ull 88 #define ID_AIC7902_B 0x801D9005FFFF9005ull 89 #define ID_AHA_39320 0x8010900500409005ull 90 #define ID_AHA_29320 0x8012900500429005ull 91 #define ID_AHA_29320B 0x8013900500439005ull 92 #define ID_AHA_39320_B 0x8015900500409005ull 93 #define ID_AHA_39320A 0x8016900500409005ull 94 #define ID_AHA_39320D 0x8011900500419005ull 95 #define ID_AHA_39320D_B 0x801C900500419005ull 96 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 97 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 98 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 99 #define ID_AIC7902_PCI_REV_A4 0x3 100 #define ID_AIC7902_PCI_REV_B0 0x10 101 #define SUBID_HP 0x0E11 102 103 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 104 105 #define DEVID_9005_TYPE(id) ((id) & 0xF) 106 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 107 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 108 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 109 110 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 111 112 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 113 114 #define SUBID_9005_TYPE(id) ((id) & 0xF) 115 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 116 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 117 118 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 119 120 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 121 122 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 123 #define SUBID_9005_SEEPTYPE_NONE 0x0 124 #define SUBID_9005_SEEPTYPE_4K 0x1 125 126 static ahd_device_setup_t ahd_aic7901_setup; 127 static ahd_device_setup_t ahd_aic7901A_setup; 128 static ahd_device_setup_t ahd_aic7902_setup; 129 static ahd_device_setup_t ahd_aic790X_setup; 130 131 static struct ahd_pci_identity ahd_pci_ident_table [] = 132 { 133 /* aic7901 based controllers */ 134 { 135 ID_AHA_29320A, 136 ID_ALL_MASK, 137 "Adaptec 29320A Ultra320 SCSI adapter", 138 ahd_aic7901_setup 139 }, 140 { 141 ID_AHA_29320ALP, 142 ID_ALL_MASK, 143 "Adaptec 29320ALP Ultra320 SCSI adapter", 144 ahd_aic7901_setup 145 }, 146 /* aic7901A based controllers */ 147 { 148 ID_AHA_29320LP, 149 ID_ALL_MASK, 150 "Adaptec 29320LP Ultra320 SCSI adapter", 151 ahd_aic7901A_setup 152 }, 153 /* aic7902 based controllers */ 154 { 155 ID_AHA_39320, 156 ID_ALL_MASK, 157 "Adaptec 39320 Ultra320 SCSI adapter", 158 ahd_aic7902_setup 159 }, 160 { 161 ID_AHA_39320_B, 162 ID_ALL_MASK, 163 "Adaptec 39320 Ultra320 SCSI adapter", 164 ahd_aic7902_setup 165 }, 166 { 167 ID_AHA_39320_B_DELL, 168 ID_ALL_IROC_MASK, 169 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 170 ahd_aic7902_setup 171 }, 172 { 173 ID_AHA_39320A, 174 ID_ALL_MASK, 175 "Adaptec 39320A Ultra320 SCSI adapter", 176 ahd_aic7902_setup 177 }, 178 { 179 ID_AHA_39320D, 180 ID_ALL_MASK, 181 "Adaptec 39320D Ultra320 SCSI adapter", 182 ahd_aic7902_setup 183 }, 184 { 185 ID_AHA_39320D_HP, 186 ID_ALL_MASK, 187 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 188 ahd_aic7902_setup 189 }, 190 { 191 ID_AHA_39320D_B, 192 ID_ALL_MASK, 193 "Adaptec 39320D Ultra320 SCSI adapter", 194 ahd_aic7902_setup 195 }, 196 { 197 ID_AHA_39320D_B_HP, 198 ID_ALL_MASK, 199 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 200 ahd_aic7902_setup 201 }, 202 /* Generic chip probes for devices we don't know 'exactly' */ 203 { 204 ID_AIC7901 & ID_9005_GENERIC_MASK, 205 ID_9005_GENERIC_MASK, 206 "Adaptec AIC7901 Ultra320 SCSI adapter", 207 ahd_aic7901_setup 208 }, 209 { 210 ID_AIC7901A & ID_DEV_VENDOR_MASK, 211 ID_DEV_VENDOR_MASK, 212 "Adaptec AIC7901A Ultra320 SCSI adapter", 213 ahd_aic7901A_setup 214 }, 215 { 216 ID_AIC7902 & ID_9005_GENERIC_MASK, 217 ID_9005_GENERIC_MASK, 218 "Adaptec AIC7902 Ultra320 SCSI adapter", 219 ahd_aic7902_setup 220 } 221 }; 222 223 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 224 225 #define DEVCONFIG 0x40 226 #define PCIXINITPAT 0x0000E000ul 227 #define PCIXINIT_PCI33_66 0x0000E000ul 228 #define PCIXINIT_PCIX50_66 0x0000C000ul 229 #define PCIXINIT_PCIX66_100 0x0000A000ul 230 #define PCIXINIT_PCIX100_133 0x00008000ul 231 #define PCI_BUS_MODES_INDEX(devconfig) \ 232 (((devconfig) & PCIXINITPAT) >> 13) 233 234 static const char *pci_bus_modes[] = 235 { 236 "PCI bus mode unknown", 237 "PCI bus mode unknown", 238 "PCI bus mode unknown", 239 "PCI bus mode unknown", 240 "PCI-X 101-133 MHz", 241 "PCI-X 67-100 MHz", 242 "PCI-X 50-66 MHz", 243 "PCI 33 or 66 MHz" 244 }; 245 246 #define TESTMODE 0x00000800ul 247 #define IRDY_RST 0x00000200ul 248 #define FRAME_RST 0x00000100ul 249 #define PCI64BIT 0x00000080ul 250 #define MRDCEN 0x00000040ul 251 #define ENDIANSEL 0x00000020ul 252 #define MIXQWENDIANEN 0x00000008ul 253 #define DACEN 0x00000004ul 254 #define STPWLEVEL 0x00000002ul 255 #define QWENDIANSEL 0x00000001ul 256 257 #define DEVCONFIG1 0x44 258 #define PREQDIS 0x01 259 260 #define LATTIME 0x0000ff00ul 261 262 static int ahd_check_extport(struct ahd_softc *ahd); 263 static void ahd_configure_termination(struct ahd_softc *ahd, 264 u_int adapter_control); 265 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 266 267 static int ahd_pci_test_register_access(struct ahd_softc *); 268 269 static int ahd_pci_intr(struct ahd_softc *); 270 271 static const struct ahd_pci_identity * 272 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 273 { 274 u_int64_t full_id; 275 const struct ahd_pci_identity *entry; 276 u_int i; 277 278 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 279 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 280 281 for (i = 0; i < ahd_num_pci_devs; i++) { 282 entry = &ahd_pci_ident_table[i]; 283 if (entry->full_id == (full_id & entry->id_mask)) 284 return (entry); 285 } 286 return (NULL); 287 } 288 289 static int 290 ahd_pci_probe(device_t parent, cfdata_t match, void *aux) 291 { 292 struct pci_attach_args *pa = aux; 293 const struct ahd_pci_identity *entry; 294 pcireg_t subid; 295 296 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 297 entry = ahd_find_pci_device(pa->pa_id, subid); 298 return entry != NULL ? 1 : 0; 299 } 300 301 static void 302 ahd_pci_attach(device_t parent, device_t self, void *aux) 303 { 304 struct pci_attach_args *pa = aux; 305 struct ahd_softc *ahd = device_private(self); 306 307 const struct ahd_pci_identity *entry; 308 309 uint32_t devconfig; 310 pcireg_t command; 311 int error; 312 pcireg_t subid; 313 uint16_t subvendor; 314 pcireg_t reg; 315 int ioh_valid, ioh2_valid, memh_valid; 316 pcireg_t memtype; 317 pci_intr_handle_t ih; 318 const char *intrstr; 319 struct ahd_pci_busdata *bd; 320 321 ahd_set_name(ahd, device_xname(self)); 322 ahd->parent_dmat = pa->pa_dmat; 323 324 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 325 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 326 entry = ahd_find_pci_device(pa->pa_id, subid); 327 if (entry == NULL) 328 return; 329 330 /* Keep information about the PCI bus */ 331 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 332 if (bd == NULL) { 333 aprint_error("%s: unable to allocate bus-specific data\n", 334 ahd_name(ahd)); 335 return; 336 } 337 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 338 339 bd->pc = pa->pa_pc; 340 bd->tag = pa->pa_tag; 341 bd->func = pa->pa_function; 342 bd->dev = pa->pa_device; 343 344 ahd->bus_data = bd; 345 346 ahd->description = entry->name; 347 348 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 349 M_DEVBUF, M_NOWAIT); 350 if (ahd->seep_config == NULL) { 351 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 352 return; 353 } 354 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 355 356 LIST_INIT(&ahd->pending_scbs); 357 ahd_timer_init(&ahd->reset_timer); 358 ahd_timer_init(&ahd->stat_timer); 359 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 360 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 361 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 362 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 363 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 364 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 365 ahd->int_coalescing_stop_threshold = 366 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 367 368 if (ahd_platform_alloc(ahd, NULL) != 0) { 369 ahd_free(ahd); 370 return; 371 } 372 373 /* 374 * Record if this is an HP board. 375 */ 376 subvendor = PCI_VENDOR(subid); 377 if (subvendor == SUBID_HP) 378 ahd->flags |= AHD_HP_BOARD; 379 380 error = entry->setup(ahd, pa); 381 if (error != 0) 382 return; 383 384 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 385 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 386 ahd->chip |= AHD_PCI; 387 /* Disable PCIX workarounds when running in PCI mode. */ 388 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 389 } else { 390 ahd->chip |= AHD_PCIX; 391 } 392 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 393 394 memh_valid = ioh_valid = ioh2_valid = 0; 395 396 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 397 &bd->pcix_off, NULL)) { 398 if (ahd->chip & AHD_PCIX) 399 aprint_error_dev(self, 400 "warning: can't find PCI-X capability\n"); 401 ahd->chip &= ~AHD_PCIX; 402 ahd->chip |= AHD_PCI; 403 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 404 } 405 406 /* 407 * Map PCI Registers 408 */ 409 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 410 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 411 AHD_PCI_MEMADDR); 412 switch (memtype) { 413 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 414 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 415 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 416 memtype, 0, &ahd->tags[0], 417 &ahd->bshs[0], 418 NULL, NULL) == 0); 419 if (memh_valid) { 420 ahd->tags[1] = ahd->tags[0]; 421 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 422 /*offset*/0x100, 423 /*size*/0x100, 424 &ahd->bshs[1]); 425 if (ahd_pci_test_register_access(ahd) != 0) 426 memh_valid = 0; 427 } 428 break; 429 default: 430 memh_valid = 0; 431 aprint_error("%s: unknown memory type: 0x%x\n", 432 ahd_name(ahd), memtype); 433 break; 434 } 435 436 if (memh_valid) { 437 command &= ~PCI_COMMAND_IO_ENABLE; 438 pci_conf_write(pa->pa_pc, pa->pa_tag, 439 PCI_COMMAND_STATUS_REG, command); 440 } 441 #ifdef AHD_DEBUG 442 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, " 443 "shs0 0x%lx, shs1 0x%lx\n", 444 ahd_name(ahd), ahd->tags[0], ahd->tags[1], 445 ahd->bshs[0], ahd->bshs[1]); 446 #endif 447 } 448 449 if (command & PCI_COMMAND_IO_ENABLE) { 450 /* First BAR */ 451 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 452 PCI_MAPREG_TYPE_IO, 0, 453 &ahd->tags[0], &ahd->bshs[0], 454 NULL, NULL) == 0); 455 456 /* 2nd BAR */ 457 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 458 PCI_MAPREG_TYPE_IO, 0, 459 &ahd->tags[1], &ahd->bshs[1], 460 NULL, NULL) == 0); 461 462 if (ioh_valid && ioh2_valid) { 463 KASSERT(memh_valid == 0); 464 command &= ~PCI_COMMAND_MEM_ENABLE; 465 pci_conf_write(pa->pa_pc, pa->pa_tag, 466 PCI_COMMAND_STATUS_REG, command); 467 } 468 #ifdef AHD_DEBUG 469 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, " 470 "shs0 0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 471 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 472 #endif 473 474 } 475 476 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 477 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 478 return; 479 } 480 481 aprint_normal("\n"); 482 aprint_naive("\n"); 483 484 /* power up chip */ 485 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 486 pci_activate_null)) && error != EOPNOTSUPP) { 487 aprint_error_dev(self, "cannot activate %d\n", error); 488 return; 489 } 490 /* 491 * Should we bother disabling 39Bit addressing 492 * based on installed memory? 493 */ 494 if (sizeof(bus_addr_t) > 4) 495 ahd->flags |= AHD_39BIT_ADDRESSING; 496 497 /* 498 * If we need to support high memory, enable dual 499 * address cycles. This bit must be set to enable 500 * high address bit generation even if we are on a 501 * 64bit bus (PCI64BIT set in devconfig). 502 */ 503 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 504 uint32_t dvconfig; 505 506 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 507 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 508 dvconfig |= DACEN; 509 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig); 510 } 511 512 /* Ensure busmastering is enabled */ 513 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 514 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 515 reg | PCI_COMMAND_MASTER_ENABLE); 516 517 ahd_softc_init(ahd); 518 519 /* 520 * Map the interrupt routines 521 */ 522 ahd->bus_intr = ahd_pci_intr; 523 524 error = ahd_reset(ahd, /*reinit*/FALSE); 525 if (error != 0) { 526 ahd_free(ahd); 527 return; 528 } 529 530 if (pci_intr_map(pa, &ih)) { 531 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 532 ahd_free(ahd); 533 return; 534 } 535 intrstr = pci_intr_string(pa->pa_pc, ih); 536 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 537 if (ahd->ih == NULL) { 538 aprint_error("%s: couldn't establish interrupt", 539 ahd_name(ahd)); 540 if (intrstr != NULL) 541 aprint_error(" at %s", intrstr); 542 aprint_error("\n"); 543 ahd_free(ahd); 544 return; 545 } 546 if (intrstr != NULL) 547 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 548 intrstr); 549 550 /* Get the size of the cache */ 551 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 552 ahd->pci_cachesize *= 4; 553 554 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 555 /* See if we have a SEEPROM and perform auto-term */ 556 error = ahd_check_extport(ahd); 557 if (error != 0) 558 return; 559 560 /* Core initialization */ 561 error = ahd_init(ahd); 562 if (error != 0) 563 return; 564 565 /* 566 * Link this softc in with all other ahd instances. 567 */ 568 ahd_attach(ahd); 569 } 570 571 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 572 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 573 574 /* 575 * Perform some simple tests that should catch situations where 576 * our registers are invalidly mapped. 577 */ 578 static int 579 ahd_pci_test_register_access(struct ahd_softc *ahd) 580 { 581 uint32_t cmd; 582 struct ahd_pci_busdata *bd = ahd->bus_data; 583 u_int targpcistat; 584 uint32_t pci_status1; 585 int error; 586 uint8_t hcntrl; 587 588 error = EIO; 589 590 /* 591 * Enable PCI error interrupt status, but suppress NMIs 592 * generated by SERR raised due to target aborts. 593 */ 594 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 595 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 596 cmd & ~PCI_COMMAND_SERR_ENABLE); 597 598 /* 599 * First a simple test to see if any 600 * registers can be read. Reading 601 * HCNTRL has no side effects and has 602 * at least one bit that is guaranteed to 603 * be zero so it is a good register to 604 * use for this test. 605 */ 606 hcntrl = ahd_inb(ahd, HCNTRL); 607 if (hcntrl == 0xFF) 608 goto fail; 609 610 /* 611 * Next create a situation where write combining 612 * or read prefetching could be initiated by the 613 * CPU or host bridge. Our device does not support 614 * either, so look for data corruption and/or flaged 615 * PCI errors. First pause without causing another 616 * chip reset. 617 */ 618 hcntrl &= ~CHIPRST; 619 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 620 while (ahd_is_paused(ahd) == 0) 621 ; 622 623 /* Clear any PCI errors that occurred before our driver attached. */ 624 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 625 targpcistat = ahd_inb(ahd, TARGPCISTAT); 626 ahd_outb(ahd, TARGPCISTAT, targpcistat); 627 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 628 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 629 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 630 ahd_outb(ahd, CLRINT, CLRPCIINT); 631 632 ahd_outb(ahd, SEQCTL0, PERRORDIS); 633 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 634 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 635 goto fail; 636 637 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 638 u_int trgpcistat; 639 640 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 641 trgpcistat = ahd_inb(ahd, TARGPCISTAT); 642 if ((trgpcistat & STA) != 0) 643 goto fail; 644 } 645 646 error = 0; 647 648 fail: 649 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 650 651 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 652 targpcistat = ahd_inb(ahd, TARGPCISTAT); 653 654 /* Silently clear any latched errors. */ 655 ahd_outb(ahd, TARGPCISTAT, targpcistat); 656 pci_status1 = pci_conf_read(bd->pc, bd->tag, 657 PCI_COMMAND_STATUS_REG); 658 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 659 pci_status1); 660 ahd_outb(ahd, CLRINT, CLRPCIINT); 661 } 662 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 663 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 664 return (error); 665 } 666 667 /* 668 * Check the external port logic for a serial eeprom 669 * and termination/cable detection contrls. 670 */ 671 static int 672 ahd_check_extport(struct ahd_softc *ahd) 673 { 674 struct vpd_config vpd; 675 struct seeprom_config *sc; 676 u_int adapter_control; 677 int have_seeprom; 678 int error; 679 680 sc = ahd->seep_config; 681 have_seeprom = ahd_acquire_seeprom(ahd); 682 if (have_seeprom) { 683 u_int start_addr; 684 685 /* 686 * Fetch VPD for this function and parse it. 687 */ 688 #ifdef AHD_DEBUG 689 printf("%s: Reading VPD from SEEPROM...", 690 ahd_name(ahd)); 691 #endif 692 /* Address is always in units of 16bit words */ 693 start_addr = ((2 * sizeof(*sc)) 694 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 695 696 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 697 start_addr, sizeof(vpd)/2, 698 /*bytestream*/TRUE); 699 if (error == 0) 700 error = ahd_parse_vpddata(ahd, &vpd); 701 #ifdef AHD_DEBUG 702 printf("%s: VPD parsing %s\n", 703 ahd_name(ahd), 704 error == 0 ? "successful" : "failed"); 705 #endif 706 707 #ifdef AHD_DEBUG 708 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 709 #endif 710 711 /* Address is always in units of 16bit words */ 712 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 713 714 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 715 start_addr, sizeof(*sc)/2, 716 /*bytestream*/FALSE); 717 718 if (error != 0) { 719 #ifdef AHD_DEBUG 720 printf("Unable to read SEEPROM\n"); 721 #endif 722 have_seeprom = 0; 723 } else { 724 have_seeprom = ahd_verify_cksum(sc); 725 #ifdef AHD_DEBUG 726 if (have_seeprom == 0) 727 printf ("checksum error\n"); 728 else 729 printf ("done.\n"); 730 #endif 731 } 732 ahd_release_seeprom(ahd); 733 } 734 735 if (!have_seeprom) { 736 u_int nvram_scb; 737 738 /* 739 * Pull scratch ram settings and treat them as 740 * if they are the contents of an seeprom if 741 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 742 * in SCB 0xFF. We manually compose the data as 16bit 743 * values to avoid endian issues. 744 */ 745 ahd_set_scbptr(ahd, 0xFF); 746 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 747 if (nvram_scb != 0xFF 748 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 749 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 750 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 751 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 752 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 753 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 754 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 755 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 756 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 757 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 758 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 759 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 760 uint16_t *sc_data; 761 int i; 762 763 ahd_set_scbptr(ahd, nvram_scb); 764 sc_data = (uint16_t *)sc; 765 for (i = 0; i < 64; i += 2) 766 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 767 have_seeprom = ahd_verify_cksum(sc); 768 if (have_seeprom) 769 ahd->flags |= AHD_SCB_CONFIG_USED; 770 } 771 } 772 773 #ifdef AHD_DEBUG 774 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 775 uint16_t *sc_data; 776 int i; 777 778 printf("%s: Seeprom Contents:", ahd_name(ahd)); 779 sc_data = (uint16_t *)sc; 780 for (i = 0; i < (sizeof(*sc)); i += 2) 781 printf("\n\t0x%.4x", sc_data[i]); 782 printf("\n"); 783 } 784 #endif 785 786 if (!have_seeprom) { 787 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 788 ahd->flags |= AHD_USEDEFAULTS; 789 error = ahd_default_config(ahd); 790 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 791 free(ahd->seep_config, M_DEVBUF); 792 ahd->seep_config = NULL; 793 } else { 794 error = ahd_parse_cfgdata(ahd, sc); 795 adapter_control = sc->adapter_control; 796 } 797 if (error != 0) 798 return (error); 799 800 ahd_configure_termination(ahd, adapter_control); 801 802 return (0); 803 } 804 805 static void 806 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 807 { 808 int error; 809 u_int sxfrctl1; 810 uint8_t termctl; 811 uint32_t devconfig; 812 struct ahd_pci_busdata *bd = ahd->bus_data; 813 814 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 815 devconfig &= ~STPWLEVEL; 816 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 817 devconfig |= STPWLEVEL; 818 #ifdef AHD_DEBUG 819 printf("%s: STPWLEVEL is %s\n", 820 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 821 #endif 822 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 823 824 /* Make sure current sensing is off. */ 825 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 826 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 827 } 828 829 /* 830 * Read to sense. Write to set. 831 */ 832 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 833 if ((adapter_control & CFAUTOTERM) == 0) { 834 if (bootverbose) 835 printf("%s: Manual Primary Termination\n", 836 ahd_name(ahd)); 837 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 838 if ((adapter_control & CFSTERM) != 0) 839 termctl |= FLX_TERMCTL_ENPRILOW; 840 if ((adapter_control & CFWSTERM) != 0) 841 termctl |= FLX_TERMCTL_ENPRIHIGH; 842 } else if (error != 0) { 843 if (bootverbose) 844 printf("%s: Primary Auto-Term Sensing failed! " 845 "Using Defaults.\n", ahd_name(ahd)); 846 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 847 } 848 849 if ((adapter_control & CFSEAUTOTERM) == 0) { 850 if (bootverbose) 851 printf("%s: Manual Secondary Termination\n", 852 ahd_name(ahd)); 853 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 854 if ((adapter_control & CFSELOWTERM) != 0) 855 termctl |= FLX_TERMCTL_ENSECLOW; 856 if ((adapter_control & CFSEHIGHTERM) != 0) 857 termctl |= FLX_TERMCTL_ENSECHIGH; 858 } else if (error != 0) { 859 if (bootverbose) 860 printf("%s: Secondary Auto-Term Sensing failed! " 861 "Using Defaults.\n", ahd_name(ahd)); 862 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 863 } 864 865 /* 866 * Now set the termination based on what we found. 867 */ 868 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 869 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 870 ahd->flags |= AHD_TERM_ENB_A; 871 sxfrctl1 |= STPWEN; 872 } 873 /* Must set the latch once in order to be effective. */ 874 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 875 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 876 877 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 878 if (error != 0) { 879 aprint_error("%s: Unable to set termination settings!\n", 880 ahd_name(ahd)); 881 } else { 882 if (bootverbose) { 883 printf("%s: Primary High byte termination %sabled\n", 884 ahd_name(ahd), 885 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 886 887 printf("%s: Primary Low byte termination %sabled\n", 888 ahd_name(ahd), 889 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 890 891 printf("%s: Secondary High byte termination %sabled\n", 892 ahd_name(ahd), 893 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 894 895 printf("%s: Secondary Low byte termination %sabled\n", 896 ahd_name(ahd), 897 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 898 } 899 } 900 return; 901 } 902 903 #define DPE 0x80 904 #define SSE 0x40 905 #define RMA 0x20 906 #define RTA 0x10 907 #define STA 0x08 908 #define DPR 0x01 909 910 static const char *split_status_source[] = 911 { 912 "DFF0", 913 "DFF1", 914 "OVLY", 915 "CMC", 916 }; 917 918 static const char *pci_status_source[] = 919 { 920 "DFF0", 921 "DFF1", 922 "SG", 923 "CMC", 924 "OVLY", 925 "NONE", 926 "MSI", 927 "TARG" 928 }; 929 930 static const char *split_status_strings[] = 931 { 932 "%s: Received split response in %s.\n", 933 "%s: Received split completion error message in %s\n", 934 "%s: Receive overrun in %s\n", 935 "%s: Count not complete in %s\n", 936 "%s: Split completion data bucket in %s\n", 937 "%s: Split completion address error in %s\n", 938 "%s: Split completion byte count error in %s\n", 939 "%s: Signaled Target-abort to early terminate a split in %s\n" 940 }; 941 942 static const char *pci_status_strings[] = 943 { 944 "%s: Data Parity Error has been reported via PERR# in %s\n", 945 "%s: Target initial wait state error in %s\n", 946 "%s: Split completion read data parity error in %s\n", 947 "%s: Split completion address attribute parity error in %s\n", 948 "%s: Received a Target Abort in %s\n", 949 "%s: Received a Master Abort in %s\n", 950 "%s: Signal System Error Detected in %s\n", 951 "%s: Address or Write Phase Parity Error Detected in %s.\n" 952 }; 953 954 static int 955 ahd_pci_intr(struct ahd_softc *ahd) 956 { 957 uint8_t pci_status[8]; 958 ahd_mode_state saved_modes; 959 u_int pci_status1; 960 u_int intstat; 961 u_int i; 962 u_int reg; 963 struct ahd_pci_busdata *bd = ahd->bus_data; 964 965 intstat = ahd_inb(ahd, INTSTAT); 966 967 if ((intstat & SPLTINT) != 0) 968 ahd_pci_split_intr(ahd, intstat); 969 970 if ((intstat & PCIINT) == 0) 971 return 0; 972 973 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 974 saved_modes = ahd_save_modes(ahd); 975 ahd_dump_card_state(ahd); 976 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 977 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 978 979 if (i == 5) 980 continue; 981 pci_status[i] = ahd_inb(ahd, reg); 982 /* Clear latched errors. So our interrupt deasserts. */ 983 ahd_outb(ahd, reg, pci_status[i]); 984 } 985 986 for (i = 0; i < 8; i++) { 987 u_int bit; 988 989 if (i == 5) 990 continue; 991 992 for (bit = 0; bit < 8; bit++) { 993 994 if ((pci_status[i] & (0x1 << bit)) != 0) { 995 static const char *s; 996 997 s = pci_status_strings[bit]; 998 if (i == 7/*TARG*/ && bit == 3) 999 s = "%s: Signaled Target Abort\n"; 1000 printf(s, ahd_name(ahd), pci_status_source[i]); 1001 } 1002 } 1003 } 1004 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1005 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1006 1007 ahd_restore_modes(ahd, saved_modes); 1008 ahd_outb(ahd, CLRINT, CLRPCIINT); 1009 ahd_unpause(ahd); 1010 1011 return 1; 1012 } 1013 1014 static void 1015 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1016 { 1017 uint8_t split_status[4]; 1018 uint8_t split_status1[4]; 1019 uint8_t sg_split_status[2]; 1020 uint8_t sg_split_status1[2]; 1021 ahd_mode_state saved_modes; 1022 u_int i; 1023 pcireg_t pcix_status; 1024 struct ahd_pci_busdata *bd = ahd->bus_data; 1025 1026 /* 1027 * Check for splits in all modes. Modes 0 and 1 1028 * additionally have SG engine splits to look at. 1029 */ 1030 pcix_status = pci_conf_read(bd->pc, bd->tag, 1031 bd->pcix_off + PCI_PCIX_STATUS); 1032 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1033 ahd_name(ahd), pcix_status); 1034 1035 saved_modes = ahd_save_modes(ahd); 1036 for (i = 0; i < 4; i++) { 1037 ahd_set_modes(ahd, i, i); 1038 1039 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1040 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1041 /* Clear latched errors. So our interrupt deasserts. */ 1042 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1043 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1044 if (i > 1) 1045 continue; 1046 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1047 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1048 /* Clear latched errors. So our interrupt deasserts. */ 1049 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1050 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1051 } 1052 1053 for (i = 0; i < 4; i++) { 1054 u_int bit; 1055 1056 for (bit = 0; bit < 8; bit++) { 1057 1058 if ((split_status[i] & (0x1 << bit)) != 0) { 1059 static const char *s; 1060 1061 s = split_status_strings[bit]; 1062 printf(s, ahd_name(ahd), 1063 split_status_source[i]); 1064 } 1065 1066 if (i > 0) 1067 continue; 1068 1069 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1070 static const char *s; 1071 1072 s = split_status_strings[bit]; 1073 printf(s, ahd_name(ahd), "SG"); 1074 } 1075 } 1076 } 1077 /* 1078 * Clear PCI-X status bits. 1079 */ 1080 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1081 pcix_status); 1082 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1083 ahd_restore_modes(ahd, saved_modes); 1084 } 1085 1086 static int 1087 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1088 { 1089 1090 ahd->chip = AHD_AIC7901; 1091 ahd->features = AHD_AIC7901_FE; 1092 return (ahd_aic790X_setup(ahd, pa)); 1093 } 1094 1095 static int 1096 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1097 { 1098 1099 ahd->chip = AHD_AIC7901A; 1100 ahd->features = AHD_AIC7901A_FE; 1101 return (ahd_aic790X_setup(ahd, pa)); 1102 } 1103 1104 static int 1105 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1106 { 1107 1108 ahd->chip = AHD_AIC7902; 1109 ahd->features = AHD_AIC7902_FE; 1110 return (ahd_aic790X_setup(ahd, pa)); 1111 } 1112 1113 static int 1114 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1115 { 1116 u_int rev; 1117 1118 rev = PCI_REVISION(pa->pa_class); 1119 #ifdef AHD_DEBUG 1120 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1121 #endif 1122 if (rev < ID_AIC7902_PCI_REV_A4) { 1123 aprint_error("%s: Unable to attach to " 1124 "unsupported chip revision %d\n", ahd_name(ahd), rev); 1125 pci_conf_write(pa->pa_pc, pa->pa_tag, 1126 PCI_COMMAND_STATUS_REG, 0); 1127 return (ENXIO); 1128 } 1129 1130 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1131 if (rev < ID_AIC7902_PCI_REV_B0) { 1132 /* 1133 * Enable A series workarounds. 1134 */ 1135 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1136 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1137 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1138 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1139 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1140 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1141 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1142 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1143 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1144 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1145 | AHD_FAINT_LED_BUG; 1146 1147 1148 /* 1149 * IO Cell parameter setup. 1150 */ 1151 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1152 1153 if ((ahd->flags & AHD_HP_BOARD) == 0) 1154 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1155 } else { 1156 u_int devconfig1; 1157 1158 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1159 | AHD_NEW_DFCNTRL_OPTS; 1160 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1161 1162 /* 1163 * Some issues have been resolved in the 7901B. 1164 */ 1165 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1166 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1167 1168 /* 1169 * IO Cell parameter setup. 1170 */ 1171 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1172 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1173 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1174 1175 /* 1176 * Set the PREQDIS bit for H2B which disables some workaround 1177 * that doesn't work on regular PCI busses. 1178 * XXX - Find out exactly what this does from the hardware 1179 * folks! 1180 */ 1181 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1182 pci_conf_write(pa->pa_pc, pa->pa_tag, 1183 DEVCONFIG1, devconfig1|PREQDIS); 1184 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1185 } 1186 1187 return (0); 1188 } 1189