1 /* $NetBSD: ahcisata_pci.c,v 1.26 2011/08/06 14:56:33 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.26 2011/08/06 14:56:33 jakllsch Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/pmf.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/ic/ahcisatavar.h> 44 45 struct ahci_pci_quirk { 46 pci_vendor_id_t vendor; /* Vendor ID */ 47 pci_product_id_t product; /* Product ID */ 48 int quirks; /* quirks; see below */ 49 }; 50 51 #define AHCI_PCI_QUIRK_FORCE __BIT(0) /* force attach */ 52 #define AHCI_PCI_QUIRK_BAD64 __BIT(1) /* broken 64-bit DMA */ 53 54 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 55 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 56 AHCI_PCI_QUIRK_FORCE }, 57 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 58 AHCI_PCI_QUIRK_FORCE }, 59 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 60 AHCI_PCI_QUIRK_FORCE }, 61 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 62 AHCI_PCI_QUIRK_FORCE }, 63 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 64 AHCI_PCI_QUIRK_FORCE }, 65 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 66 AHCI_PCI_QUIRK_FORCE }, 67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 68 AHCI_PCI_QUIRK_FORCE }, 69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 70 AHCI_PCI_QUIRK_FORCE }, 71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 72 AHCI_PCI_QUIRK_FORCE }, 73 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 74 AHCI_PCI_QUIRK_FORCE }, 75 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 76 AHCI_PCI_QUIRK_FORCE }, 77 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 78 AHCI_PCI_QUIRK_FORCE }, 79 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 80 AHCI_PCI_QUIRK_FORCE }, 81 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 82 AHCI_PCI_QUIRK_FORCE }, 83 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 84 AHCI_PCI_QUIRK_FORCE }, 85 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 86 AHCI_PCI_QUIRK_FORCE }, 87 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 88 AHCI_PCI_QUIRK_FORCE }, 89 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 90 AHCI_PCI_QUIRK_FORCE }, 91 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288, 92 AHCI_PCI_QUIRK_FORCE }, 93 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 94 AHCI_PCI_QUIRK_FORCE }, 95 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE9128, 96 AHCI_PCI_QUIRK_FORCE }, 97 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 98 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 99 AHCI_PCI_QUIRK_BAD64 }, 100 }; 101 102 struct ahci_pci_softc { 103 struct ahci_softc ah_sc; 104 pci_chipset_tag_t sc_pc; 105 pcitag_t sc_pcitag; 106 void * sc_ih; 107 }; 108 109 static bool ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t, int); 110 static int ahci_pci_match(device_t, cfdata_t, void *); 111 static void ahci_pci_attach(device_t, device_t, void *); 112 static int ahci_pci_detach(device_t, int); 113 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 114 115 116 CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 117 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL); 118 119 static bool 120 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product, int quirk) 121 { 122 int i; 123 124 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 125 if (vendor == ahci_pci_quirks[i].vendor && 126 product == ahci_pci_quirks[i].product) 127 return (ahci_pci_quirks[i].quirks & quirk) != 0; 128 return false; 129 } 130 131 static int 132 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa = aux; 135 bus_space_tag_t regt; 136 bus_space_handle_t regh; 137 bus_size_t size; 138 int ret = 0; 139 bool force; 140 141 force = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 142 PCI_PRODUCT(pa->pa_id), 143 AHCI_PCI_QUIRK_FORCE); 144 145 /* if wrong class and not forced by quirks, don't match */ 146 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 147 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 148 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 149 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 150 (force == false)) 151 return 0; 152 153 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 154 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 155 ®t, ®h, NULL, &size) != 0) 156 return 0; 157 158 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 159 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 160 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 161 (force == true)) 162 ret = 3; 163 164 bus_space_unmap(regt, regh, size); 165 return ret; 166 } 167 168 static void 169 ahci_pci_attach(device_t parent, device_t self, void *aux) 170 { 171 struct pci_attach_args *pa = aux; 172 struct ahci_pci_softc *psc = device_private(self); 173 struct ahci_softc *sc = &psc->ah_sc; 174 char devinfo[256]; 175 const char *intrstr; 176 bool ahci_cap_64bit; 177 bool ahci_bad_64bit; 178 pci_intr_handle_t intrhandle; 179 180 sc->sc_atac.atac_dev = self; 181 182 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 183 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 184 &sc->sc_ahcit, &sc->sc_ahcih, NULL, &sc->sc_ahcis) != 0) { 185 aprint_error_dev(self, "can't map ahci registers\n"); 186 return; 187 } 188 psc->sc_pc = pa->pa_pc; 189 psc->sc_pcitag = pa->pa_tag; 190 191 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 192 aprint_naive(": AHCI disk controller\n"); 193 aprint_normal(": %s\n", devinfo); 194 195 if (pci_intr_map(pa, &intrhandle) != 0) { 196 aprint_error_dev(self, "couldn't map interrupt\n"); 197 return; 198 } 199 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 200 psc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc); 201 if (psc->sc_ih == NULL) { 202 aprint_error_dev(self, "couldn't establish interrupt\n"); 203 return; 204 } 205 aprint_normal_dev(self, "interrupting at %s\n", 206 intrstr ? intrstr : "unknown interrupt"); 207 208 sc->sc_dmat = pa->pa_dmat; 209 210 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 211 ahci_bad_64bit = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 212 PCI_PRODUCT(pa->pa_id), 213 AHCI_PCI_QUIRK_BAD64); 214 215 if (pci_dma64_available(pa) && ahci_cap_64bit) { 216 if (!ahci_bad_64bit) 217 sc->sc_dmat = pa->pa_dmat64; 218 aprint_verbose_dev(self, "64-bit DMA%s\n", 219 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 220 } 221 222 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 223 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 224 sc->sc_atac_capflags = ATAC_CAP_RAID; 225 } else { 226 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 227 } 228 229 ahci_attach(sc); 230 231 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 232 aprint_error_dev(self, "couldn't establish power handler\n"); 233 } 234 235 static int 236 ahci_pci_detach(device_t dv, int flags) 237 { 238 struct ahci_pci_softc *psc; 239 struct ahci_softc *sc; 240 int rv; 241 242 psc = device_private(dv); 243 sc = &psc->ah_sc; 244 245 if ((rv = ahci_detach(sc, flags))) 246 return rv; 247 248 pmf_device_deregister(dv); 249 250 if (psc->sc_ih != NULL) 251 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 252 253 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 254 255 return 0; 256 } 257 258 static bool 259 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 260 { 261 struct ahci_pci_softc *psc = device_private(dv); 262 struct ahci_softc *sc = &psc->ah_sc; 263 int s; 264 265 s = splbio(); 266 ahci_resume(sc); 267 splx(s); 268 269 return true; 270 } 271