1 /* $NetBSD: agpreg.h,v 1.7 2004/02/04 06:58:24 soren Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $ 29 */ 30 31 #ifndef _PCI_AGPREG_H_ 32 #define _PCI_AGPREG_H_ 33 34 /* 35 * Offsets for various AGP configuration registers. 36 */ 37 #define AGP_APBASE 0x10 38 39 #define AGP_STATUS 0x4 40 #define AGP_COMMAND 0x8 41 42 /* 43 * Config registers for Intel AGP chipsets. 44 */ 45 /* i845/855PM */ 46 #define AGP_I845_AGPMISC 0x51 47 # define AGPMISC_AAGN (1U << 1) /* Aperture AccessEN */ 48 49 /* i840/850/850E */ 50 #define AGP_I840_MCHCFG 0x50 51 # define MCHCFG_AAGN (1U << 9) /* Aperture AccessEN */ 52 53 /* i82443LX/BX/GX */ 54 #define AGP_INTEL_NBXCFG 0x50 55 # define NBXCFG_APAE (1U << 10) /* AGPtoPCI AccessDIS */ 56 # define NBXCFG_AAGN (1U << 9) /* Aperture AccessEN */ 57 58 /* Error Status for i8XX Chipset */ 59 #define AGP_INTEL_I8XX_ERRSTS 0xc8 60 61 /* Common register */ 62 #define AGP_INTEL_ERRSTS 0x91 /* Not i8XX */ 63 #define AGP_INTEL_AGPCMD 0xa8 64 # define AGPCMD_SBA (1U << 9) 65 # define AGPCMD_AGPEN (1U << 8) 66 # define AGPCMD_FWEN (1U << 4) 67 # define AGPCMD_RATE_1X (1U << 1) 68 # define AGPCMD_RATE_2X (1U << 2) 69 # define AGPCMD_RATE_4X (1U << 3) 70 71 #define AGP_INTEL_AGPCTRL 0xb0 72 # define AGPCTRL_AGPRSE (1U << 13) /* AGPRSE (82443 only)*/ 73 # define AGPCTRL_GTLB (1U << 7) /* GTLB EN */ 74 75 #define AGP_INTEL_APSIZE 0xb4 76 # define APSIZE_MASK 0x3f 77 78 #define AGP_INTEL_ATTBASE 0xb8 79 80 /* 81 * Config offsets for VIA AGP chipsets. 82 */ 83 #define AGP_VIA_GARTCTRL 0x80 84 #define AGP_VIA_APSIZE 0x84 85 #define AGP_VIA_ATTBASE 0x88 86 87 /* 88 * Config offsets for SiS AGP chipsets. 89 */ 90 #define AGP_SIS_ATTBASE 0x90 91 #define AGP_SIS_WINCTRL 0x94 92 #define AGP_SIS_TLBCTRL 0x97 93 #define AGP_SIS_TLBFLUSH 0x98 94 95 /* 96 * Config offsets for Ali AGP chipsets. 97 */ 98 #define AGP_ALI_AGPCTRL 0xb8 99 #define AGP_ALI_ATTBASE 0xbc 100 #define AGP_ALI_TLBCTRL 0xc0 101 102 /* 103 * Config offsets for the AMD 751 chipset. 104 */ 105 #define AGP_AMD751_REGISTERS 0x14 106 #define AGP_AMD751_APCTRL 0xac 107 #define AGP_AMD751_MODECTRL 0xb0 108 #define AGP_AMD751_MODECTRL_SYNEN 0x80 109 #define AGP_AMD751_MODECTRL2 0xb2 110 #define AGP_AMD751_MODECTRL2_G1LM 0x01 111 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 112 #define AGP_AMD751_MODECTRL2_NGSE 0x08 113 114 /* 115 * Memory mapped register offsets for AMD 751 chipset. 116 */ 117 #define AGP_AMD751_CAPS 0x00 118 #define AGP_AMD751_CAPS_EHI 0x0800 119 #define AGP_AMD751_CAPS_P2P 0x0400 120 #define AGP_AMD751_CAPS_MPC 0x0200 121 #define AGP_AMD751_CAPS_VBE 0x0100 122 #define AGP_AMD751_CAPS_REV 0x00ff 123 #define AGP_AMD751_STATUS 0x02 124 #define AGP_AMD751_STATUS_P2PS 0x0800 125 #define AGP_AMD751_STATUS_GCS 0x0400 126 #define AGP_AMD751_STATUS_MPS 0x0200 127 #define AGP_AMD751_STATUS_VBES 0x0100 128 #define AGP_AMD751_STATUS_P2PE 0x0008 129 #define AGP_AMD751_STATUS_GCE 0x0004 130 #define AGP_AMD751_STATUS_VBEE 0x0001 131 #define AGP_AMD751_ATTBASE 0x04 132 #define AGP_AMD751_TLBCTRL 0x0c 133 134 /* 135 * Config registers for i810 device 0 136 */ 137 #define AGP_I810_SMRAM 0x70 138 #define AGP_I810_SMRAM_GMS 0xc0 139 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 140 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 141 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 142 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 143 #define AGP_I810_MISCC 0x72 144 #define AGP_I810_MISCC_WINSIZE 0x0001 145 #define AGP_I810_MISCC_WINSIZE_64 0x0000 146 #define AGP_I810_MISCC_WINSIZE_32 0x0001 147 #define AGP_I810_MISCC_PLCK 0x0008 148 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 149 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 150 #define AGP_I810_MISCC_WPTC 0x0030 151 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 152 #define AGP_I810_MISCC_WPTC_62 0x0010 153 #define AGP_I810_MISCC_WPTC_50 0x0020 154 #define AGP_I810_MISCC_WPTC_37 0x0030 155 #define AGP_I810_MISCC_RPTC 0x00c0 156 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 157 #define AGP_I810_MISCC_RPTC_62 0x0040 158 #define AGP_I810_MISCC_RPTC_50 0x0080 159 #define AGP_I810_MISCC_RPTC_37 0x00c0 160 161 /* 162 * Config registers for i810 device 1 163 */ 164 #define AGP_I810_GMADR 0x10 165 #define AGP_I810_MMADR 0x14 166 167 /* 168 * Memory mapped register offsets for i810 chipset. 169 */ 170 #define AGP_I810_PGTBL_CTL 0x2020 171 #define AGP_I810_DRT 0x3000 172 #define AGP_I810_DRT_UNPOPULATED 0x00 173 #define AGP_I810_DRT_POPULATED 0x01 174 #define AGP_I810_GTT 0x10000 175 176 /* 177 * Config registers for i830MG device 0 178 */ 179 #define AGP_I830_GCC0 0x50 180 #define AGP_I830_GCC1 0x52 181 #define AGP_I830_GCC1_DEV2 0x08 182 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 183 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 184 #define AGP_I830_GCC1_GMS 0x70 185 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 186 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 187 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 188 #define AGP_I830_GCC1_GMASIZE 0x01 189 #define AGP_I830_GCC1_GMASIZE_64 0x01 190 #define AGP_I830_GCC1_GMASIZE_128 0x00 191 192 193 /* 194 * Config registers for 852GM/855GM/865G device 0 195 */ 196 #define AGP_I855_GCC1 0x52 197 #define AGP_I855_GCC1_DEV2 0x08 198 #define AGP_I855_GCC1_DEV2_ENABLED 0x00 199 #define AGP_I855_GCC1_DEV2_DISABLED 0x08 200 #define AGP_I855_GCC1_GMS 0x70 201 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 202 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 203 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 204 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 205 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 206 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 207 208 #endif /* !_PCI_AGPREG_H_ */ 209