1 /* $NetBSD: agp_intel.c,v 1.20 2006/10/12 01:31:27 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.20 2006/10/12 01:31:27 christos Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 #include <sys/agpio.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/agpvar.h> 50 #include <dev/pci/agpreg.h> 51 52 #include <machine/bus.h> 53 54 struct agp_intel_softc { 55 u_int32_t initial_aperture; 56 /* aperture size at startup */ 57 struct agp_gatt *gatt; 58 struct pci_attach_args vga_pa; 59 u_int aperture_mask; 60 int chiptype; /* Chip type */ 61 #define CHIP_INTEL 0x0 62 #define CHIP_I443 0x1 63 #define CHIP_I840 0x2 64 #define CHIP_I845 0x3 65 #define CHIP_I850 0x4 66 #define CHIP_I865 0x5 67 68 void *sc_powerhook; 69 struct pci_conf_state sc_pciconf; 70 }; 71 72 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 73 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 74 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 75 static int agp_intel_unbind_page(struct agp_softc *, off_t); 76 static void agp_intel_flush_tlb(struct agp_softc *); 77 static void agp_intel_powerhook(int, void *); 78 79 static struct agp_methods agp_intel_methods = { 80 agp_intel_get_aperture, 81 agp_intel_set_aperture, 82 agp_intel_bind_page, 83 agp_intel_unbind_page, 84 agp_intel_flush_tlb, 85 agp_generic_enable, 86 agp_generic_alloc_memory, 87 agp_generic_free_memory, 88 agp_generic_bind_memory, 89 agp_generic_unbind_memory, 90 }; 91 92 static int 93 agp_intel_vgamatch(struct pci_attach_args *pa) 94 { 95 switch (PCI_PRODUCT(pa->pa_id)) { 96 case PCI_PRODUCT_INTEL_82855PM_AGP: 97 case PCI_PRODUCT_INTEL_82443LX_AGP: 98 case PCI_PRODUCT_INTEL_82443BX_AGP: 99 case PCI_PRODUCT_INTEL_82443GX_AGP: 100 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 101 case PCI_PRODUCT_INTEL_82845_AGP: 102 case PCI_PRODUCT_INTEL_82840_AGP: 103 case PCI_PRODUCT_INTEL_82865_AGP: 104 case PCI_PRODUCT_INTEL_82875P_AGP: 105 return (1); 106 } 107 108 return (0); 109 } 110 111 int 112 agp_intel_attach(struct device *parent __unused, struct device *self, void *aux) 113 { 114 struct agp_softc *sc = (struct agp_softc *)self; 115 struct pci_attach_args *pa= aux; 116 struct agp_intel_softc *isc; 117 struct agp_gatt *gatt; 118 pcireg_t reg; 119 u_int32_t value; 120 121 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 122 if (isc == NULL) { 123 aprint_error(": can't allocate chipset-specific softc\n"); 124 return ENOMEM; 125 } 126 127 sc->as_methods = &agp_intel_methods; 128 sc->as_chipc = isc; 129 130 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 131 aprint_normal(": using generic initialization for Intel AGP\n"); 132 aprint_normal("%s", sc->as_dev.dv_xname); 133 isc->chiptype = CHIP_INTEL; 134 } 135 136 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 137 NULL); 138 139 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 140 aprint_error(": can't map aperture\n"); 141 free(isc, M_AGP); 142 sc->as_chipc = NULL; 143 return ENXIO; 144 } 145 146 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 147 case PCI_PRODUCT_INTEL_82443LX_AGP: 148 case PCI_PRODUCT_INTEL_82443BX_AGP: 149 case PCI_PRODUCT_INTEL_82443GX_AGP: 150 isc->chiptype = CHIP_I443; 151 break; 152 case PCI_PRODUCT_INTEL_82840_AGP: 153 isc->chiptype = CHIP_I840; 154 break; 155 case PCI_PRODUCT_INTEL_82855PM_AGP: 156 case PCI_PRODUCT_INTEL_82845_AGP: 157 isc->chiptype = CHIP_I845; 158 break; 159 case PCI_PRODUCT_INTEL_82850_AGP: 160 isc->chiptype = CHIP_I850; 161 break; 162 case PCI_PRODUCT_INTEL_82865_AGP: 163 case PCI_PRODUCT_INTEL_82875P_AGP: 164 isc->chiptype = CHIP_I865; 165 break; 166 } 167 168 /* Determine maximum supported aperture size. */ 169 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 170 pci_conf_write(sc->as_pc, sc->as_tag, 171 AGP_INTEL_APSIZE, APSIZE_MASK); 172 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 173 AGP_INTEL_APSIZE) & APSIZE_MASK; 174 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 175 isc->initial_aperture = AGP_GET_APERTURE(sc); 176 177 for (;;) { 178 gatt = agp_alloc_gatt(sc); 179 if (gatt) 180 break; 181 182 /* 183 * Probably contigmalloc failure. Try reducing the 184 * aperture so that the gatt size reduces. 185 */ 186 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 187 agp_generic_detach(sc); 188 aprint_error(": failed to set aperture\n"); 189 return ENOMEM; 190 } 191 } 192 isc->gatt = gatt; 193 194 /* Install the gatt. */ 195 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 196 gatt->ag_physical); 197 198 /* Enable the GLTB and setup the control register. */ 199 switch (isc->chiptype) { 200 case CHIP_I443: 201 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 202 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 203 204 default: 205 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 206 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 207 | AGPCTRL_GTLB); 208 } 209 210 /* Enable things, clear errors etc. */ 211 switch (isc->chiptype) { 212 case CHIP_I845: 213 case CHIP_I865: 214 { 215 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 216 reg |= MCHCFG_AAGN; 217 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg); 218 break; 219 } 220 case CHIP_I840: 221 case CHIP_I850: 222 { 223 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 224 reg |= AGPCMD_AGPEN; 225 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 226 reg); 227 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 228 reg |= MCHCFG_AAGN; 229 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 230 reg); 231 break; 232 } 233 default: 234 { 235 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 236 reg &= ~NBXCFG_APAE; 237 reg |= NBXCFG_AAGN; 238 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 239 } 240 } 241 242 /* Clear Error status */ 243 switch (isc->chiptype) { 244 case CHIP_I840: 245 pci_conf_write(sc->as_pc, sc->as_tag, 246 AGP_INTEL_I8XX_ERRSTS, 0xc000); 247 break; 248 249 case CHIP_I845: 250 case CHIP_I850: 251 case CHIP_I865: 252 pci_conf_write(sc->as_pc, sc->as_tag, 253 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 254 break; 255 256 default: 257 pci_conf_write(sc->as_pc, sc->as_tag, 258 AGP_INTEL_ERRSTS, 0x70); 259 } 260 261 isc->sc_powerhook = powerhook_establish(sc->as_dev.dv_xname, 262 agp_intel_powerhook, sc); 263 if (isc->sc_powerhook == NULL) 264 aprint_error("%s: couldn't establish powerhook\n", 265 sc->as_dev.dv_xname); 266 267 return (0); 268 } 269 270 #if 0 271 static int 272 agp_intel_detach(struct agp_softc *sc) 273 { 274 int error; 275 pcireg_t reg; 276 struct agp_intel_softc *isc = sc->as_chipc; 277 278 if (isc->sc_powerhook) 279 powerhook_disestablish(isc->sc_powerhook); 280 281 error = agp_generic_detach(sc); 282 if (error) 283 return error; 284 285 /* XXX i845/i855PM/i840/i850E */ 286 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 287 reg &= ~(1 << 9); 288 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 289 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 290 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 291 AGP_SET_APERTURE(sc, isc->initial_aperture); 292 agp_free_gatt(sc, isc->gatt); 293 294 return 0; 295 } 296 #endif 297 298 static u_int32_t 299 agp_intel_get_aperture(struct agp_softc *sc) 300 { 301 struct agp_intel_softc *isc = sc->as_chipc; 302 u_int32_t apsize; 303 304 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 305 AGP_INTEL_APSIZE) & isc->aperture_mask; 306 307 /* 308 * The size is determined by the number of low bits of 309 * register APBASE which are forced to zero. The low 22 bits 310 * are always forced to zero and each zero bit in the apsize 311 * field just read forces the corresponding bit in the 27:22 312 * to be zero. We calculate the aperture size accordingly. 313 */ 314 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 315 } 316 317 static int 318 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 319 { 320 struct agp_intel_softc *isc = sc->as_chipc; 321 u_int32_t apsize; 322 323 /* 324 * Reverse the magic from get_aperture. 325 */ 326 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 327 328 /* 329 * Double check for sanity. 330 */ 331 if ((((apsize ^ isc->aperture_mask) << 22) | 332 ((1 << 22) - 1)) + 1 != aperture) 333 return EINVAL; 334 335 pci_conf_write(sc->as_pc, sc->as_tag, 336 AGP_INTEL_APSIZE, apsize); 337 338 return 0; 339 } 340 341 static int 342 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 343 { 344 struct agp_intel_softc *isc = sc->as_chipc; 345 346 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 347 return EINVAL; 348 349 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 350 return 0; 351 } 352 353 static int 354 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 355 { 356 struct agp_intel_softc *isc = sc->as_chipc; 357 358 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 359 return EINVAL; 360 361 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 362 return 0; 363 } 364 365 static void 366 agp_intel_flush_tlb(struct agp_softc *sc) 367 { 368 struct agp_intel_softc *isc = sc->as_chipc; 369 pcireg_t reg; 370 371 switch (isc->chiptype) { 372 case CHIP_I865: 373 case CHIP_I850: 374 case CHIP_I845: 375 case CHIP_I840: 376 case CHIP_I443: 377 { 378 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 379 reg &= ~AGPCTRL_GTLB; 380 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 381 reg); 382 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 383 reg | AGPCTRL_GTLB); 384 break; 385 } 386 default: /* XXX */ 387 { 388 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 389 0x2200); 390 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 391 0x2280); 392 } 393 } 394 } 395 396 static void 397 agp_intel_powerhook(int why, void *opaque) 398 { 399 struct agp_softc *sc; 400 struct agp_intel_softc *isc; 401 402 sc = (struct agp_softc *)opaque; 403 isc = (struct agp_intel_softc *)sc->as_chipc; 404 405 switch (why) { 406 case PWR_SUSPEND: 407 case PWR_STANDBY: 408 pci_conf_capture(sc->as_pc, sc->as_tag, &isc->sc_pciconf); 409 break; 410 case PWR_RESUME: 411 pci_conf_restore(sc->as_pc, sc->as_tag, &isc->sc_pciconf); 412 agp_flush_cache(); 413 break; 414 case PWR_SOFTSUSPEND: 415 case PWR_SOFTSTANDBY: 416 case PWR_SOFTRESUME: 417 break; 418 } 419 420 return; 421 } 422