1 /* $NetBSD: agp_intel.c,v 1.11 2003/07/06 12:39:41 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.11 2003/07/06 12:39:41 tron Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 #include <sys/agpio.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/agpvar.h> 50 #include <dev/pci/agpreg.h> 51 52 #include <machine/bus.h> 53 54 struct agp_intel_softc { 55 u_int32_t initial_aperture; 56 /* aperture size at startup */ 57 struct agp_gatt *gatt; 58 struct pci_attach_args vga_pa; 59 u_int aperture_mask; 60 int chiptype; /* Chip type */ 61 #define CHIP_INTEL 0x0 62 #define CHIP_I443 0x1 63 #define CHIP_I840 0x2 64 #define CHIP_I845 0x3 65 #define CHIP_I850 0x4 66 }; 67 68 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 69 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 70 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 71 static int agp_intel_unbind_page(struct agp_softc *, off_t); 72 static void agp_intel_flush_tlb(struct agp_softc *); 73 74 struct agp_methods agp_intel_methods = { 75 agp_intel_get_aperture, 76 agp_intel_set_aperture, 77 agp_intel_bind_page, 78 agp_intel_unbind_page, 79 agp_intel_flush_tlb, 80 agp_generic_enable, 81 agp_generic_alloc_memory, 82 agp_generic_free_memory, 83 agp_generic_bind_memory, 84 agp_generic_unbind_memory, 85 }; 86 87 static int 88 agp_intel_vgamatch(struct pci_attach_args *pa) 89 { 90 switch (PCI_PRODUCT(pa->pa_id)) { 91 case PCI_PRODUCT_INTEL_82855PM_AGP: 92 case PCI_PRODUCT_INTEL_82443LX_AGP: 93 case PCI_PRODUCT_INTEL_82443BX_AGP: 94 case PCI_PRODUCT_INTEL_82443GX_AGP: 95 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 96 case PCI_PRODUCT_INTEL_82845_AGP: 97 case PCI_PRODUCT_INTEL_82840_AGP: 98 case PCI_PRODUCT_INTEL_82865_AGP: 99 case PCI_PRODUCT_INTEL_82875P_AGP: 100 return (1); 101 } 102 103 return (0); 104 } 105 106 int 107 agp_intel_attach(struct device *parent, struct device *self, void *aux) 108 { 109 struct agp_softc *sc = (struct agp_softc *)self; 110 struct pci_attach_args *pa= aux; 111 struct agp_intel_softc *isc; 112 struct agp_gatt *gatt; 113 pcireg_t reg; 114 u_int32_t value; 115 116 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 117 if (isc == NULL) { 118 aprint_error(": can't allocate chipset-specific softc\n"); 119 return ENOMEM; 120 } 121 122 sc->as_methods = &agp_intel_methods; 123 sc->as_chipc = isc; 124 125 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 126 aprint_normal(": using generic initialization for Intel AGP\n"); 127 isc->chiptype = CHIP_INTEL; 128 } 129 130 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 131 NULL); 132 133 if (agp_map_aperture(pa, sc) != 0) { 134 aprint_error(": can't map aperture\n"); 135 free(isc, M_AGP); 136 sc->as_chipc = NULL; 137 return ENXIO; 138 } 139 140 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 141 case PCI_PRODUCT_INTEL_82855PM_AGP: 142 case PCI_PRODUCT_INTEL_82845_AGP: 143 case PCI_PRODUCT_INTEL_82865_AGP: 144 case PCI_PRODUCT_INTEL_82875P_AGP: 145 isc->chiptype = CHIP_I845; 146 break; 147 case PCI_PRODUCT_INTEL_82840_AGP: 148 isc->chiptype = CHIP_I840; 149 break; 150 case PCI_PRODUCT_INTEL_82850_AGP: 151 isc->chiptype = CHIP_I850; 152 break; 153 case PCI_PRODUCT_INTEL_82443LX_AGP: 154 case PCI_PRODUCT_INTEL_82443BX_AGP: 155 case PCI_PRODUCT_INTEL_82443GX_AGP: 156 isc->chiptype = CHIP_I443; 157 break; 158 } 159 160 /* Determine maximum supported aperture size. */ 161 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 162 pci_conf_write(sc->as_pc, sc->as_tag, 163 AGP_INTEL_APSIZE, APSIZE_MASK); 164 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 165 AGP_INTEL_APSIZE) & APSIZE_MASK; 166 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 167 isc->initial_aperture = AGP_GET_APERTURE(sc); 168 169 for (;;) { 170 gatt = agp_alloc_gatt(sc); 171 if (gatt) 172 break; 173 174 /* 175 * Probably contigmalloc failure. Try reducing the 176 * aperture so that the gatt size reduces. 177 */ 178 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 179 agp_generic_detach(sc); 180 aprint_error(": failed to set aperture\n"); 181 return ENOMEM; 182 } 183 } 184 isc->gatt = gatt; 185 186 /* Install the gatt. */ 187 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 188 gatt->ag_physical); 189 190 /* Enable the GLTB and setup the control register. */ 191 switch (isc->chiptype) { 192 case CHIP_I443: 193 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 194 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 195 196 default: 197 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 198 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 199 | AGPCTRL_GTLB); 200 } 201 202 /* Enable things, clear errors etc. */ 203 switch (isc->chiptype) { 204 case CHIP_I845: 205 { 206 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 207 AGPCMD_SBA | AGPCMD_AGPEN | AGPCMD_RATE_4X); 208 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I845_AGPMISC, AGPMISC_AAGN); 209 break; 210 } 211 case CHIP_I840: 212 case CHIP_I850: 213 { 214 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 215 reg |= AGPCMD_AGPEN; 216 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 217 reg); 218 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 219 reg |= MCHCFG_AAGN; 220 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 221 reg); 222 break; 223 } 224 default: 225 { 226 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 227 reg &= ~NBXCFG_APAE; 228 reg |= NBXCFG_AAGN; 229 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 230 } 231 } 232 233 /* Clear Error status */ 234 switch (isc->chiptype) { 235 case CHIP_I840: 236 pci_conf_write(sc->as_pc, sc->as_tag, 237 AGP_INTEL_I8XX_ERRSTS, 0xc000); 238 break; 239 240 case CHIP_I850: 241 case CHIP_I845: 242 pci_conf_write(sc->as_pc, sc->as_tag, 243 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 244 break; 245 246 default: 247 pci_conf_write(sc->as_pc, sc->as_tag, 248 AGP_INTEL_ERRSTS, 0x70); 249 } 250 251 return (0); 252 } 253 254 #if 0 255 static int 256 agp_intel_detach(struct agp_softc *sc) 257 { 258 int error; 259 pcireg_t reg; 260 struct agp_intel_softc *isc = sc->as_chipc; 261 262 error = agp_generic_detach(sc); 263 if (error) 264 return error; 265 266 /* XXX i845/i855PM/i840/i850E */ 267 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 268 reg &= ~(1 << 9); 269 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 270 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 271 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 272 AGP_SET_APERTURE(sc, isc->initial_aperture); 273 agp_free_gatt(sc, isc->gatt); 274 275 return 0; 276 } 277 #endif 278 279 static u_int32_t 280 agp_intel_get_aperture(struct agp_softc *sc) 281 { 282 struct agp_intel_softc *isc = sc->as_chipc; 283 u_int32_t apsize; 284 285 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 286 AGP_INTEL_APSIZE) & isc->aperture_mask; 287 288 /* 289 * The size is determined by the number of low bits of 290 * register APBASE which are forced to zero. The low 22 bits 291 * are always forced to zero and each zero bit in the apsize 292 * field just read forces the corresponding bit in the 27:22 293 * to be zero. We calculate the aperture size accordingly. 294 */ 295 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 296 } 297 298 static int 299 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 300 { 301 struct agp_intel_softc *isc = sc->as_chipc; 302 u_int32_t apsize; 303 304 /* 305 * Reverse the magic from get_aperture. 306 */ 307 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 308 309 /* 310 * Double check for sanity. 311 */ 312 if ((((apsize ^ isc->aperture_mask) << 22) | 313 ((1 << 22) - 1)) + 1 != aperture) 314 return EINVAL; 315 316 pci_conf_write(sc->as_pc, sc->as_tag, 317 AGP_INTEL_APSIZE, apsize); 318 319 return 0; 320 } 321 322 static int 323 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 324 { 325 struct agp_intel_softc *isc = sc->as_chipc; 326 327 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 328 return EINVAL; 329 330 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 331 return 0; 332 } 333 334 static int 335 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 336 { 337 struct agp_intel_softc *isc = sc->as_chipc; 338 339 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 340 return EINVAL; 341 342 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 343 return 0; 344 } 345 346 static void 347 agp_intel_flush_tlb(struct agp_softc *sc) 348 { 349 struct agp_intel_softc *isc = sc->as_chipc; 350 pcireg_t reg; 351 352 switch (isc->chiptype) { 353 case CHIP_I850: 354 case CHIP_I845: 355 case CHIP_I840: 356 case CHIP_I443: 357 { 358 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 359 reg &= ~AGPCTRL_GTLB; 360 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 361 reg); 362 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 363 reg | AGPCTRL_GTLB); 364 break; 365 } 366 default: /* XXX */ 367 { 368 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 369 0x2200); 370 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 371 0x2280); 372 } 373 } 374 } 375