1 /* $NetBSD: agp_i810.c,v 1.125 2022/07/17 10:10:45 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.125 2022/07/17 10:10:45 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/atomic.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/xcall.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 #include <dev/pci/agp_i810var.h> 51 52 #include <sys/agpio.h> 53 54 #include <sys/bus.h> 55 56 #include "agp_intel.h" 57 58 #ifdef AGP_DEBUG 59 #define DPRINTF(sc, fmt, ...) \ 60 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 61 #else 62 #define DPRINTF(sc, fmt, ...) do {} while (0) 63 #endif 64 65 struct agp_softc *agp_i810_sc = NULL; 66 67 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 68 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 69 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 70 71 #define CHIP_I810 0 /* i810/i815 */ 72 #define CHIP_I830 1 /* 830M/845G */ 73 #define CHIP_I855 2 /* 852GM/855GM/865G */ 74 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 75 #define CHIP_I965 4 /* 965Q/965PM */ 76 #define CHIP_G33 5 /* G33/Q33/Q35 */ 77 #define CHIP_G4X 6 /* G45/Q45 */ 78 #define CHIP_PINEVIEW 7 /* Pineview */ 79 80 /* XXX hack, see below */ 81 static bus_addr_t agp_i810_vga_regbase; 82 static bus_size_t agp_i810_vga_regsize; 83 static bus_space_tag_t agp_i810_vga_bst; 84 static bus_space_handle_t agp_i810_vga_bsh; 85 86 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 87 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 88 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 89 static int agp_i810_unbind_page(struct agp_softc *, off_t); 90 static void agp_i810_flush_tlb(struct agp_softc *); 91 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 92 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 93 vsize_t); 94 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 95 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 96 off_t); 97 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 98 off_t); 99 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 100 struct agp_memory *, off_t); 101 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 102 103 static bool agp_i810_resume(device_t, const pmf_qual_t *); 104 static int agp_i810_init(struct agp_softc *); 105 106 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 107 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 108 static int agp_i810_init(struct agp_softc *); 109 110 static struct agp_methods agp_i810_methods = { 111 agp_i810_get_aperture, 112 agp_i810_set_aperture, 113 agp_i810_bind_page, 114 agp_i810_unbind_page, 115 agp_i810_flush_tlb, 116 agp_i810_enable, 117 agp_i810_alloc_memory, 118 agp_i810_free_memory, 119 agp_i810_bind_memory, 120 agp_i810_unbind_memory, 121 }; 122 123 int 124 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, 125 bus_addr_t addr, int flags) 126 { 127 u_int32_t pte; 128 129 /* 130 * Bits 11:4 (physical start address extension) should be zero. 131 * Flag bits 3:0 should be zero too. 132 * 133 * XXX This should be a kassert -- no reason for this routine 134 * to allow failure. 135 */ 136 if ((addr & 0xfff) != 0) 137 return EINVAL; 138 KASSERT(flags == (flags & 0x7)); 139 140 pte = (u_int32_t)addr; 141 /* 142 * We need to massage the pte if bus_addr_t is wider than 32 bits. 143 * The compiler isn't smart enough, hence the casts to uintmax_t. 144 */ 145 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 146 /* 965+ can do 36-bit addressing, add in the extra bits. */ 147 if (isc->chiptype == CHIP_I965 || 148 isc->chiptype == CHIP_G33 || 149 isc->chiptype == CHIP_PINEVIEW || 150 isc->chiptype == CHIP_G4X) { 151 if (((uintmax_t)addr >> 36) != 0) 152 return EINVAL; 153 pte |= (addr >> 28) & 0xf0; 154 } else { 155 if (((uintmax_t)addr >> 32) != 0) 156 return EINVAL; 157 } 158 } 159 160 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 161 4*(off >> AGP_PAGE_SHIFT), pte | flags); 162 163 return 0; 164 } 165 166 void 167 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 168 { 169 170 /* 171 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>. 172 * Out of paranoia, let's do the write barrier and posting 173 * read, because I don't have enough time or hardware to 174 * conduct conclusive tests. 175 */ 176 bus_space_barrier(isc->gtt_bst, isc->gtt_bsh, 0, isc->gtt_size, 177 BUS_SPACE_BARRIER_WRITE); 178 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 179 4*(off >> AGP_PAGE_SHIFT)); 180 } 181 182 static void 183 agp_flush_cache_xc(void *a __unused, void *b __unused) 184 { 185 186 agp_flush_cache(); 187 } 188 189 void 190 agp_i810_chipset_flush(struct agp_i810_softc *isc) 191 { 192 unsigned int timo = 20000; /* * 50 us = 1 s */ 193 194 switch (isc->chiptype) { 195 case CHIP_I810: 196 break; 197 case CHIP_I830: 198 case CHIP_I855: 199 /* 200 * Flush all CPU caches. If we're cold, we can't run 201 * xcalls, but there should be only one CPU up, so 202 * flushing only the local CPU's cache should suffice. 203 * 204 * XXX Come to think of it, do these chipsets appear in 205 * any multi-CPU systems? 206 */ 207 if (cold) 208 agp_flush_cache(); 209 else 210 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 211 NULL, NULL)); 212 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 213 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 214 if (timo-- == 0) 215 break; 216 DELAY(50); 217 } 218 break; 219 case CHIP_I915: 220 case CHIP_I965: 221 case CHIP_G33: 222 case CHIP_PINEVIEW: 223 case CHIP_G4X: 224 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 225 break; 226 } 227 } 228 229 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 230 static int 231 agp_i810_vgamatch(const struct pci_attach_args *pa) 232 { 233 234 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 235 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 236 return (0); 237 238 switch (PCI_PRODUCT(pa->pa_id)) { 239 case PCI_PRODUCT_INTEL_82810_GC: 240 case PCI_PRODUCT_INTEL_82810_DC100_GC: 241 case PCI_PRODUCT_INTEL_82810E_GC: 242 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 243 case PCI_PRODUCT_INTEL_82830MP_IV: 244 case PCI_PRODUCT_INTEL_82845G_IGD: 245 case PCI_PRODUCT_INTEL_82855GM_IGD: 246 case PCI_PRODUCT_INTEL_82865_IGD: 247 case PCI_PRODUCT_INTEL_82915G_IGD: 248 case PCI_PRODUCT_INTEL_82915GM_IGD: 249 case PCI_PRODUCT_INTEL_82945P_IGD: 250 case PCI_PRODUCT_INTEL_82945GM_IGD: 251 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 252 case PCI_PRODUCT_INTEL_82945GME_IGD: 253 case PCI_PRODUCT_INTEL_E7221_IGD: 254 case PCI_PRODUCT_INTEL_82965Q_IGD: 255 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 256 case PCI_PRODUCT_INTEL_82965PM_IGD: 257 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 258 case PCI_PRODUCT_INTEL_82G33_IGD: 259 case PCI_PRODUCT_INTEL_82G33_IGD_1: 260 case PCI_PRODUCT_INTEL_82965G_IGD: 261 case PCI_PRODUCT_INTEL_82965G_IGD_1: 262 case PCI_PRODUCT_INTEL_82965GME_IGD: 263 case PCI_PRODUCT_INTEL_82Q35_IGD: 264 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 265 case PCI_PRODUCT_INTEL_82Q33_IGD: 266 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 267 case PCI_PRODUCT_INTEL_82G35_IGD: 268 case PCI_PRODUCT_INTEL_82G35_IGD_1: 269 case PCI_PRODUCT_INTEL_82946GZ_IGD: 270 case PCI_PRODUCT_INTEL_82GM45_IGD: 271 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 272 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 273 case PCI_PRODUCT_INTEL_82Q45_IGD: 274 case PCI_PRODUCT_INTEL_82G45_IGD: 275 case PCI_PRODUCT_INTEL_82G41_IGD: 276 case PCI_PRODUCT_INTEL_82B43_IGD: 277 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 278 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 279 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 280 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 281 return (1); 282 } 283 284 return (0); 285 } 286 287 static int 288 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 289 { 290 /* 291 * Find the aperture. Don't map it (yet), this would 292 * eat KVA. 293 */ 294 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 295 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 296 &sc->as_apflags) != 0) 297 return ENXIO; 298 299 sc->as_apt = pa->pa_memt; 300 301 return 0; 302 } 303 304 int 305 agp_i810_attach(device_t parent, device_t self, void *aux) 306 { 307 struct agp_softc *sc = device_private(self); 308 struct agp_i810_softc *isc; 309 int apbase, mmadr_bar, gtt_bar; 310 int mmadr_type, mmadr_flags; 311 bus_addr_t mmadr; 312 bus_size_t mmadr_size, gtt_off; 313 int error; 314 315 isc = malloc(sizeof *isc, M_AGP, M_WAITOK|M_ZERO); 316 sc->as_chipc = isc; 317 sc->as_methods = &agp_i810_methods; 318 319 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 320 #if NAGP_INTEL > 0 321 const struct pci_attach_args *pa = aux; 322 323 switch (PCI_PRODUCT(pa->pa_id)) { 324 case PCI_PRODUCT_INTEL_82840_HB: 325 case PCI_PRODUCT_INTEL_82865_HB: 326 case PCI_PRODUCT_INTEL_82845G_DRAM: 327 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 328 case PCI_PRODUCT_INTEL_82855GM_MCH: 329 free(isc, M_AGP); 330 return agp_intel_attach(parent, self, aux); 331 } 332 #endif 333 aprint_error(": can't find internal VGA" 334 " config space\n"); 335 error = ENOENT; 336 goto fail1; 337 } 338 339 /* XXXfvdl */ 340 sc->as_dmat = isc->vga_pa.pa_dmat; 341 342 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 343 case PCI_PRODUCT_INTEL_82810_GC: 344 case PCI_PRODUCT_INTEL_82810_DC100_GC: 345 case PCI_PRODUCT_INTEL_82810E_GC: 346 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 347 isc->chiptype = CHIP_I810; 348 aprint_normal(": i810-family chipset\n"); 349 break; 350 case PCI_PRODUCT_INTEL_82830MP_IV: 351 case PCI_PRODUCT_INTEL_82845G_IGD: 352 isc->chiptype = CHIP_I830; 353 aprint_normal(": i830-family chipset\n"); 354 break; 355 case PCI_PRODUCT_INTEL_82855GM_IGD: 356 case PCI_PRODUCT_INTEL_82865_IGD: 357 isc->chiptype = CHIP_I855; 358 aprint_normal(": i855-family chipset\n"); 359 break; 360 case PCI_PRODUCT_INTEL_82915G_IGD: 361 case PCI_PRODUCT_INTEL_82915GM_IGD: 362 case PCI_PRODUCT_INTEL_82945P_IGD: 363 case PCI_PRODUCT_INTEL_82945GM_IGD: 364 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 365 case PCI_PRODUCT_INTEL_82945GME_IGD: 366 case PCI_PRODUCT_INTEL_E7221_IGD: 367 isc->chiptype = CHIP_I915; 368 aprint_normal(": i915-family chipset\n"); 369 break; 370 case PCI_PRODUCT_INTEL_82965Q_IGD: 371 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 372 case PCI_PRODUCT_INTEL_82965PM_IGD: 373 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 374 case PCI_PRODUCT_INTEL_82965G_IGD: 375 case PCI_PRODUCT_INTEL_82965G_IGD_1: 376 case PCI_PRODUCT_INTEL_82965GME_IGD: 377 case PCI_PRODUCT_INTEL_82946GZ_IGD: 378 case PCI_PRODUCT_INTEL_82G35_IGD: 379 case PCI_PRODUCT_INTEL_82G35_IGD_1: 380 isc->chiptype = CHIP_I965; 381 aprint_normal(": i965-family chipset\n"); 382 break; 383 case PCI_PRODUCT_INTEL_82Q35_IGD: 384 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 385 case PCI_PRODUCT_INTEL_82G33_IGD: 386 case PCI_PRODUCT_INTEL_82G33_IGD_1: 387 case PCI_PRODUCT_INTEL_82Q33_IGD: 388 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 389 isc->chiptype = CHIP_G33; 390 aprint_normal(": G33-family chipset\n"); 391 break; 392 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 393 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 394 isc->chiptype = CHIP_PINEVIEW; 395 aprint_normal(": Pineview chipset\n"); 396 break; 397 case PCI_PRODUCT_INTEL_82GM45_IGD: 398 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 399 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 400 case PCI_PRODUCT_INTEL_82Q45_IGD: 401 case PCI_PRODUCT_INTEL_82G45_IGD: 402 case PCI_PRODUCT_INTEL_82G41_IGD: 403 case PCI_PRODUCT_INTEL_82B43_IGD: 404 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 405 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 406 isc->chiptype = CHIP_G4X; 407 aprint_normal(": G4X-family chipset\n"); 408 break; 409 } 410 aprint_naive("\n"); 411 412 /* Discriminate on the chipset to choose the relevant BARs. */ 413 switch (isc->chiptype) { 414 case CHIP_I915: 415 case CHIP_G33: 416 case CHIP_PINEVIEW: 417 apbase = AGP_I915_GMADR; 418 mmadr_bar = AGP_I915_MMADR; 419 gtt_bar = AGP_I915_GTTADR; 420 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 421 break; 422 case CHIP_I965: 423 apbase = AGP_I965_GMADR; 424 mmadr_bar = AGP_I965_MMADR; 425 gtt_bar = 0; 426 gtt_off = AGP_I965_GTT; 427 break; 428 case CHIP_G4X: 429 apbase = AGP_I965_GMADR; 430 mmadr_bar = AGP_I965_MMADR; 431 gtt_bar = 0; 432 gtt_off = AGP_G4X_GTT; 433 break; 434 default: 435 apbase = AGP_I810_GMADR; 436 mmadr_bar = AGP_I810_MMADR; 437 gtt_bar = 0; 438 gtt_off = AGP_I810_GTT; 439 break; 440 } 441 442 /* 443 * Ensure the MMIO BAR is, in fact, a memory BAR. 444 * 445 * XXX This is required because we use pa_memt below. It is 446 * not a priori clear to me there is any other reason to 447 * require this. 448 */ 449 mmadr_type = pci_mapreg_type(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 450 mmadr_bar); 451 if (PCI_MAPREG_TYPE(mmadr_type) != PCI_MAPREG_TYPE_MEM) { 452 aprint_error_dev(self, "non-memory device MMIO registers\n"); 453 error = ENXIO; 454 goto fail1; 455 } 456 457 /* 458 * Determine the size of the MMIO registers. 459 * 460 * XXX The size of the MMIO registers we use is statically 461 * determined, as a function of the chipset, by the driver's 462 * implementation. 463 * 464 * On some chipsets, the GTT is part of the MMIO register BAR. 465 * We would like to map the GTT separately, so that we can map 466 * it prefetchable, which we can't do with the MMIO registers. 467 * Consequently, we would especially like to map a fixed size 468 * of MMIO registers, not just whatever size the BAR says. 469 * 470 * However, old drm assumes that the combined GTT/MMIO register 471 * space is a single bus space mapping, so mapping them 472 * separately breaks that. Once we rip out old drm, we can 473 * replace the pci_mapreg_info call by the chipset switch. 474 */ 475 #if notyet 476 switch (isc->chiptype) { 477 case CHIP_I810: 478 case CHIP_I830: 479 case CHIP_I855: 480 case CHIP_I915: 481 case CHIP_I965: 482 case CHIP_G33: 483 case CHIP_PINEVIEW: 484 case CHIP_G4X: 485 isc->size = 512*1024; 486 break; 487 case CHIP_SANDYBRIDGE: 488 case CHIP_IVYBRIDGE: 489 case CHIP_HASWELL: 490 isc->size = 2*1024*1024; 491 break; 492 } 493 #else 494 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 495 mmadr_bar, mmadr_type, NULL, &isc->size, NULL)) 496 isc->size = 512*1024; 497 #endif /* notyet */ 498 499 /* Map (or, rather, find the address and size of) the aperture. */ 500 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 501 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 502 else 503 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 504 if (error) { 505 aprint_error_dev(self, "can't map aperture: %d\n", error); 506 goto fail1; 507 } 508 509 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 510 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 511 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 512 aprint_error_dev(self, "can't find MMIO registers\n"); 513 error = ENXIO; 514 goto fail1; 515 } 516 if (mmadr_size < isc->size) { 517 aprint_error_dev(self, "MMIO registers too small" 518 ": %"PRIuMAX" < %"PRIuMAX"\n", 519 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 520 error = ENXIO; 521 goto fail1; 522 } 523 isc->bst = isc->vga_pa.pa_memt; 524 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 525 &isc->bsh); 526 if (error) { 527 aprint_error_dev(self, "can't map MMIO registers: %d\n", 528 error); 529 error = ENXIO; 530 goto fail1; 531 } 532 533 /* Set up a chipset flush page if necessary. */ 534 switch (isc->chiptype) { 535 case CHIP_I915: 536 case CHIP_I965: 537 case CHIP_G33: 538 case CHIP_PINEVIEW: 539 case CHIP_G4X: 540 error = agp_i810_setup_chipset_flush_page(sc); 541 if (error) { 542 aprint_error_dev(self, 543 "can't set up chipset flush page: %d\n", error); 544 goto fail2; 545 } 546 break; 547 } 548 549 /* 550 * XXX horrible hack to allow drm code to use our mapping 551 * of VGA chip registers 552 */ 553 agp_i810_vga_regbase = mmadr; 554 agp_i810_vga_regsize = isc->size; 555 agp_i810_vga_bst = isc->bst; 556 agp_i810_vga_bsh = isc->bsh; 557 558 /* Initialize the chipset. */ 559 error = agp_i810_init(sc); 560 if (error) 561 goto fail3; 562 563 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 564 if (gtt_bar == 0) { 565 isc->gtt_bst = isc->bst; 566 if ((mmadr_size - gtt_off) < isc->gtt_size) { 567 aprint_error_dev(self, "GTTMMADR too small for GTT" 568 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 569 (uintmax_t)mmadr_size, 570 (uintmax_t)gtt_off, 571 (uintmax_t)isc->gtt_size); 572 error = ENXIO; 573 goto fail4; 574 } 575 /* 576 * Map the GTT separately if we can, so that we can map 577 * it prefetchable, but in early models, there are MMIO 578 * registers before and after the GTT, so we can only 579 * take a subregion. 580 */ 581 if (isc->size < gtt_off) 582 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 583 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 584 else 585 error = bus_space_subregion(isc->bst, isc->bsh, 586 gtt_off, isc->gtt_size, &isc->gtt_bsh); 587 if (error) { 588 aprint_error_dev(self, "can't map GTT: %d\n", error); 589 error = ENXIO; 590 goto fail4; 591 } 592 } else { 593 bus_size_t gtt_bar_size; 594 /* 595 * All chipsets with a separate BAR for the GTT, namely 596 * the i915 and G33 families, have 32-bit GTT BARs. 597 * 598 * XXX [citation needed] 599 */ 600 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 601 0, 602 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 603 aprint_error_dev(self, "can't map GTT\n"); 604 error = ENXIO; 605 goto fail4; 606 } 607 if (gtt_bar_size != isc->gtt_size) { 608 aprint_error_dev(self, 609 "BAR size %"PRIxMAX 610 " mismatches detected GTT size %"PRIxMAX 611 "; trusting BAR\n", 612 (uintmax_t)gtt_bar_size, 613 (uintmax_t)isc->gtt_size); 614 isc->gtt_size = gtt_bar_size; 615 } 616 } 617 618 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 619 if (!pmf_device_register(self, NULL, agp_i810_resume)) 620 aprint_error_dev(self, "can't establish power handler\n"); 621 622 /* Match the generic AGP code's autoconf output format. */ 623 aprint_normal("%s", device_xname(self)); 624 625 /* Success! */ 626 return 0; 627 628 fail5: __unused 629 pmf_device_deregister(self); 630 if ((gtt_bar != 0) || (isc->size < gtt_off)) 631 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 632 isc->gtt_size = 0; 633 fail4: 634 #if notyet 635 agp_i810_fini(sc); 636 #endif 637 fail3: switch (isc->chiptype) { 638 case CHIP_I915: 639 case CHIP_I965: 640 case CHIP_G33: 641 case CHIP_PINEVIEW: 642 case CHIP_G4X: 643 agp_i810_teardown_chipset_flush_page(sc); 644 break; 645 } 646 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 647 isc->size = 0; 648 fail1: free(isc, M_AGP); 649 sc->as_chipc = NULL; 650 agp_generic_detach(sc); 651 KASSERT(error); 652 return error; 653 } 654 655 /* 656 * Skip pages reserved by the BIOS. Notably, skip 0xa0000-0xfffff, 657 * which includes the video BIOS at 0xc0000-0xdffff which the display 658 * drivers need for video mode detection. 659 * 660 * XXX Is there an MI name for this, or a conventional x86 name? Or 661 * should we really use bus_dma instead? 662 */ 663 #define PCIBIOS_MIN_MEM 0x100000 664 665 static int 666 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 667 { 668 struct agp_i810_softc *const isc = sc->as_chipc; 669 const pci_chipset_tag_t pc = sc->as_pc; 670 const pcitag_t tag = sc->as_tag; 671 pcireg_t lo, hi; 672 bus_addr_t addr, minaddr, maxaddr; 673 int error; 674 675 /* We always use memory-mapped I/O. */ 676 isc->flush_bst = isc->vga_pa.pa_memt; 677 678 /* No page allocated yet. */ 679 isc->flush_addr = 0; 680 681 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 682 if (isc->chiptype == CHIP_I915) { 683 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 684 minaddr = PCIBIOS_MIN_MEM; 685 maxaddr = UINT32_MAX; 686 } else { 687 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 688 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 689 /* 690 * Convert to uint64_t, rather than bus_addr_t which 691 * may be 32-bit, to avoid undefined behaviour with a 692 * too-wide shift. Since the BIOS doesn't know whether 693 * the OS will run 64-bit or with PAE, it ought to 694 * configure at most a 32-bit physical address, so 695 * let's print a warning in case that happens. 696 */ 697 addr = ((uint64_t)hi << 32) | lo; 698 if (hi) { 699 aprint_error_dev(sc->as_dev, 700 "BIOS configured >32-bit flush page address" 701 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 702 #if __i386__ && !PAE 703 return EIO; 704 #endif 705 } 706 minaddr = PCIBIOS_MIN_MEM; 707 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 708 } 709 710 /* Allocate or map a pre-allocated a page for it. */ 711 if (ISSET(addr, 1)) { 712 /* BIOS allocated it for us. Use that. */ 713 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 714 &isc->flush_bsh); 715 if (error) 716 return error; 717 } else { 718 /* None allocated. Allocate one. */ 719 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 720 PAGE_SIZE, PAGE_SIZE, 0, 0, 721 &isc->flush_addr, &isc->flush_bsh); 722 if (error) 723 return error; 724 KASSERT(isc->flush_addr != 0); 725 /* Write it into the PCI config register. */ 726 addr = isc->flush_addr | 1; 727 if (isc->chiptype == CHIP_I915) { 728 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 729 } else { 730 hi = __SHIFTOUT(addr, __BITS(63, 32)); 731 lo = __SHIFTOUT(addr, __BITS(31, 0)); 732 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 733 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 734 } 735 } 736 737 /* Success! */ 738 return 0; 739 } 740 741 static void 742 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 743 { 744 struct agp_i810_softc *const isc = sc->as_chipc; 745 746 if (isc->flush_addr) { 747 /* If we allocated a page, clear it. */ 748 if (isc->chiptype == CHIP_I915) { 749 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 750 0); 751 } else { 752 pci_conf_write(sc->as_pc, sc->as_tag, 753 AGP_I965_IFPADDR, 0); 754 pci_conf_write(sc->as_pc, sc->as_tag, 755 AGP_I965_IFPADDR + 4, 0); 756 } 757 isc->flush_addr = 0; 758 bus_space_free(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 759 } else { 760 /* Otherwise, just unmap the pre-allocated page. */ 761 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 762 } 763 } 764 765 /* 766 * XXX horrible hack to allow drm code to use our mapping 767 * of VGA chip registers 768 */ 769 int 770 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 771 { 772 773 if (agp_i810_vga_regbase == 0) 774 return 0; 775 if (base < agp_i810_vga_regbase) 776 return 0; 777 if (agp_i810_vga_regsize < size) 778 return 0; 779 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 780 return 0; 781 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 782 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 783 hdlp)) 784 return 0; 785 return 1; 786 } 787 788 static int 789 agp_i810_init(struct agp_softc *sc) 790 { 791 struct agp_i810_softc *isc; 792 int error; 793 794 isc = sc->as_chipc; 795 796 if (isc->chiptype == CHIP_I810) { 797 struct agp_gatt *gatt; 798 void *virtual; 799 int dummyseg; 800 801 /* Some i810s have on-chip memory called dcache */ 802 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 803 isc->dcache_size = 4 * 1024 * 1024; 804 else 805 isc->dcache_size = 0; 806 807 /* According to the specs the gatt on the i810 must be 64k */ 808 isc->gtt_size = 64 * 1024; 809 gatt = malloc(sizeof(*gatt), M_AGP, M_WAITOK); 810 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 811 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 812 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 813 &gatt->ag_dmaseg, 1, &dummyseg); 814 if (error) { 815 aprint_error_dev(sc->as_dev, 816 "can't allocate memory for GTT: %d\n", error); 817 free(gatt, M_AGP); 818 goto fail0; 819 } 820 821 gatt->ag_virtual = (uint32_t *)virtual; 822 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 823 memset(gatt->ag_virtual, 0, gatt->ag_size); 824 agp_flush_cache(); 825 826 /* Install the GATT. */ 827 isc->pgtblctl = gatt->ag_physical | 1; 828 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 829 isc->gatt = gatt; 830 } else if (isc->chiptype == CHIP_I830) { 831 /* The i830 automatically initializes the 128k gatt on boot. */ 832 /* XXX [citation needed] */ 833 pcireg_t reg; 834 u_int16_t gcc1; 835 836 isc->gtt_size = 128 * 1024; 837 838 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 839 gcc1 = (u_int16_t)(reg >> 16); 840 switch (gcc1 & AGP_I830_GCC1_GMS) { 841 case AGP_I830_GCC1_GMS_STOLEN_512: 842 isc->stolen = (512 - 132) * 1024 / 4096; 843 break; 844 case AGP_I830_GCC1_GMS_STOLEN_1024: 845 isc->stolen = (1024 - 132) * 1024 / 4096; 846 break; 847 case AGP_I830_GCC1_GMS_STOLEN_8192: 848 isc->stolen = (8192 - 132) * 1024 / 4096; 849 break; 850 default: 851 isc->stolen = 0; 852 aprint_error_dev(sc->as_dev, 853 "unknown memory configuration, disabling\n"); 854 error = ENXIO; 855 goto fail0; 856 } 857 858 if (isc->stolen > 0) { 859 aprint_normal_dev(sc->as_dev, 860 "detected %dk stolen memory\n", 861 isc->stolen * 4); 862 } 863 864 /* GATT address is already in there, make sure it's enabled */ 865 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 866 isc->pgtblctl |= 1; 867 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 868 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 869 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 870 isc->chiptype == CHIP_PINEVIEW || 871 isc->chiptype == CHIP_G4X) { 872 pcireg_t reg; 873 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 874 u_int16_t gcc1; 875 876 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 877 gcc1 = (u_int16_t)(reg >> 16); 878 879 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 880 881 /* Stolen memory is set up at the beginning of the aperture by 882 * the BIOS, consisting of the GATT followed by 4kb for the 883 * BIOS display. 884 */ 885 switch (isc->chiptype) { 886 case CHIP_I855: 887 gtt_size = 128; 888 break; 889 case CHIP_I915: 890 gtt_size = 256; 891 break; 892 case CHIP_I965: 893 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 894 case AGP_I810_PGTBL_SIZE_128KB: 895 case AGP_I810_PGTBL_SIZE_512KB: 896 gtt_size = 512; 897 break; 898 case AGP_I965_PGTBL_SIZE_1MB: 899 gtt_size = 1024; 900 break; 901 case AGP_I965_PGTBL_SIZE_2MB: 902 gtt_size = 2048; 903 break; 904 case AGP_I965_PGTBL_SIZE_1_5MB: 905 gtt_size = 1024 + 512; 906 break; 907 default: 908 aprint_error_dev(sc->as_dev, 909 "bad PGTBL size\n"); 910 error = ENXIO; 911 goto fail0; 912 } 913 break; 914 case CHIP_G33: 915 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 916 case AGP_G33_PGTBL_SIZE_1M: 917 gtt_size = 1024; 918 break; 919 case AGP_G33_PGTBL_SIZE_2M: 920 gtt_size = 2048; 921 break; 922 default: 923 aprint_error_dev(sc->as_dev, 924 "bad PGTBL size\n"); 925 error = ENXIO; 926 goto fail0; 927 } 928 break; 929 case CHIP_PINEVIEW: 930 switch (gcc1 & AGP_PINEVIEW_PGTBL_SIZE_MASK) { 931 case AGP_PINEVIEW_PGTBL_SIZE_1M: 932 gtt_size = 1024; 933 break; 934 default: 935 aprint_error_dev(sc->as_dev, 936 "bad PGTBL size\n"); 937 error = ENXIO; 938 goto fail0; 939 } 940 break; 941 case CHIP_G4X: 942 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 943 case AGP_G4X_PGTBL_SIZE_512K: 944 gtt_size = 512; 945 break; 946 case AGP_G4X_PGTBL_SIZE_256K: 947 gtt_size = 256; 948 break; 949 case AGP_G4X_PGTBL_SIZE_128K: 950 gtt_size = 128; 951 break; 952 case AGP_G4X_PGTBL_SIZE_1M: 953 gtt_size = 1*1024; 954 break; 955 case AGP_G4X_PGTBL_SIZE_2M: 956 gtt_size = 2*1024; 957 break; 958 case AGP_G4X_PGTBL_SIZE_1_5M: 959 gtt_size = 1*1024 + 512; 960 break; 961 default: 962 aprint_error_dev(sc->as_dev, 963 "bad PGTBL size\n"); 964 error = ENXIO; 965 goto fail0; 966 } 967 break; 968 default: 969 panic("impossible chiptype %d", isc->chiptype); 970 } 971 972 /* 973 * XXX If I'm reading the datasheets right, this stolen 974 * memory detection logic is totally wrong. 975 */ 976 switch (gcc1 & AGP_I855_GCC1_GMS) { 977 case AGP_I855_GCC1_GMS_STOLEN_1M: 978 stolen = 1024; 979 break; 980 case AGP_I855_GCC1_GMS_STOLEN_4M: 981 stolen = 4 * 1024; 982 break; 983 case AGP_I855_GCC1_GMS_STOLEN_8M: 984 stolen = 8 * 1024; 985 break; 986 case AGP_I855_GCC1_GMS_STOLEN_16M: 987 stolen = 16 * 1024; 988 break; 989 case AGP_I855_GCC1_GMS_STOLEN_32M: 990 stolen = 32 * 1024; 991 break; 992 case AGP_I915_GCC1_GMS_STOLEN_48M: 993 stolen = 48 * 1024; 994 break; 995 case AGP_I915_GCC1_GMS_STOLEN_64M: 996 stolen = 64 * 1024; 997 break; 998 case AGP_G33_GCC1_GMS_STOLEN_128M: 999 stolen = 128 * 1024; 1000 break; 1001 case AGP_G33_GCC1_GMS_STOLEN_256M: 1002 stolen = 256 * 1024; 1003 break; 1004 case AGP_G4X_GCC1_GMS_STOLEN_96M: 1005 stolen = 96 * 1024; 1006 break; 1007 case AGP_G4X_GCC1_GMS_STOLEN_160M: 1008 stolen = 160 * 1024; 1009 break; 1010 case AGP_G4X_GCC1_GMS_STOLEN_224M: 1011 stolen = 224 * 1024; 1012 break; 1013 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1014 stolen = 352 * 1024; 1015 break; 1016 default: 1017 aprint_error_dev(sc->as_dev, 1018 "unknown memory configuration, disabling\n"); 1019 error = ENXIO; 1020 goto fail0; 1021 } 1022 1023 switch (gcc1 & AGP_I855_GCC1_GMS) { 1024 case AGP_I915_GCC1_GMS_STOLEN_48M: 1025 case AGP_I915_GCC1_GMS_STOLEN_64M: 1026 if (isc->chiptype != CHIP_I915 && 1027 isc->chiptype != CHIP_I965 && 1028 isc->chiptype != CHIP_G33 && 1029 isc->chiptype != CHIP_PINEVIEW && 1030 isc->chiptype != CHIP_G4X) 1031 stolen = 0; 1032 break; 1033 case AGP_G33_GCC1_GMS_STOLEN_128M: 1034 case AGP_G33_GCC1_GMS_STOLEN_256M: 1035 if (isc->chiptype != CHIP_I965 && 1036 isc->chiptype != CHIP_G33 && 1037 isc->chiptype != CHIP_PINEVIEW && 1038 isc->chiptype != CHIP_G4X) 1039 stolen = 0; 1040 break; 1041 case AGP_G4X_GCC1_GMS_STOLEN_96M: 1042 case AGP_G4X_GCC1_GMS_STOLEN_160M: 1043 case AGP_G4X_GCC1_GMS_STOLEN_224M: 1044 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1045 if (isc->chiptype != CHIP_I965 && 1046 isc->chiptype != CHIP_G4X) 1047 stolen = 0; 1048 break; 1049 } 1050 1051 isc->gtt_size = gtt_size * 1024; 1052 1053 /* BIOS space */ 1054 /* XXX [citation needed] */ 1055 gtt_size += 4; 1056 1057 /* XXX [citation needed] for this subtraction */ 1058 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 1059 1060 if (isc->stolen > 0) { 1061 aprint_normal_dev(sc->as_dev, 1062 "detected %dk stolen memory\n", 1063 isc->stolen * 4); 1064 } 1065 1066 /* GATT address is already in there, make sure it's enabled */ 1067 isc->pgtblctl |= 1; 1068 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 1069 } 1070 1071 /* 1072 * Make sure the chipset can see everything. 1073 */ 1074 agp_flush_cache(); 1075 1076 /* 1077 * Publish what we found for kludgey drivers (I'm looking at 1078 * you, drm). 1079 */ 1080 if (agp_i810_sc == NULL) 1081 agp_i810_sc = sc; 1082 else 1083 aprint_error_dev(sc->as_dev, "agp already attached\n"); 1084 1085 /* Success! */ 1086 return 0; 1087 1088 fail0: KASSERT(error); 1089 return error; 1090 } 1091 1092 #if 0 1093 static int 1094 agp_i810_detach(struct agp_softc *sc) 1095 { 1096 int error; 1097 struct agp_i810_softc *isc = sc->as_chipc; 1098 1099 error = agp_generic_detach(sc); 1100 if (error) 1101 return error; 1102 1103 switch (isc->chiptype) { 1104 case CHIP_I915: 1105 case CHIP_I965: 1106 case CHIP_G33: 1107 case CHIP_PINEVIEW: 1108 case CHIP_G4X: 1109 agp_i810_teardown_chipset_flush_page(sc); 1110 break; 1111 } 1112 1113 /* Clear the GATT base. */ 1114 if (sc->chiptype == CHIP_I810) { 1115 WRITE4(AGP_I810_PGTBL_CTL, 0); 1116 } else { 1117 unsigned int pgtblctl; 1118 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1119 pgtblctl &= ~1; 1120 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1121 } 1122 1123 if (sc->chiptype == CHIP_I810) { 1124 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1125 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1126 free(isc->gatt, M_AGP); 1127 } 1128 1129 return 0; 1130 } 1131 #endif 1132 1133 static u_int32_t 1134 agp_i810_get_aperture(struct agp_softc *sc) 1135 { 1136 struct agp_i810_softc *isc = sc->as_chipc; 1137 pcireg_t reg; 1138 u_int32_t size; 1139 u_int16_t miscc, gcc1; 1140 1141 size = 0; 1142 1143 switch (isc->chiptype) { 1144 case CHIP_I810: 1145 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1146 miscc = (u_int16_t)(reg >> 16); 1147 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1148 AGP_I810_MISCC_WINSIZE_32) 1149 size = 32 * 1024 * 1024; 1150 else 1151 size = 64 * 1024 * 1024; 1152 break; 1153 case CHIP_I830: 1154 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1155 gcc1 = (u_int16_t)(reg >> 16); 1156 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1157 size = 64 * 1024 * 1024; 1158 else 1159 size = 128 * 1024 * 1024; 1160 break; 1161 case CHIP_I855: 1162 size = 128 * 1024 * 1024; 1163 break; 1164 case CHIP_I915: 1165 case CHIP_G33: 1166 case CHIP_PINEVIEW: 1167 case CHIP_G4X: 1168 size = sc->as_apsize; 1169 break; 1170 case CHIP_I965: 1171 size = 512 * 1024 * 1024; 1172 break; 1173 default: 1174 aprint_error(": Unknown chipset\n"); 1175 } 1176 1177 return size; 1178 } 1179 1180 static int 1181 agp_i810_set_aperture(struct agp_softc *sc __unused, 1182 uint32_t aperture __unused) 1183 { 1184 1185 return ENOSYS; 1186 } 1187 1188 static int 1189 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1190 { 1191 struct agp_i810_softc *isc = sc->as_chipc; 1192 1193 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1194 DPRINTF(sc, "failed" 1195 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1196 (uintmax_t)offset, 1197 (unsigned)AGP_PAGE_SHIFT, 1198 (uintmax_t)isc->gtt_size/4); 1199 return EINVAL; 1200 } 1201 1202 if (isc->chiptype != CHIP_I810) { 1203 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1204 DPRINTF(sc, "trying to bind into stolen memory\n"); 1205 return EINVAL; 1206 } 1207 } 1208 1209 return agp_i810_write_gtt_entry(isc, offset, physical, 1210 AGP_I810_GTT_VALID); 1211 } 1212 1213 static int 1214 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1215 { 1216 struct agp_i810_softc *isc = sc->as_chipc; 1217 1218 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1219 return EINVAL; 1220 1221 if (isc->chiptype != CHIP_I810 ) { 1222 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1223 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1224 return EINVAL; 1225 } 1226 } 1227 1228 return agp_i810_write_gtt_entry(isc, offset, 0, 0); 1229 } 1230 1231 /* 1232 * Writing via memory mapped registers already flushes all TLBs. 1233 */ 1234 static void 1235 agp_i810_flush_tlb(struct agp_softc *sc) 1236 { 1237 } 1238 1239 static int 1240 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1241 { 1242 1243 return 0; 1244 } 1245 1246 #define AGP_I810_MEMTYPE_MAIN 0 1247 #define AGP_I810_MEMTYPE_DCACHE 1 1248 #define AGP_I810_MEMTYPE_HWCURSOR 2 1249 1250 static struct agp_memory * 1251 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1252 { 1253 struct agp_i810_softc *isc = sc->as_chipc; 1254 struct agp_memory *mem; 1255 int error; 1256 1257 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1258 1259 if (size <= 0) 1260 return NULL; 1261 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1262 return NULL; 1263 KASSERT(sc->as_allocated <= sc->as_maxmem); 1264 if (size > (sc->as_maxmem - sc->as_allocated)) 1265 return NULL; 1266 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1267 return NULL; 1268 1269 switch (type) { 1270 case AGP_I810_MEMTYPE_MAIN: 1271 break; 1272 case AGP_I810_MEMTYPE_DCACHE: 1273 if (isc->chiptype != CHIP_I810) 1274 return NULL; 1275 if (size != isc->dcache_size) 1276 return NULL; 1277 break; 1278 case AGP_I810_MEMTYPE_HWCURSOR: 1279 if ((size != AGP_PAGE_SIZE) && 1280 (size != AGP_PAGE_SIZE*4)) 1281 return NULL; 1282 break; 1283 default: 1284 return NULL; 1285 } 1286 1287 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1288 if (mem == NULL) 1289 goto fail0; 1290 mem->am_id = sc->as_nextid++; 1291 mem->am_size = size; 1292 mem->am_type = type; 1293 1294 switch (type) { 1295 case AGP_I810_MEMTYPE_MAIN: 1296 error = bus_dmamap_create(sc->as_dmat, size, 1297 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1298 &mem->am_dmamap); 1299 if (error) 1300 goto fail1; 1301 break; 1302 case AGP_I810_MEMTYPE_DCACHE: 1303 break; 1304 case AGP_I810_MEMTYPE_HWCURSOR: 1305 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1306 M_WAITOK); 1307 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1308 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1309 &mem->am_nseg); 1310 if (error) { 1311 free(mem->am_dmaseg, M_AGP); 1312 goto fail1; 1313 } 1314 (void)memset(mem->am_virtual, 0, size); 1315 break; 1316 default: 1317 panic("invalid agp memory type: %d", type); 1318 } 1319 1320 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1321 sc->as_allocated += size; 1322 1323 return mem; 1324 1325 fail1: free(mem, M_AGP); 1326 fail0: return NULL; 1327 } 1328 1329 static int 1330 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1331 { 1332 1333 if (mem->am_is_bound) 1334 return EBUSY; 1335 1336 switch (mem->am_type) { 1337 case AGP_I810_MEMTYPE_MAIN: 1338 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1339 break; 1340 case AGP_I810_MEMTYPE_DCACHE: 1341 break; 1342 case AGP_I810_MEMTYPE_HWCURSOR: 1343 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1344 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1345 free(mem->am_dmaseg, M_AGP); 1346 break; 1347 default: 1348 panic("invalid agp i810 memory type: %d", mem->am_type); 1349 } 1350 1351 sc->as_allocated -= mem->am_size; 1352 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1353 free(mem, M_AGP); 1354 1355 return 0; 1356 } 1357 1358 static int 1359 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1360 off_t offset) 1361 { 1362 struct agp_i810_softc *isc = sc->as_chipc; 1363 uint32_t pgtblctl; 1364 int error; 1365 1366 if (mem->am_is_bound) 1367 return EINVAL; 1368 1369 /* 1370 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1371 * X server for mysterious reasons which leads to crashes if we write 1372 * to the GTT through the MMIO window. 1373 * Until the issue is solved, simply restore it. 1374 */ 1375 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1376 if (pgtblctl != isc->pgtblctl) { 1377 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1378 " - fixing\n", pgtblctl); 1379 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1380 isc->pgtblctl); 1381 } 1382 1383 switch (mem->am_type) { 1384 case AGP_I810_MEMTYPE_MAIN: 1385 return agp_generic_bind_memory_bounded(sc, mem, offset, 1386 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1387 case AGP_I810_MEMTYPE_DCACHE: 1388 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1389 break; 1390 case AGP_I810_MEMTYPE_HWCURSOR: 1391 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1392 break; 1393 default: 1394 panic("invalid agp i810 memory type: %d", mem->am_type); 1395 } 1396 if (error) 1397 return error; 1398 1399 /* Success! */ 1400 mem->am_is_bound = 1; 1401 return 0; 1402 } 1403 1404 static int 1405 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1406 off_t offset) 1407 { 1408 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1409 uint32_t i, j; 1410 int error; 1411 1412 KASSERT(isc->chiptype == CHIP_I810); 1413 1414 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1415 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1416 error = agp_i810_write_gtt_entry(isc, offset + i, 1417 i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE); 1418 if (error) 1419 goto fail0; 1420 } 1421 1422 /* Success! */ 1423 mem->am_offset = offset; 1424 return 0; 1425 1426 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1427 (void)agp_i810_unbind_page(sc, offset + j); 1428 return error; 1429 } 1430 1431 static int 1432 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1433 off_t offset) 1434 { 1435 const bus_addr_t pa = mem->am_physical; 1436 uint32_t i, j; 1437 int error; 1438 1439 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1440 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1441 error = agp_i810_bind_page(sc, offset + i, pa + i); 1442 if (error) 1443 goto fail0; 1444 } 1445 1446 /* Success! */ 1447 mem->am_offset = offset; 1448 return 0; 1449 1450 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1451 (void)agp_i810_unbind_page(sc, offset + j); 1452 return error; 1453 } 1454 1455 static int 1456 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1457 { 1458 struct agp_i810_softc *isc __diagused = sc->as_chipc; 1459 u_int32_t i; 1460 1461 if (!mem->am_is_bound) 1462 return EINVAL; 1463 1464 switch (mem->am_type) { 1465 case AGP_I810_MEMTYPE_MAIN: 1466 return agp_generic_unbind_memory(sc, mem); 1467 case AGP_I810_MEMTYPE_DCACHE: 1468 KASSERT(isc->chiptype == CHIP_I810); 1469 /* FALLTHROUGH */ 1470 case AGP_I810_MEMTYPE_HWCURSOR: 1471 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1472 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1473 mem->am_offset = 0; 1474 break; 1475 default: 1476 panic("invalid agp i810 memory type: %d", mem->am_type); 1477 } 1478 1479 mem->am_is_bound = 0; 1480 return 0; 1481 } 1482 1483 void 1484 agp_i810_reset(struct agp_i810_softc *isc) 1485 { 1486 1487 /* Restore the page table control register. */ 1488 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1489 isc->pgtblctl); 1490 1491 agp_flush_cache(); 1492 } 1493 1494 static bool 1495 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1496 { 1497 struct agp_softc *sc = device_private(dv); 1498 struct agp_i810_softc *isc = sc->as_chipc; 1499 1500 agp_i810_reset(isc); 1501 1502 return true; 1503 } 1504