1 /* $NetBSD: aceride.c,v 1.15 2005/05/24 05:25:15 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.15 2005/05/24 05:25:15 lukem Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_acer_reg.h> 43 44 static void acer_chip_map(struct pciide_softc*, struct pci_attach_args*); 45 static void acer_setup_channel(struct ata_channel*); 46 static int acer_pci_intr(void *); 47 48 static int aceride_match(struct device *, struct cfdata *, void *); 49 static void aceride_attach(struct device *, struct device *, void *); 50 51 CFATTACH_DECL(aceride, sizeof(struct pciide_softc), 52 aceride_match, aceride_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_acer_products[] = { 55 { PCI_PRODUCT_ALI_M5229, 56 0, 57 "Acer Labs M5229 UDMA IDE Controller", 58 acer_chip_map, 59 }, 60 { 0, 61 0, 62 NULL, 63 NULL 64 } 65 }; 66 67 static int 68 aceride_match(struct device *parent, struct cfdata *match, void *aux) 69 { 70 struct pci_attach_args *pa = aux; 71 72 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 73 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 74 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 75 if (pciide_lookup_product(pa->pa_id, pciide_acer_products)) 76 return (2); 77 } 78 return (0); 79 } 80 81 static void 82 aceride_attach(struct device *parent, struct device *self, void *aux) 83 { 84 struct pci_attach_args *pa = aux; 85 struct pciide_softc *sc = (struct pciide_softc *)self; 86 87 pciide_common_attach(sc, pa, 88 pciide_lookup_product(pa->pa_id, pciide_acer_products)); 89 90 } 91 92 static void 93 acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 94 { 95 struct pciide_channel *cp; 96 int channel; 97 pcireg_t cr, interface; 98 bus_size_t cmdsize, ctlsize; 99 pcireg_t rev = PCI_REVISION(pa->pa_class); 100 101 if (pciide_chipen(sc, pa) == 0) 102 return; 103 104 aprint_normal("%s: bus-master DMA support present", 105 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 106 pciide_mapreg_dma(sc, pa); 107 aprint_normal("\n"); 108 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 109 if (sc->sc_dma_ok) { 110 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 111 if (rev >= 0x20) { 112 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 113 if (rev >= 0xC4) 114 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 115 else if (rev >= 0xC2) 116 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 117 else 118 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 119 } 120 sc->sc_wdcdev.irqack = pciide_irqack; 121 } 122 123 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 124 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 125 sc->sc_wdcdev.sc_atac.atac_set_modes = acer_setup_channel; 126 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 127 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 128 129 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 130 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 131 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 132 133 /* Enable "microsoft register bits" R/W. */ 134 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 135 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 136 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 137 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 138 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 139 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 140 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 141 ~ACER_CHANSTATUSREGS_RO); 142 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 143 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 144 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 145 /* Don't use cr, re-read the real register content instead */ 146 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 147 PCI_CLASS_REG)); 148 149 /* From linux: enable "Cable Detection" */ 150 if (rev >= 0xC2) { 151 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 152 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 153 | ACER_0x4B_CDETECT); 154 } 155 156 wdc_allocate_regs(&sc->sc_wdcdev); 157 158 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 159 channel++) { 160 cp = &sc->pciide_channels[channel]; 161 if (pciide_chansetup(sc, channel, interface) == 0) 162 continue; 163 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 164 aprint_normal("%s: %s channel ignored (disabled)\n", 165 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 166 cp->ata_channel.ch_flags |= ATACH_DISABLED; 167 continue; 168 } 169 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 170 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 171 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 172 } 173 } 174 175 static void 176 acer_setup_channel(struct ata_channel *chp) 177 { 178 struct ata_drive_datas *drvp; 179 int drive, s; 180 u_int32_t acer_fifo_udma; 181 u_int32_t idedma_ctl; 182 struct pciide_channel *cp = (struct pciide_channel*)chp; 183 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 184 185 idedma_ctl = 0; 186 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 187 ATADEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 188 acer_fifo_udma), DEBUG_PROBE); 189 /* setup DMA if needed */ 190 pciide_channel_dma_setup(cp); 191 192 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 193 DRIVE_UDMA) { /* check 80 pins cable */ 194 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 195 ACER_0x4A_80PIN(chp->ch_channel)) { 196 if (chp->ch_drive[0].UDMA_mode > 2) 197 chp->ch_drive[0].UDMA_mode = 2; 198 if (chp->ch_drive[1].UDMA_mode > 2) 199 chp->ch_drive[1].UDMA_mode = 2; 200 } 201 } 202 203 for (drive = 0; drive < 2; drive++) { 204 drvp = &chp->ch_drive[drive]; 205 /* If no drive, skip */ 206 if ((drvp->drive_flags & DRIVE) == 0) 207 continue; 208 ATADEBUG_PRINT(("acer_setup_channel: old timings reg for " 209 "channel %d drive %d 0x%x\n", chp->ch_channel, drive, 210 pciide_pci_read(sc->sc_pc, sc->sc_tag, 211 ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE); 212 /* clear FIFO/DMA mode */ 213 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) | 214 ACER_UDMA_EN(chp->ch_channel, drive) | 215 ACER_UDMA_TIM(chp->ch_channel, drive, 0x7)); 216 217 /* add timing values, setup DMA if needed */ 218 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 219 (drvp->drive_flags & DRIVE_UDMA) == 0) { 220 acer_fifo_udma |= 221 ACER_FTH_OPL(chp->ch_channel, drive, 0x1); 222 goto pio; 223 } 224 225 acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2); 226 if (drvp->drive_flags & DRIVE_UDMA) { 227 /* use Ultra/DMA */ 228 s = splbio(); 229 drvp->drive_flags &= ~DRIVE_DMA; 230 splx(s); 231 acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive); 232 acer_fifo_udma |= 233 ACER_UDMA_TIM(chp->ch_channel, drive, 234 acer_udma[drvp->UDMA_mode]); 235 /* XXX disable if one drive < UDMA3 ? */ 236 if (drvp->UDMA_mode >= 3) { 237 pciide_pci_write(sc->sc_pc, sc->sc_tag, 238 ACER_0x4B, 239 pciide_pci_read(sc->sc_pc, sc->sc_tag, 240 ACER_0x4B) | ACER_0x4B_UDMA66); 241 } 242 } else { 243 /* 244 * use Multiword DMA 245 * Timings will be used for both PIO and DMA, 246 * so adjust DMA mode if needed 247 */ 248 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 249 drvp->PIO_mode = drvp->DMA_mode + 2; 250 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 251 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 252 drvp->PIO_mode - 2 : 0; 253 if (drvp->DMA_mode == 0) 254 drvp->PIO_mode = 0; 255 } 256 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 257 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 258 ACER_IDETIM(chp->ch_channel, drive), 259 acer_pio[drvp->PIO_mode]); 260 } 261 ATADEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 262 acer_fifo_udma), DEBUG_PROBE); 263 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 264 if (idedma_ctl != 0) { 265 /* Add software bits in status register */ 266 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 267 idedma_ctl); 268 } 269 } 270 271 static int 272 acer_pci_intr(void *arg) 273 { 274 struct pciide_softc *sc = arg; 275 struct pciide_channel *cp; 276 struct ata_channel *wdc_cp; 277 int i, rv, crv; 278 u_int32_t chids; 279 280 rv = 0; 281 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 282 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 283 cp = &sc->pciide_channels[i]; 284 wdc_cp = &cp->ata_channel; 285 /* If a compat channel skip. */ 286 if (cp->compat) 287 continue; 288 if (chids & ACER_CHIDS_INT(i)) { 289 crv = wdcintr(wdc_cp); 290 if (crv == 0) { 291 printf("%s:%d: bogus intr\n", 292 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 293 pciide_irqack(wdc_cp); 294 } else 295 rv = 1; 296 } 297 } 298 return rv; 299 } 300