xref: /netbsd-src/sys/dev/pci/aceride.c (revision 8b0f9554ff8762542c4defc4f70e1eb76fb508fa)
1 /*	$NetBSD: aceride.c,v 1.23 2007/02/09 21:55:27 ad Exp $	*/
2 
3 /*
4  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by Manuel Bouyer.
17  * 4. The name of the author may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.23 2007/02/09 21:55:27 ad Exp $");
34 
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 
38 #include <dev/pci/pcivar.h>
39 #include <dev/pci/pcidevs.h>
40 #include <dev/pci/pciidereg.h>
41 #include <dev/pci/pciidevar.h>
42 #include <dev/pci/pciide_acer_reg.h>
43 
44 static int acer_pcib_match(struct pci_attach_args *);
45 static void acer_do_reset(struct ata_channel *, int);
46 static void acer_chip_map(struct pciide_softc*, struct pci_attach_args*);
47 static void acer_setup_channel(struct ata_channel*);
48 static int  acer_pci_intr(void *);
49 
50 static int  aceride_match(struct device *, struct cfdata *, void *);
51 static void aceride_attach(struct device *, struct device *, void *);
52 
53 struct aceride_softc {
54 	struct pciide_softc pciide_sc;
55 	struct pci_attach_args pcib_pa;
56 };
57 
58 CFATTACH_DECL(aceride, sizeof(struct aceride_softc),
59     aceride_match, aceride_attach, NULL, NULL);
60 
61 static const struct pciide_product_desc pciide_acer_products[] =  {
62 	{ PCI_PRODUCT_ALI_M5229,
63 	  0,
64 	  "Acer Labs M5229 UDMA IDE Controller",
65 	  acer_chip_map,
66 	},
67 	{ 0,
68 	  0,
69 	  NULL,
70 	  NULL
71 	}
72 };
73 
74 static int
75 aceride_match(struct device *parent, struct cfdata *match,
76     void *aux)
77 {
78 	struct pci_attach_args *pa = aux;
79 
80 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
81 	    PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
82 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
83 		if (pciide_lookup_product(pa->pa_id, pciide_acer_products))
84 			return (2);
85 	}
86 	return (0);
87 }
88 
89 static void
90 aceride_attach(struct device *parent, struct device *self, void *aux)
91 {
92 	struct pci_attach_args *pa = aux;
93 	struct pciide_softc *sc = (struct pciide_softc *)self;
94 
95 	pciide_common_attach(sc, pa,
96 	    pciide_lookup_product(pa->pa_id, pciide_acer_products));
97 
98 }
99 
100 static int
101 acer_pcib_match(struct pci_attach_args *pa)
102 {
103 	/*
104 	 * we need to access the PCI config space of the pcib, see
105 	 * acer_do_reset()
106 	 */
107 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
108 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
109 	    PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
110 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)
111 		return 1;
112 	return 0;
113 }
114 
115 static void
116 acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
117 {
118 	struct pciide_channel *cp;
119 	int channel;
120 	pcireg_t cr, interface;
121 	bus_size_t cmdsize, ctlsize;
122 	pcireg_t rev = PCI_REVISION(pa->pa_class);
123 	struct aceride_softc *acer_sc = (struct aceride_softc *)sc;
124 
125 	if (pciide_chipen(sc, pa) == 0)
126 		return;
127 
128 	aprint_verbose("%s: bus-master DMA support present",
129 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
130 	pciide_mapreg_dma(sc, pa);
131 	aprint_verbose("\n");
132 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
133 	if (sc->sc_dma_ok) {
134 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
135 		if (rev >= 0x20) {
136 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
137 			if (rev >= 0xC7)
138 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
139 			else if (rev >= 0xC4)
140 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
141 			else if (rev >= 0xC2)
142 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
143 			else
144 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
145 		}
146 		sc->sc_wdcdev.irqack = pciide_irqack;
147 	}
148 
149 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
150 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
151 	sc->sc_wdcdev.sc_atac.atac_set_modes = acer_setup_channel;
152 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
153 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
154 
155 	pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC,
156 	    (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) |
157 		ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE);
158 
159 	/* Enable "microsoft register bits" R/W. */
160 	pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3,
161 	    pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI);
162 	pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1,
163 	    pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) &
164 	    ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1)));
165 	pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2,
166 	    pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) &
167 	    ~ACER_CHANSTATUSREGS_RO);
168 	cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG);
169 	cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT);
170 	pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr);
171 	/* Don't use cr, re-read the real register content instead */
172 	interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag,
173 	    PCI_CLASS_REG));
174 
175 	/* From linux: enable "Cable Detection" */
176 	if (rev >= 0xC2) {
177 		pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B,
178 		    pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B)
179 		    | ACER_0x4B_CDETECT);
180 	}
181 
182 	wdc_allocate_regs(&sc->sc_wdcdev);
183 	if (rev == 0xC3) {
184 		/* install reset bug workaround */
185 		if (pci_find_device(&acer_sc->pcib_pa, acer_pcib_match) == 0) {
186 			printf("%s: WARNING: can't find pci-isa bridge\n",
187 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
188 		} else
189 			sc->sc_wdcdev.reset = acer_do_reset;
190 	}
191 
192 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
193 	     channel++) {
194 		cp = &sc->pciide_channels[channel];
195 		if (pciide_chansetup(sc, channel, interface) == 0)
196 			continue;
197 		if ((interface & PCIIDE_CHAN_EN(channel)) == 0) {
198 			aprint_normal("%s: %s channel ignored (disabled)\n",
199 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
200 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
201 			continue;
202 		}
203 		/* newer controllers seems to lack the ACER_CHIDS. Sigh */
204 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
205 		     (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr);
206 	}
207 }
208 
209 static void
210 acer_do_reset(struct ata_channel *chp, int poll)
211 {
212 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
213 	struct aceride_softc *acer_sc = (struct aceride_softc *)sc;
214 	u_int8_t reg;
215 
216 	/*
217 	 * From OpenSolaris: after a reset we need to disable/enable the
218 	 * corresponding channel, or data corruption will occur in
219 	 * UltraDMA modes
220 	 */
221 
222 	wdc_do_reset(chp, poll);
223 	reg = pciide_pci_read(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
224 	    ACER_PCIB_CTRL);
225 	pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
226 	    ACER_PCIB_CTRL, reg & ~ACER_PCIB_CTRL_ENCHAN(chp->ch_channel));
227 	delay(1000);
228 	pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
229 	    ACER_PCIB_CTRL, reg);
230 }
231 
232 static void
233 acer_setup_channel(struct ata_channel *chp)
234 {
235 	struct ata_drive_datas *drvp;
236 	int drive, s;
237 	u_int32_t acer_fifo_udma;
238 	u_int32_t idedma_ctl;
239 	struct pciide_channel *cp = (struct pciide_channel*)chp;
240 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
241 
242 	idedma_ctl = 0;
243 	acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA);
244 	ATADEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n",
245 	    acer_fifo_udma), DEBUG_PROBE);
246 	/* setup DMA if needed */
247 	pciide_channel_dma_setup(cp);
248 
249 	if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) &
250 	    DRIVE_UDMA) { /* check 80 pins cable */
251 		if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) &
252 		    ACER_0x4A_80PIN(chp->ch_channel)) {
253 			if (chp->ch_drive[0].UDMA_mode > 2)
254 				chp->ch_drive[0].UDMA_mode = 2;
255 			if (chp->ch_drive[1].UDMA_mode > 2)
256 				chp->ch_drive[1].UDMA_mode = 2;
257 		}
258 	}
259 
260 	for (drive = 0; drive < 2; drive++) {
261 		drvp = &chp->ch_drive[drive];
262 		/* If no drive, skip */
263 		if ((drvp->drive_flags & DRIVE) == 0)
264 			continue;
265 		ATADEBUG_PRINT(("acer_setup_channel: old timings reg for "
266 		    "channel %d drive %d 0x%x\n", chp->ch_channel, drive,
267 		    pciide_pci_read(sc->sc_pc, sc->sc_tag,
268 		    ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE);
269 		/* clear FIFO/DMA mode */
270 		acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) |
271 		    ACER_UDMA_EN(chp->ch_channel, drive) |
272 		    ACER_UDMA_TIM(chp->ch_channel, drive, 0x7));
273 
274 		/* add timing values, setup DMA if needed */
275 		if ((drvp->drive_flags & DRIVE_DMA) == 0 &&
276 		    (drvp->drive_flags & DRIVE_UDMA) == 0) {
277 			acer_fifo_udma |=
278 			    ACER_FTH_OPL(chp->ch_channel, drive, 0x1);
279 			goto pio;
280 		}
281 
282 		acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2);
283 		if (drvp->drive_flags & DRIVE_UDMA) {
284 			/* use Ultra/DMA */
285 			s = splbio();
286 			drvp->drive_flags &= ~DRIVE_DMA;
287 			splx(s);
288 			acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive);
289 			acer_fifo_udma |=
290 			    ACER_UDMA_TIM(chp->ch_channel, drive,
291 				acer_udma[drvp->UDMA_mode]);
292 			/* XXX disable if one drive < UDMA3 ? */
293 			if (drvp->UDMA_mode >= 3) {
294 				pciide_pci_write(sc->sc_pc, sc->sc_tag,
295 				    ACER_0x4B,
296 				    pciide_pci_read(sc->sc_pc, sc->sc_tag,
297 					ACER_0x4B) | ACER_0x4B_UDMA66);
298 			}
299 		} else {
300 			/*
301 			 * use Multiword DMA
302 			 * Timings will be used for both PIO and DMA,
303 			 * so adjust DMA mode if needed
304 			 */
305 			if (drvp->PIO_mode > (drvp->DMA_mode + 2))
306 				drvp->PIO_mode = drvp->DMA_mode + 2;
307 			if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
308 				drvp->DMA_mode = (drvp->PIO_mode > 2) ?
309 				    drvp->PIO_mode - 2 : 0;
310 			if (drvp->DMA_mode == 0)
311 				drvp->PIO_mode = 0;
312 		}
313 		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
314 pio:		pciide_pci_write(sc->sc_pc, sc->sc_tag,
315 		    ACER_IDETIM(chp->ch_channel, drive),
316 		    acer_pio[drvp->PIO_mode]);
317 	}
318 	ATADEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n",
319 	    acer_fifo_udma), DEBUG_PROBE);
320 	pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma);
321 	if (idedma_ctl != 0) {
322 		/* Add software bits in status register */
323 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
324 		    idedma_ctl);
325 	}
326 }
327 
328 static int
329 acer_pci_intr(void *arg)
330 {
331 	struct pciide_softc *sc = arg;
332 	struct pciide_channel *cp;
333 	struct ata_channel *wdc_cp;
334 	int i, rv, crv;
335 	u_int32_t chids;
336 
337 	rv = 0;
338 	chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS);
339 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
340 		cp = &sc->pciide_channels[i];
341 		wdc_cp = &cp->ata_channel;
342 		/* If a compat channel skip. */
343 		if (cp->compat)
344 			continue;
345 		if (chids & ACER_CHIDS_INT(i)) {
346 			crv = wdcintr(wdc_cp);
347 			if (crv == 0) {
348 				printf("%s:%d: bogus intr\n",
349 				    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i);
350 				pciide_irqack(wdc_cp);
351 			} else
352 				rv = 1;
353 		}
354 	}
355 	return rv;
356 }
357