1 /* $NetBSD: acardide.c,v 1.22 2008/03/18 20:46:36 cube Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Izumi Tsutsui. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acardide.c,v 1.22 2008/03/18 20:46:36 cube Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_acard_reg.h> 40 41 static void acard_chip_map(struct pciide_softc*, struct pci_attach_args*); 42 static void acard_setup_channel(struct ata_channel*); 43 #if 0 /* XXX !! */ 44 static int acard_pci_intr(void *); 45 #endif 46 47 static int acardide_match(device_t, cfdata_t, void *); 48 static void acardide_attach(device_t, device_t, void *); 49 50 CFATTACH_DECL_NEW(acardide, sizeof(struct pciide_softc), 51 acardide_match, acardide_attach, NULL, NULL); 52 53 static const struct pciide_product_desc pciide_acard_products[] = { 54 { PCI_PRODUCT_ACARD_ATP850U, 55 0, 56 "Acard ATP850U Ultra33 IDE Controller", 57 acard_chip_map, 58 }, 59 { PCI_PRODUCT_ACARD_ATP860, 60 0, 61 "Acard ATP860 Ultra66 IDE Controller", 62 acard_chip_map, 63 }, 64 { PCI_PRODUCT_ACARD_ATP860A, 65 0, 66 "Acard ATP860-A Ultra66 IDE Controller", 67 acard_chip_map, 68 }, 69 { PCI_PRODUCT_ACARD_ATP865, 70 0, 71 "Acard ATP865 Ultra133 IDE Controller", 72 acard_chip_map, 73 }, 74 { PCI_PRODUCT_ACARD_ATP865A, 75 0, 76 "Acard ATP865-A Ultra133 IDE Controller", 77 acard_chip_map, 78 }, 79 { 0, 80 0, 81 NULL, 82 NULL 83 } 84 }; 85 86 static int 87 acardide_match(device_t parent, cfdata_t match, void *aux) 88 { 89 struct pci_attach_args *pa = aux; 90 91 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ACARD) { 92 if (pciide_lookup_product(pa->pa_id, pciide_acard_products)) 93 return (2); 94 } 95 return (0); 96 } 97 98 static void 99 acardide_attach(device_t parent, device_t self, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 struct pciide_softc *sc = device_private(self); 103 104 sc->sc_wdcdev.sc_atac.atac_dev = self; 105 106 pciide_common_attach(sc, pa, 107 pciide_lookup_product(pa->pa_id, pciide_acard_products)); 108 109 } 110 111 #define ACARD_IS_850(sc) \ 112 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 113 114 static void 115 acard_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 116 { 117 struct pciide_channel *cp; 118 int i; 119 pcireg_t interface; 120 bus_size_t cmdsize, ctlsize; 121 122 if (pciide_chipen(sc, pa) == 0) 123 return; 124 125 /* 126 * when the chip is in native mode it identifies itself as a 127 * 'misc mass storage'. Fake interface in this case. 128 */ 129 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 130 interface = PCI_INTERFACE(pa->pa_class); 131 } else { 132 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 133 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 134 } 135 136 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 137 "bus-master DMA support present"); 138 pciide_mapreg_dma(sc, pa); 139 aprint_verbose("\n"); 140 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 141 142 if (sc->sc_dma_ok) { 143 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 144 sc->sc_wdcdev.irqack = pciide_irqack; 145 } 146 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 147 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 148 switch (sc->sc_pp->ide_product) { 149 case PCI_PRODUCT_ACARD_ATP860: 150 case PCI_PRODUCT_ACARD_ATP860A: 151 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 152 break; 153 case PCI_PRODUCT_ACARD_ATP865: 154 case PCI_PRODUCT_ACARD_ATP865A: 155 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 156 break; 157 default: 158 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 159 break; 160 } 161 162 sc->sc_wdcdev.sc_atac.atac_set_modes = acard_setup_channel; 163 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 164 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 165 166 wdc_allocate_regs(&sc->sc_wdcdev); 167 168 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 169 cp = &sc->pciide_channels[i]; 170 if (pciide_chansetup(sc, i, interface) == 0) 171 continue; 172 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 173 pciide_pci_intr); 174 } 175 if (!ACARD_IS_850(sc)) { 176 u_int32_t reg; 177 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 178 reg &= ~ATP860_CTRL_INT; 179 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 180 } 181 } 182 183 static void 184 acard_setup_channel(struct ata_channel *chp) 185 { 186 struct ata_drive_datas *drvp; 187 struct atac_softc *atac = chp->ch_atac; 188 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 189 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 190 int channel = chp->ch_channel; 191 int drive, s; 192 u_int32_t idetime, udma_mode; 193 u_int32_t idedma_ctl; 194 195 /* setup DMA if needed */ 196 pciide_channel_dma_setup(cp); 197 198 if (ACARD_IS_850(sc)) { 199 idetime = 0; 200 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 201 udma_mode &= ~ATP850_UDMA_MASK(channel); 202 } else { 203 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 204 idetime &= ~ATP860_SETTIME_MASK(channel); 205 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 206 udma_mode &= ~ATP860_UDMA_MASK(channel); 207 208 /* check 80 pins cable */ 209 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 210 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 211 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 212 & ATP860_CTRL_80P(chp->ch_channel)) { 213 if (chp->ch_drive[0].UDMA_mode > 2) 214 chp->ch_drive[0].UDMA_mode = 2; 215 if (chp->ch_drive[1].UDMA_mode > 2) 216 chp->ch_drive[1].UDMA_mode = 2; 217 } 218 } 219 } 220 221 idedma_ctl = 0; 222 223 /* Per drive settings */ 224 for (drive = 0; drive < 2; drive++) { 225 drvp = &chp->ch_drive[drive]; 226 /* If no drive, skip */ 227 if ((drvp->drive_flags & DRIVE) == 0) 228 continue; 229 /* add timing values, setup DMA if needed */ 230 if ((atac->atac_cap & ATAC_CAP_UDMA) && 231 (drvp->drive_flags & DRIVE_UDMA)) { 232 /* use Ultra/DMA */ 233 if (ACARD_IS_850(sc)) { 234 idetime |= ATP850_SETTIME(drive, 235 acard_act_udma[drvp->UDMA_mode], 236 acard_rec_udma[drvp->UDMA_mode]); 237 udma_mode |= ATP850_UDMA_MODE(channel, drive, 238 acard_udma_conf[drvp->UDMA_mode]); 239 } else { 240 idetime |= ATP860_SETTIME(channel, drive, 241 acard_act_udma[drvp->UDMA_mode], 242 acard_rec_udma[drvp->UDMA_mode]); 243 udma_mode |= ATP860_UDMA_MODE(channel, drive, 244 acard_udma_conf[drvp->UDMA_mode]); 245 } 246 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 247 } else if ((atac->atac_cap & ATAC_CAP_DMA) && 248 (drvp->drive_flags & DRIVE_DMA)) { 249 /* use Multiword DMA */ 250 s = splbio(); 251 drvp->drive_flags &= ~DRIVE_UDMA; 252 splx(s); 253 if (ACARD_IS_850(sc)) { 254 idetime |= ATP850_SETTIME(drive, 255 acard_act_dma[drvp->DMA_mode], 256 acard_rec_dma[drvp->DMA_mode]); 257 } else { 258 idetime |= ATP860_SETTIME(channel, drive, 259 acard_act_dma[drvp->DMA_mode], 260 acard_rec_dma[drvp->DMA_mode]); 261 } 262 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 263 } else { 264 /* PIO only */ 265 s = splbio(); 266 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 267 splx(s); 268 if (ACARD_IS_850(sc)) { 269 idetime |= ATP850_SETTIME(drive, 270 acard_act_pio[drvp->PIO_mode], 271 acard_rec_pio[drvp->PIO_mode]); 272 } else { 273 idetime |= ATP860_SETTIME(channel, drive, 274 acard_act_pio[drvp->PIO_mode], 275 acard_rec_pio[drvp->PIO_mode]); 276 } 277 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 278 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 279 | ATP8x0_CTRL_EN(channel)); 280 } 281 } 282 283 if (idedma_ctl != 0) { 284 /* Add software bits in status register */ 285 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 286 idedma_ctl); 287 } 288 289 if (ACARD_IS_850(sc)) { 290 pci_conf_write(sc->sc_pc, sc->sc_tag, 291 ATP850_IDETIME(channel), idetime); 292 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 293 } else { 294 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 295 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 296 } 297 } 298 299 #if 0 /* XXX !! */ 300 static int 301 acard_pci_intr(void *arg) 302 { 303 struct pciide_softc *sc = arg; 304 struct pciide_channel *cp; 305 struct ata_channel *wdc_cp; 306 int rv = 0; 307 int dmastat, i, crv; 308 309 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 310 cp = &sc->pciide_channels[i]; 311 dmastat = bus_space_read_1(sc->sc_dma_iot, 312 cp->dma_iohs[IDEDMA_CTL], 0); 313 if ((dmastat & IDEDMA_CTL_INTR) == 0) 314 continue; 315 wdc_cp = &cp->ata_channel; 316 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) { 317 (void)wdcintr(wdc_cp); 318 bus_space_write_1(sc->sc_dma_iot, 319 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 320 continue; 321 } 322 crv = wdcintr(wdc_cp); 323 if (crv == 0) { 324 printf("%s:%d: bogus intr\n", 325 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i); 326 bus_space_write_1(sc->sc_dma_iot, 327 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 328 } else if (crv == 1) 329 rv = 1; 330 else if (rv == 0) 331 rv = crv; 332 } 333 return rv; 334 } 335 #endif 336