1 /* $NetBSD: aac_pci.c,v 1.32 2011/02/18 22:54:27 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * Copyright (c) 2000 Niklas Hallqvist 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp 60 * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp 61 */ 62 63 /* 64 * PCI front-end for the `aac' driver. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.32 2011/02/18 22:54:27 jmcneill Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 77 #include <sys/bus.h> 78 #include <machine/endian.h> 79 #include <sys/intr.h> 80 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 85 #include <dev/ic/aacreg.h> 86 #include <dev/ic/aacvar.h> 87 88 struct aac_pci_softc { 89 struct aac_softc sc_aac; 90 pci_chipset_tag_t sc_pc; 91 pci_intr_handle_t sc_ih; 92 }; 93 94 /* i960Rx interface */ 95 static int aac_rx_get_fwstatus(struct aac_softc *); 96 static void aac_rx_qnotify(struct aac_softc *, int); 97 static int aac_rx_get_istatus(struct aac_softc *); 98 static void aac_rx_clear_istatus(struct aac_softc *, int); 99 static void aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, u_int32_t); 101 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int); 102 static void aac_rx_set_interrupts(struct aac_softc *, int); 103 static int aac_rx_send_command(struct aac_softc *, struct aac_ccb *); 104 static int aac_rx_get_outb_queue(struct aac_softc *); 105 static void aac_rx_set_outb_queue(struct aac_softc *, int); 106 107 /* StrongARM interface */ 108 static int aac_sa_get_fwstatus(struct aac_softc *); 109 static void aac_sa_qnotify(struct aac_softc *, int); 110 static int aac_sa_get_istatus(struct aac_softc *); 111 static void aac_sa_clear_istatus(struct aac_softc *, int); 112 static void aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 113 u_int32_t, u_int32_t, u_int32_t); 114 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int); 115 static void aac_sa_set_interrupts(struct aac_softc *, int); 116 117 /* Rocket/MIPS interface */ 118 static int aac_rkt_get_fwstatus(struct aac_softc *); 119 static void aac_rkt_qnotify(struct aac_softc *, int); 120 static int aac_rkt_get_istatus(struct aac_softc *); 121 static void aac_rkt_clear_istatus(struct aac_softc *, int); 122 static void aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 123 u_int32_t, u_int32_t, u_int32_t); 124 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int); 125 static void aac_rkt_set_interrupts(struct aac_softc *, int); 126 static int aac_rkt_send_command(struct aac_softc *, struct aac_ccb *); 127 static int aac_rkt_get_outb_queue(struct aac_softc *); 128 static void aac_rkt_set_outb_queue(struct aac_softc *, int); 129 130 static const struct aac_interface aac_rx_interface = { 131 aac_rx_get_fwstatus, 132 aac_rx_qnotify, 133 aac_rx_get_istatus, 134 aac_rx_clear_istatus, 135 aac_rx_set_mailbox, 136 aac_rx_get_mailbox, 137 aac_rx_set_interrupts, 138 aac_rx_send_command, 139 aac_rx_get_outb_queue, 140 aac_rx_set_outb_queue 141 }; 142 143 static const struct aac_interface aac_sa_interface = { 144 aac_sa_get_fwstatus, 145 aac_sa_qnotify, 146 aac_sa_get_istatus, 147 aac_sa_clear_istatus, 148 aac_sa_set_mailbox, 149 aac_sa_get_mailbox, 150 aac_sa_set_interrupts, 151 NULL, NULL, NULL 152 }; 153 154 static const struct aac_interface aac_rkt_interface = { 155 aac_rkt_get_fwstatus, 156 aac_rkt_qnotify, 157 aac_rkt_get_istatus, 158 aac_rkt_clear_istatus, 159 aac_rkt_set_mailbox, 160 aac_rkt_get_mailbox, 161 aac_rkt_set_interrupts, 162 aac_rkt_send_command, 163 aac_rkt_get_outb_queue, 164 aac_rkt_set_outb_queue 165 }; 166 167 static struct aac_ident { 168 u_short vendor; 169 u_short device; 170 u_short subvendor; 171 u_short subdevice; 172 u_short hwif; 173 u_short quirks; 174 const char *prodstr; 175 } const aac_ident[] = { 176 { 177 PCI_VENDOR_DELL, 178 PCI_PRODUCT_DELL_PERC_2SI, 179 PCI_VENDOR_DELL, 180 PCI_PRODUCT_DELL_PERC_2SI, 181 AAC_HWIF_I960RX, 182 0, 183 "Dell PERC 2/Si" 184 }, 185 { 186 PCI_VENDOR_DELL, 187 PCI_PRODUCT_DELL_PERC_3DI, 188 PCI_VENDOR_DELL, 189 PCI_PRODUCT_DELL_PERC_3DI, 190 AAC_HWIF_I960RX, 191 0, 192 "Dell PERC 3/Di" 193 }, 194 { 195 PCI_VENDOR_DELL, 196 PCI_PRODUCT_DELL_PERC_3DI, 197 PCI_VENDOR_DELL, 198 PCI_PRODUCT_DELL_PERC_3DI_SUB2, 199 AAC_HWIF_I960RX, 200 0, 201 "Dell PERC 3/Di" 202 }, 203 { 204 PCI_VENDOR_DELL, 205 PCI_PRODUCT_DELL_PERC_3DI, 206 PCI_VENDOR_DELL, 207 PCI_PRODUCT_DELL_PERC_3DI_SUB3, 208 AAC_HWIF_I960RX, 209 0, 210 "Dell PERC 3/Di" 211 }, 212 { 213 PCI_VENDOR_DELL, 214 PCI_PRODUCT_DELL_PERC_3DI_2, 215 PCI_VENDOR_DELL, 216 PCI_PRODUCT_DELL_PERC_3DI_2_SUB, 217 AAC_HWIF_I960RX, 218 0, 219 "Dell PERC 3/Di" 220 }, 221 { 222 PCI_VENDOR_DELL, 223 PCI_PRODUCT_DELL_PERC_3DI_3, 224 PCI_VENDOR_DELL, 225 PCI_PRODUCT_DELL_PERC_3DI_3_SUB, 226 AAC_HWIF_I960RX, 227 0, 228 "Dell PERC 3/Di" 229 }, 230 { 231 PCI_VENDOR_DELL, 232 PCI_PRODUCT_DELL_PERC_3DI_3, 233 PCI_VENDOR_DELL, 234 PCI_PRODUCT_DELL_PERC_3DI_3_SUB2, 235 AAC_HWIF_I960RX, 236 0, 237 "Dell PERC 3/Di" 238 }, 239 { 240 PCI_VENDOR_DELL, 241 PCI_PRODUCT_DELL_PERC_3DI_3, 242 PCI_VENDOR_DELL, 243 PCI_PRODUCT_DELL_PERC_3DI_3_SUB3, 244 AAC_HWIF_I960RX, 245 0, 246 "Dell PERC 3/Di" 247 }, 248 { 249 PCI_VENDOR_DELL, 250 PCI_PRODUCT_DELL_PERC_3SI, 251 PCI_VENDOR_DELL, 252 PCI_PRODUCT_DELL_PERC_3SI, 253 AAC_HWIF_I960RX, 254 0, 255 "Dell PERC 3/Si" 256 }, 257 { 258 PCI_VENDOR_DELL, 259 PCI_PRODUCT_DELL_PERC_3SI_2, 260 PCI_VENDOR_DELL, 261 PCI_PRODUCT_DELL_PERC_3SI_2_SUB, 262 AAC_HWIF_I960RX, 263 0, 264 "Dell PERC 3/Si" 265 }, 266 { 267 PCI_VENDOR_ADP2, 268 PCI_PRODUCT_ADP2_ASR2200S, 269 PCI_VENDOR_DELL, 270 PCI_PRODUCT_DELL_CERC_1_5, 271 AAC_HWIF_I960RX, 272 AAC_QUIRK_NO4GB, 273 "Dell CERC SATA RAID 1.5/6ch" 274 }, 275 { 276 PCI_VENDOR_ADP2, 277 PCI_PRODUCT_ADP2_AAC2622, 278 PCI_VENDOR_ADP2, 279 PCI_PRODUCT_ADP2_AAC2622, 280 AAC_HWIF_I960RX, 281 0, 282 "Adaptec ADP-2622" 283 }, 284 { 285 PCI_VENDOR_ADP2, 286 PCI_PRODUCT_ADP2_ASR2200S, 287 PCI_VENDOR_ADP2, 288 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 289 AAC_HWIF_I960RX, 290 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 291 "Adaptec ASR-2200S" 292 }, 293 { 294 PCI_VENDOR_ADP2, 295 PCI_PRODUCT_ADP2_ASR2200S, 296 PCI_VENDOR_DELL, 297 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 298 AAC_HWIF_I960RX, 299 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 300 "Dell PERC 320/DC" 301 }, 302 { 303 PCI_VENDOR_ADP2, 304 PCI_PRODUCT_ADP2_ASR2200S, 305 PCI_VENDOR_ADP2, 306 PCI_PRODUCT_ADP2_ASR2200S, 307 AAC_HWIF_I960RX, 308 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 309 "Adaptec ASR-2200S" 310 }, 311 { 312 PCI_VENDOR_ADP2, 313 PCI_PRODUCT_ADP2_ASR2200S, 314 PCI_VENDOR_ADP2, 315 PCI_PRODUCT_ADP2_AAR2810SA, 316 AAC_HWIF_I960RX, 317 AAC_QUIRK_NO4GB, 318 "Adaptec AAR-2810SA" 319 }, 320 { 321 PCI_VENDOR_ADP2, 322 PCI_PRODUCT_ADP2_ASR2200S, 323 PCI_VENDOR_ADP2, 324 PCI_PRODUCT_ADP2_ASR2120S, 325 AAC_HWIF_I960RX, 326 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 327 "Adaptec ASR-2120S" 328 }, 329 { 330 PCI_VENDOR_ADP2, 331 PCI_PRODUCT_ADP2_ASR2200S, 332 PCI_VENDOR_ADP2, 333 PCI_PRODUCT_ADP2_ASR2410SA, 334 AAC_HWIF_I960RX, 335 AAC_QUIRK_NO4GB, 336 "Adaptec ASR-2410SA" 337 }, 338 { 339 PCI_VENDOR_ADP2, 340 PCI_PRODUCT_ADP2_ASR2200S, 341 PCI_VENDOR_HP, 342 PCI_PRODUCT_ADP2_HP_M110_G2, 343 AAC_HWIF_I960RX, 344 AAC_QUIRK_NO4GB, 345 "HP ML110 G2 (Adaptec ASR-2610SA)" 346 }, 347 { 348 PCI_VENDOR_ADP2, 349 PCI_PRODUCT_ADP2_ASR2120S, 350 PCI_VENDOR_IBM, 351 PCI_PRODUCT_IBM_SERVERAID8K, 352 AAC_HWIF_RKT, 353 0, 354 "IBM ServeRAID 8k" 355 }, 356 { PCI_VENDOR_ADP2, 357 PCI_PRODUCT_ADP2_ASR2200S, 358 PCI_VENDOR_ADP2, 359 PCI_PRODUCT_ADP2_3405, 360 AAC_HWIF_I960RX, 361 0, 362 "Adaptec RAID 3405" 363 }, 364 { 365 PCI_VENDOR_DEC, 366 PCI_PRODUCT_DEC_21554, 367 PCI_VENDOR_ADP2, 368 PCI_PRODUCT_ADP2_AAC364, 369 AAC_HWIF_STRONGARM, 370 0, 371 "Adaptec AAC-364" 372 }, 373 { 374 PCI_VENDOR_DEC, 375 PCI_PRODUCT_DEC_21554, 376 PCI_VENDOR_ADP2, 377 PCI_PRODUCT_ADP2_ASR5400S, 378 AAC_HWIF_STRONGARM, 379 AAC_QUIRK_BROKEN_MMAP, 380 "Adaptec ASR-5400S" 381 }, 382 { 383 PCI_VENDOR_DEC, 384 PCI_PRODUCT_DEC_21554, 385 PCI_VENDOR_ADP2, 386 PCI_PRODUCT_ADP2_PERC_2QC, 387 AAC_HWIF_STRONGARM, 388 AAC_QUIRK_PERC2QC, 389 "Dell PERC 2/QC" 390 }, 391 { 392 PCI_VENDOR_DEC, 393 PCI_PRODUCT_DEC_21554, 394 PCI_VENDOR_ADP2, 395 PCI_PRODUCT_ADP2_PERC_3QC, 396 AAC_HWIF_STRONGARM, 397 0, 398 "Dell PERC 3/QC" 399 }, 400 { 401 PCI_VENDOR_DEC, 402 PCI_PRODUCT_DEC_21554, 403 PCI_VENDOR_HP, 404 PCI_PRODUCT_HP_NETRAID_4M, 405 AAC_HWIF_STRONGARM, 406 0, 407 "HP NetRAID-4M" 408 }, 409 { 0x9005, 410 0x0285, 411 0x108e, 412 0x286, 413 AAC_HWIF_I960RX, 414 0, 415 "SG-XPCIESAS-R-IN" 416 }, 417 }; 418 419 static const struct aac_ident * 420 aac_find_ident(struct pci_attach_args *pa) 421 { 422 const struct aac_ident *m, *mm; 423 u_int32_t subsysid; 424 425 m = aac_ident; 426 mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0])); 427 428 while (m < mm) { 429 if (m->vendor == PCI_VENDOR(pa->pa_id) && 430 m->device == PCI_PRODUCT(pa->pa_id)) { 431 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, 432 PCI_SUBSYS_ID_REG); 433 if (m->subvendor == PCI_VENDOR(subsysid) && 434 m->subdevice == PCI_PRODUCT(subsysid)) 435 return (m); 436 } 437 m++; 438 } 439 440 return (NULL); 441 } 442 443 static int 444 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg) 445 { 446 struct aac_pci_softc *pcisc; 447 448 pcisc = (struct aac_pci_softc *) sc; 449 450 pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih); 451 sc->sc_ih = pci_intr_establish(pcisc->sc_pc, pcisc->sc_ih, 452 IPL_BIO, hand, arg); 453 if (sc->sc_ih == NULL) { 454 return ENXIO; 455 } 456 return 0; 457 } 458 459 static int 460 aac_pci_match(device_t parent, cfdata_t match, void *aux) 461 { 462 struct pci_attach_args *pa; 463 464 pa = aux; 465 466 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 467 return (0); 468 469 return (aac_find_ident(pa) != NULL); 470 } 471 472 static void 473 aac_pci_attach(device_t parent, device_t self, void *aux) 474 { 475 struct pci_attach_args *pa; 476 pci_chipset_tag_t pc; 477 struct aac_pci_softc *pcisc; 478 struct aac_softc *sc; 479 u_int16_t command; 480 bus_addr_t membase; 481 bus_size_t memsize; 482 const char *intrstr; 483 int state; 484 const struct aac_ident *m; 485 486 pa = aux; 487 pc = pa->pa_pc; 488 pcisc = device_private(self); 489 pcisc->sc_pc = pc; 490 sc = &pcisc->sc_aac; 491 state = 0; 492 493 aprint_naive(": RAID controller\n"); 494 aprint_normal(": "); 495 496 /* 497 * Verify that the adapter is correctly set up in PCI space. 498 */ 499 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 500 command |= PCI_COMMAND_MASTER_ENABLE; 501 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 502 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 503 AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x ")); 504 505 if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) { 506 aprint_error("can't enable bus-master feature\n"); 507 goto bail_out; 508 } 509 510 if ((command & PCI_COMMAND_MEM_ENABLE) == 0) { 511 aprint_error("memory window not available\n"); 512 goto bail_out; 513 } 514 515 /* 516 * Map control/status registers. 517 */ 518 if (pci_mapreg_map(pa, PCI_MAPREG_START, 519 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt, 520 &sc->sc_memh, &membase, &memsize)) { 521 aprint_error("can't find mem space\n"); 522 goto bail_out; 523 } 524 state++; 525 526 if (pci_intr_map(pa, &pcisc->sc_ih)) { 527 aprint_error("couldn't map interrupt\n"); 528 goto bail_out; 529 } 530 intrstr = pci_intr_string(pc, pcisc->sc_ih); 531 sc->sc_ih = pci_intr_establish(pc, pcisc->sc_ih, IPL_BIO, aac_intr, sc); 532 if (sc->sc_ih == NULL) { 533 aprint_error("couldn't establish interrupt"); 534 if (intrstr != NULL) 535 aprint_error(" at %s", intrstr); 536 aprint_error("\n"); 537 goto bail_out; 538 } 539 state++; 540 541 sc->sc_dmat = pa->pa_dmat; 542 543 m = aac_find_ident(pa); 544 aprint_normal("%s\n", m->prodstr); 545 if (intrstr != NULL) 546 aprint_normal_dev(&sc->sc_dv, "interrupting at %s\n", 547 intrstr); 548 549 sc->sc_hwif = m->hwif; 550 sc->sc_quirks = m->quirks; 551 switch (sc->sc_hwif) { 552 case AAC_HWIF_I960RX: 553 AAC_DPRINTF(AAC_D_MISC, 554 ("set hardware up for i960Rx")); 555 sc->sc_if = aac_rx_interface; 556 break; 557 558 case AAC_HWIF_STRONGARM: 559 AAC_DPRINTF(AAC_D_MISC, 560 ("set hardware up for StrongARM")); 561 sc->sc_if = aac_sa_interface; 562 break; 563 564 case AAC_HWIF_RKT: 565 AAC_DPRINTF(AAC_D_MISC, 566 ("set hardware up for MIPS/Rocket")); 567 sc->sc_if = aac_rkt_interface; 568 break; 569 } 570 sc->sc_regsize = memsize; 571 sc->sc_intr_set = aac_pci_intr_set; 572 573 if (!aac_attach(sc)) 574 return; 575 576 bail_out: 577 if (state > 1) 578 pci_intr_disestablish(pc, sc->sc_ih); 579 if (state > 0) 580 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 581 } 582 583 CFATTACH_DECL(aac_pci, sizeof(struct aac_pci_softc), 584 aac_pci_match, aac_pci_attach, NULL, NULL); 585 586 /* 587 * Read the current firmware status word. 588 */ 589 static int 590 aac_sa_get_fwstatus(struct aac_softc *sc) 591 { 592 593 return (AAC_GETREG4(sc, AAC_SA_FWSTATUS)); 594 } 595 596 static int 597 aac_rx_get_fwstatus(struct aac_softc *sc) 598 { 599 600 return (AAC_GETREG4(sc, AAC_RX_FWSTATUS)); 601 } 602 603 static int 604 aac_rkt_get_fwstatus(struct aac_softc *sc) 605 { 606 607 return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS)); 608 } 609 610 /* 611 * Notify the controller of a change in a given queue 612 */ 613 614 static void 615 aac_sa_qnotify(struct aac_softc *sc, int qbit) 616 { 617 618 AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit); 619 } 620 621 static void 622 aac_rx_qnotify(struct aac_softc *sc, int qbit) 623 { 624 625 AAC_SETREG4(sc, AAC_RX_IDBR, qbit); 626 } 627 628 static void 629 aac_rkt_qnotify(struct aac_softc *sc, int qbit) 630 { 631 632 AAC_SETREG4(sc, AAC_RKT_IDBR, qbit); 633 } 634 635 /* 636 * Get the interrupt reason bits 637 */ 638 static int 639 aac_sa_get_istatus(struct aac_softc *sc) 640 { 641 642 return (AAC_GETREG2(sc, AAC_SA_DOORBELL0)); 643 } 644 645 static int 646 aac_rx_get_istatus(struct aac_softc *sc) 647 { 648 649 return (AAC_GETREG4(sc, AAC_RX_ODBR)); 650 } 651 652 static int 653 aac_rkt_get_istatus(struct aac_softc *sc) 654 { 655 656 return (AAC_GETREG4(sc, AAC_RKT_ODBR)); 657 } 658 659 /* 660 * Clear some interrupt reason bits 661 */ 662 static void 663 aac_sa_clear_istatus(struct aac_softc *sc, int mask) 664 { 665 666 AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask); 667 } 668 669 static void 670 aac_rx_clear_istatus(struct aac_softc *sc, int mask) 671 { 672 673 AAC_SETREG4(sc, AAC_RX_ODBR, mask); 674 } 675 676 static void 677 aac_rkt_clear_istatus(struct aac_softc *sc, int mask) 678 { 679 680 AAC_SETREG4(sc, AAC_RKT_ODBR, mask); 681 } 682 683 /* 684 * Populate the mailbox and set the command word 685 */ 686 static void 687 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command, 688 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 689 u_int32_t arg3) 690 { 691 692 AAC_SETREG4(sc, AAC_SA_MAILBOX, command); 693 AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0); 694 AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1); 695 AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2); 696 AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3); 697 } 698 699 static void 700 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command, 701 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 702 u_int32_t arg3) 703 { 704 705 AAC_SETREG4(sc, AAC_RX_MAILBOX, command); 706 AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0); 707 AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1); 708 AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2); 709 AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3); 710 } 711 712 static void 713 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command, 714 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 715 u_int32_t arg3) 716 { 717 718 AAC_SETREG4(sc, AAC_RKT_MAILBOX, command); 719 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0); 720 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1); 721 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2); 722 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3); 723 } 724 725 /* 726 * Fetch the specified mailbox 727 */ 728 static uint32_t 729 aac_sa_get_mailbox(struct aac_softc *sc, int mb) 730 { 731 732 return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4))); 733 } 734 735 static uint32_t 736 aac_rx_get_mailbox(struct aac_softc *sc, int mb) 737 { 738 739 return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4))); 740 } 741 742 static uint32_t 743 aac_rkt_get_mailbox(struct aac_softc *sc, int mb) 744 { 745 746 return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4))); 747 } 748 749 /* 750 * Set/clear interrupt masks 751 */ 752 static void 753 aac_sa_set_interrupts(struct aac_softc *sc, int enable) 754 { 755 756 if (enable) 757 AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS); 758 else 759 AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0); 760 } 761 762 static void 763 aac_rx_set_interrupts(struct aac_softc *sc, int enable) 764 { 765 766 if (enable) { 767 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 768 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM); 769 else 770 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS); 771 } else { 772 AAC_SETREG4(sc, AAC_RX_OIMR, ~0); 773 } 774 } 775 776 static void 777 aac_rkt_set_interrupts(struct aac_softc *sc, int enable) 778 { 779 780 if (enable) { 781 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 782 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM); 783 else 784 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS); 785 } else { 786 AAC_SETREG4(sc, AAC_RKT_OIMR, ~0); 787 } 788 } 789 790 /* 791 * New comm. interface: Send command functions 792 */ 793 static int 794 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac) 795 { 796 u_int32_t index, device; 797 798 index = AAC_GETREG4(sc, AAC_RX_IQUE); 799 if (index == 0xffffffffL) 800 index = AAC_GETREG4(sc, AAC_RX_IQUE); 801 if (index == 0xffffffffL) 802 return index; 803 #ifdef notyet 804 aac_enqueue_busy(ac); 805 #endif 806 device = index; 807 AAC_SETREG4(sc, device, 808 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 809 device += 4; 810 if (sizeof(bus_addr_t) > 4) { 811 AAC_SETREG4(sc, device, 812 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 813 } else { 814 AAC_SETREG4(sc, device, 0); 815 } 816 device += 4; 817 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 818 AAC_SETREG4(sc, AAC_RX_IQUE, index); 819 return 0; 820 } 821 822 static int 823 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac) 824 { 825 u_int32_t index, device; 826 827 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 828 if (index == 0xffffffffL) 829 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 830 if (index == 0xffffffffL) 831 return index; 832 #ifdef notyet 833 aac_enqueue_busy(ac); 834 #endif 835 device = index; 836 AAC_SETREG4(sc, device, 837 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 838 device += 4; 839 if (sizeof(bus_addr_t) > 4) { 840 AAC_SETREG4(sc, device, 841 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 842 } else { 843 AAC_SETREG4(sc, device, 0); 844 } 845 device += 4; 846 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 847 AAC_SETREG4(sc, AAC_RKT_IQUE, index); 848 return 0; 849 } 850 851 /* 852 * New comm. interface: get, set outbound queue index 853 */ 854 static int 855 aac_rx_get_outb_queue(struct aac_softc *sc) 856 { 857 858 return AAC_GETREG4(sc, AAC_RX_OQUE); 859 } 860 861 static int 862 aac_rkt_get_outb_queue(struct aac_softc *sc) 863 { 864 865 return AAC_GETREG4(sc, AAC_RKT_OQUE); 866 } 867 868 static void 869 aac_rx_set_outb_queue(struct aac_softc *sc, int index) 870 { 871 872 AAC_SETREG4(sc, AAC_RX_OQUE, index); 873 } 874 875 static void 876 aac_rkt_set_outb_queue(struct aac_softc *sc, int index) 877 { 878 879 AAC_SETREG4(sc, AAC_RKT_OQUE, index); 880 } 881