1 /* $NetBSD: aac_pci.c,v 1.33 2011/09/29 12:51:28 is Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * Copyright (c) 2000 Niklas Hallqvist 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp 60 * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp 61 */ 62 63 /* 64 * PCI front-end for the `aac' driver. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.33 2011/09/29 12:51:28 is Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 77 #include <sys/bus.h> 78 #include <machine/endian.h> 79 #include <sys/intr.h> 80 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 85 #include <dev/ic/aacreg.h> 86 #include <dev/ic/aacvar.h> 87 88 struct aac_pci_softc { 89 struct aac_softc sc_aac; 90 pci_chipset_tag_t sc_pc; 91 pci_intr_handle_t sc_ih; 92 }; 93 94 /* i960Rx interface */ 95 static int aac_rx_get_fwstatus(struct aac_softc *); 96 static void aac_rx_qnotify(struct aac_softc *, int); 97 static int aac_rx_get_istatus(struct aac_softc *); 98 static void aac_rx_clear_istatus(struct aac_softc *, int); 99 static void aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, u_int32_t); 101 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int); 102 static void aac_rx_set_interrupts(struct aac_softc *, int); 103 static int aac_rx_send_command(struct aac_softc *, struct aac_ccb *); 104 static int aac_rx_get_outb_queue(struct aac_softc *); 105 static void aac_rx_set_outb_queue(struct aac_softc *, int); 106 107 /* StrongARM interface */ 108 static int aac_sa_get_fwstatus(struct aac_softc *); 109 static void aac_sa_qnotify(struct aac_softc *, int); 110 static int aac_sa_get_istatus(struct aac_softc *); 111 static void aac_sa_clear_istatus(struct aac_softc *, int); 112 static void aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 113 u_int32_t, u_int32_t, u_int32_t); 114 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int); 115 static void aac_sa_set_interrupts(struct aac_softc *, int); 116 117 /* Rocket/MIPS interface */ 118 static int aac_rkt_get_fwstatus(struct aac_softc *); 119 static void aac_rkt_qnotify(struct aac_softc *, int); 120 static int aac_rkt_get_istatus(struct aac_softc *); 121 static void aac_rkt_clear_istatus(struct aac_softc *, int); 122 static void aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 123 u_int32_t, u_int32_t, u_int32_t); 124 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int); 125 static void aac_rkt_set_interrupts(struct aac_softc *, int); 126 static int aac_rkt_send_command(struct aac_softc *, struct aac_ccb *); 127 static int aac_rkt_get_outb_queue(struct aac_softc *); 128 static void aac_rkt_set_outb_queue(struct aac_softc *, int); 129 130 static const struct aac_interface aac_rx_interface = { 131 aac_rx_get_fwstatus, 132 aac_rx_qnotify, 133 aac_rx_get_istatus, 134 aac_rx_clear_istatus, 135 aac_rx_set_mailbox, 136 aac_rx_get_mailbox, 137 aac_rx_set_interrupts, 138 aac_rx_send_command, 139 aac_rx_get_outb_queue, 140 aac_rx_set_outb_queue 141 }; 142 143 static const struct aac_interface aac_sa_interface = { 144 aac_sa_get_fwstatus, 145 aac_sa_qnotify, 146 aac_sa_get_istatus, 147 aac_sa_clear_istatus, 148 aac_sa_set_mailbox, 149 aac_sa_get_mailbox, 150 aac_sa_set_interrupts, 151 NULL, NULL, NULL 152 }; 153 154 static const struct aac_interface aac_rkt_interface = { 155 aac_rkt_get_fwstatus, 156 aac_rkt_qnotify, 157 aac_rkt_get_istatus, 158 aac_rkt_clear_istatus, 159 aac_rkt_set_mailbox, 160 aac_rkt_get_mailbox, 161 aac_rkt_set_interrupts, 162 aac_rkt_send_command, 163 aac_rkt_get_outb_queue, 164 aac_rkt_set_outb_queue 165 }; 166 167 static struct aac_ident { 168 u_short vendor; 169 u_short device; 170 u_short subvendor; 171 u_short subdevice; 172 u_short hwif; 173 u_short quirks; 174 const char *prodstr; 175 } const aac_ident[] = { 176 { 177 PCI_VENDOR_DELL, 178 PCI_PRODUCT_DELL_PERC_2SI, 179 PCI_VENDOR_DELL, 180 PCI_PRODUCT_DELL_PERC_2SI, 181 AAC_HWIF_I960RX, 182 0, 183 "Dell PERC 2/Si" 184 }, 185 { 186 PCI_VENDOR_DELL, 187 PCI_PRODUCT_DELL_PERC_3DI, 188 PCI_VENDOR_DELL, 189 PCI_PRODUCT_DELL_PERC_3DI, 190 AAC_HWIF_I960RX, 191 0, 192 "Dell PERC 3/Di" 193 }, 194 { 195 PCI_VENDOR_DELL, 196 PCI_PRODUCT_DELL_PERC_3DI, 197 PCI_VENDOR_DELL, 198 PCI_PRODUCT_DELL_PERC_3DI_SUB2, 199 AAC_HWIF_I960RX, 200 0, 201 "Dell PERC 3/Di" 202 }, 203 { 204 PCI_VENDOR_DELL, 205 PCI_PRODUCT_DELL_PERC_3DI, 206 PCI_VENDOR_DELL, 207 PCI_PRODUCT_DELL_PERC_3DI_SUB3, 208 AAC_HWIF_I960RX, 209 0, 210 "Dell PERC 3/Di" 211 }, 212 { 213 PCI_VENDOR_DELL, 214 PCI_PRODUCT_DELL_PERC_3DI_2, 215 PCI_VENDOR_DELL, 216 PCI_PRODUCT_DELL_PERC_3DI_2_SUB, 217 AAC_HWIF_I960RX, 218 0, 219 "Dell PERC 3/Di" 220 }, 221 { 222 PCI_VENDOR_DELL, 223 PCI_PRODUCT_DELL_PERC_3DI_3, 224 PCI_VENDOR_DELL, 225 PCI_PRODUCT_DELL_PERC_3DI_3_SUB, 226 AAC_HWIF_I960RX, 227 0, 228 "Dell PERC 3/Di" 229 }, 230 { 231 PCI_VENDOR_DELL, 232 PCI_PRODUCT_DELL_PERC_3DI_3, 233 PCI_VENDOR_DELL, 234 PCI_PRODUCT_DELL_PERC_3DI_3_SUB2, 235 AAC_HWIF_I960RX, 236 0, 237 "Dell PERC 3/Di" 238 }, 239 { 240 PCI_VENDOR_DELL, 241 PCI_PRODUCT_DELL_PERC_3DI_3, 242 PCI_VENDOR_DELL, 243 PCI_PRODUCT_DELL_PERC_3DI_3_SUB3, 244 AAC_HWIF_I960RX, 245 0, 246 "Dell PERC 3/Di" 247 }, 248 { 249 PCI_VENDOR_DELL, 250 PCI_PRODUCT_DELL_PERC_3SI, 251 PCI_VENDOR_DELL, 252 PCI_PRODUCT_DELL_PERC_3SI, 253 AAC_HWIF_I960RX, 254 0, 255 "Dell PERC 3/Si" 256 }, 257 { 258 PCI_VENDOR_DELL, 259 PCI_PRODUCT_DELL_PERC_3SI_2, 260 PCI_VENDOR_DELL, 261 PCI_PRODUCT_DELL_PERC_3SI_2_SUB, 262 AAC_HWIF_I960RX, 263 0, 264 "Dell PERC 3/Si" 265 }, 266 { 267 PCI_VENDOR_ADP2, 268 PCI_PRODUCT_ADP2_ASR2200S, 269 PCI_VENDOR_DELL, 270 PCI_PRODUCT_DELL_CERC_1_5, 271 AAC_HWIF_I960RX, 272 AAC_QUIRK_NO4GB, 273 "Dell CERC SATA RAID 1.5/6ch" 274 }, 275 { 276 PCI_VENDOR_ADP2, 277 PCI_PRODUCT_ADP2_AAC2622, 278 PCI_VENDOR_ADP2, 279 PCI_PRODUCT_ADP2_AAC2622, 280 AAC_HWIF_I960RX, 281 0, 282 "Adaptec ADP-2622" 283 }, 284 { 285 PCI_VENDOR_ADP2, 286 PCI_PRODUCT_ADP2_ASR2200S, 287 PCI_VENDOR_ADP2, 288 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 289 AAC_HWIF_I960RX, 290 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 291 "Adaptec ASR-2200S" 292 }, 293 { 294 PCI_VENDOR_ADP2, 295 PCI_PRODUCT_ADP2_ASR2200S, 296 PCI_VENDOR_DELL, 297 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 298 AAC_HWIF_I960RX, 299 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 300 "Dell PERC 320/DC" 301 }, 302 { 303 PCI_VENDOR_ADP2, 304 PCI_PRODUCT_ADP2_ASR2200S, 305 PCI_VENDOR_ADP2, 306 PCI_PRODUCT_ADP2_ASR2200S, 307 AAC_HWIF_I960RX, 308 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 309 "Adaptec ASR-2200S" 310 }, 311 { 312 PCI_VENDOR_ADP2, 313 PCI_PRODUCT_ADP2_ASR2200S, 314 PCI_VENDOR_ADP2, 315 PCI_PRODUCT_ADP2_AAR2810SA, 316 AAC_HWIF_I960RX, 317 AAC_QUIRK_NO4GB, 318 "Adaptec AAR-2810SA" 319 }, 320 { 321 PCI_VENDOR_ADP2, 322 PCI_PRODUCT_ADP2_ASR2200S, 323 PCI_VENDOR_ADP2, 324 PCI_PRODUCT_ADP2_ASR2120S, 325 AAC_HWIF_I960RX, 326 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 327 "Adaptec ASR-2120S" 328 }, 329 { 330 PCI_VENDOR_ADP2, 331 PCI_PRODUCT_ADP2_ASR2200S, 332 PCI_VENDOR_ADP2, 333 PCI_PRODUCT_ADP2_ASR2410SA, 334 AAC_HWIF_I960RX, 335 AAC_QUIRK_NO4GB, 336 "Adaptec ASR-2410SA" 337 }, 338 { 339 PCI_VENDOR_ADP2, 340 PCI_PRODUCT_ADP2_ASR2200S, 341 PCI_VENDOR_HP, 342 PCI_PRODUCT_ADP2_HP_M110_G2, 343 AAC_HWIF_I960RX, 344 AAC_QUIRK_NO4GB, 345 "HP ML110 G2 (Adaptec ASR-2610SA)" 346 }, 347 { 348 PCI_VENDOR_ADP2, 349 PCI_PRODUCT_ADP2_ASR2120S, 350 PCI_VENDOR_IBM, 351 PCI_PRODUCT_IBM_SERVERAID8K, 352 AAC_HWIF_RKT, 353 0, 354 "IBM ServeRAID 8k" 355 }, 356 { PCI_VENDOR_ADP2, 357 PCI_PRODUCT_ADP2_ASR2200S, 358 PCI_VENDOR_ADP2, 359 PCI_PRODUCT_ADP2_3405, 360 AAC_HWIF_I960RX, 361 0, 362 "Adaptec RAID 3405" 363 }, 364 { 365 PCI_VENDOR_DEC, 366 PCI_PRODUCT_DEC_21554, 367 PCI_VENDOR_ADP2, 368 PCI_PRODUCT_ADP2_AAC364, 369 AAC_HWIF_STRONGARM, 370 0, 371 "Adaptec AAC-364" 372 }, 373 { 374 PCI_VENDOR_DEC, 375 PCI_PRODUCT_DEC_21554, 376 PCI_VENDOR_ADP2, 377 PCI_PRODUCT_ADP2_ASR5400S, 378 AAC_HWIF_STRONGARM, 379 AAC_QUIRK_BROKEN_MMAP, 380 "Adaptec ASR-5400S" 381 }, 382 { 383 PCI_VENDOR_DEC, 384 PCI_PRODUCT_DEC_21554, 385 PCI_VENDOR_ADP2, 386 PCI_PRODUCT_ADP2_PERC_2QC, 387 AAC_HWIF_STRONGARM, 388 AAC_QUIRK_PERC2QC, 389 "Dell PERC 2/QC" 390 }, 391 { 392 PCI_VENDOR_DEC, 393 PCI_PRODUCT_DEC_21554, 394 PCI_VENDOR_ADP2, 395 PCI_PRODUCT_ADP2_PERC_3QC, 396 AAC_HWIF_STRONGARM, 397 0, 398 "Dell PERC 3/QC" 399 }, 400 { 401 PCI_VENDOR_DEC, 402 PCI_PRODUCT_DEC_21554, 403 PCI_VENDOR_HP, 404 PCI_PRODUCT_HP_NETRAID_4M, 405 AAC_HWIF_STRONGARM, 406 0, 407 "HP NetRAID-4M" 408 }, 409 { 410 PCI_VENDOR_ADP2, 411 PCI_PRODUCT_ADP2_ASR2200S, 412 PCI_VENDOR_SUN, 413 PCI_PRODUCT_ADP2_ASR2120S, 414 AAC_HWIF_I960RX, 415 0, 416 "SG-XPCIESAS-R-IN" 417 }, 418 }; 419 420 static const struct aac_ident * 421 aac_find_ident(struct pci_attach_args *pa) 422 { 423 const struct aac_ident *m, *mm; 424 u_int32_t subsysid; 425 426 m = aac_ident; 427 mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0])); 428 429 while (m < mm) { 430 if (m->vendor == PCI_VENDOR(pa->pa_id) && 431 m->device == PCI_PRODUCT(pa->pa_id)) { 432 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, 433 PCI_SUBSYS_ID_REG); 434 if (m->subvendor == PCI_VENDOR(subsysid) && 435 m->subdevice == PCI_PRODUCT(subsysid)) 436 return (m); 437 } 438 m++; 439 } 440 441 return (NULL); 442 } 443 444 static int 445 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg) 446 { 447 struct aac_pci_softc *pcisc; 448 449 pcisc = (struct aac_pci_softc *) sc; 450 451 pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih); 452 sc->sc_ih = pci_intr_establish(pcisc->sc_pc, pcisc->sc_ih, 453 IPL_BIO, hand, arg); 454 if (sc->sc_ih == NULL) { 455 return ENXIO; 456 } 457 return 0; 458 } 459 460 static int 461 aac_pci_match(device_t parent, cfdata_t match, void *aux) 462 { 463 struct pci_attach_args *pa; 464 465 pa = aux; 466 467 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 468 return (0); 469 470 return (aac_find_ident(pa) != NULL); 471 } 472 473 static void 474 aac_pci_attach(device_t parent, device_t self, void *aux) 475 { 476 struct pci_attach_args *pa; 477 pci_chipset_tag_t pc; 478 struct aac_pci_softc *pcisc; 479 struct aac_softc *sc; 480 u_int16_t command; 481 bus_addr_t membase; 482 bus_size_t memsize; 483 const char *intrstr; 484 int state; 485 const struct aac_ident *m; 486 487 pa = aux; 488 pc = pa->pa_pc; 489 pcisc = device_private(self); 490 pcisc->sc_pc = pc; 491 sc = &pcisc->sc_aac; 492 state = 0; 493 494 aprint_naive(": RAID controller\n"); 495 aprint_normal(": "); 496 497 /* 498 * Verify that the adapter is correctly set up in PCI space. 499 */ 500 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 501 command |= PCI_COMMAND_MASTER_ENABLE; 502 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 503 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 504 AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x ")); 505 506 if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) { 507 aprint_error("can't enable bus-master feature\n"); 508 goto bail_out; 509 } 510 511 if ((command & PCI_COMMAND_MEM_ENABLE) == 0) { 512 aprint_error("memory window not available\n"); 513 goto bail_out; 514 } 515 516 /* 517 * Map control/status registers. 518 */ 519 if (pci_mapreg_map(pa, PCI_MAPREG_START, 520 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt, 521 &sc->sc_memh, &membase, &memsize)) { 522 aprint_error("can't find mem space\n"); 523 goto bail_out; 524 } 525 state++; 526 527 if (pci_intr_map(pa, &pcisc->sc_ih)) { 528 aprint_error("couldn't map interrupt\n"); 529 goto bail_out; 530 } 531 intrstr = pci_intr_string(pc, pcisc->sc_ih); 532 sc->sc_ih = pci_intr_establish(pc, pcisc->sc_ih, IPL_BIO, aac_intr, sc); 533 if (sc->sc_ih == NULL) { 534 aprint_error("couldn't establish interrupt"); 535 if (intrstr != NULL) 536 aprint_error(" at %s", intrstr); 537 aprint_error("\n"); 538 goto bail_out; 539 } 540 state++; 541 542 sc->sc_dmat = pa->pa_dmat; 543 544 m = aac_find_ident(pa); 545 aprint_normal("%s\n", m->prodstr); 546 if (intrstr != NULL) 547 aprint_normal_dev(&sc->sc_dv, "interrupting at %s\n", 548 intrstr); 549 550 sc->sc_hwif = m->hwif; 551 sc->sc_quirks = m->quirks; 552 switch (sc->sc_hwif) { 553 case AAC_HWIF_I960RX: 554 AAC_DPRINTF(AAC_D_MISC, 555 ("set hardware up for i960Rx")); 556 sc->sc_if = aac_rx_interface; 557 break; 558 559 case AAC_HWIF_STRONGARM: 560 AAC_DPRINTF(AAC_D_MISC, 561 ("set hardware up for StrongARM")); 562 sc->sc_if = aac_sa_interface; 563 break; 564 565 case AAC_HWIF_RKT: 566 AAC_DPRINTF(AAC_D_MISC, 567 ("set hardware up for MIPS/Rocket")); 568 sc->sc_if = aac_rkt_interface; 569 break; 570 } 571 sc->sc_regsize = memsize; 572 sc->sc_intr_set = aac_pci_intr_set; 573 574 if (!aac_attach(sc)) 575 return; 576 577 bail_out: 578 if (state > 1) 579 pci_intr_disestablish(pc, sc->sc_ih); 580 if (state > 0) 581 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 582 } 583 584 CFATTACH_DECL(aac_pci, sizeof(struct aac_pci_softc), 585 aac_pci_match, aac_pci_attach, NULL, NULL); 586 587 /* 588 * Read the current firmware status word. 589 */ 590 static int 591 aac_sa_get_fwstatus(struct aac_softc *sc) 592 { 593 594 return (AAC_GETREG4(sc, AAC_SA_FWSTATUS)); 595 } 596 597 static int 598 aac_rx_get_fwstatus(struct aac_softc *sc) 599 { 600 601 return (AAC_GETREG4(sc, AAC_RX_FWSTATUS)); 602 } 603 604 static int 605 aac_rkt_get_fwstatus(struct aac_softc *sc) 606 { 607 608 return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS)); 609 } 610 611 /* 612 * Notify the controller of a change in a given queue 613 */ 614 615 static void 616 aac_sa_qnotify(struct aac_softc *sc, int qbit) 617 { 618 619 AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit); 620 } 621 622 static void 623 aac_rx_qnotify(struct aac_softc *sc, int qbit) 624 { 625 626 AAC_SETREG4(sc, AAC_RX_IDBR, qbit); 627 } 628 629 static void 630 aac_rkt_qnotify(struct aac_softc *sc, int qbit) 631 { 632 633 AAC_SETREG4(sc, AAC_RKT_IDBR, qbit); 634 } 635 636 /* 637 * Get the interrupt reason bits 638 */ 639 static int 640 aac_sa_get_istatus(struct aac_softc *sc) 641 { 642 643 return (AAC_GETREG2(sc, AAC_SA_DOORBELL0)); 644 } 645 646 static int 647 aac_rx_get_istatus(struct aac_softc *sc) 648 { 649 650 return (AAC_GETREG4(sc, AAC_RX_ODBR)); 651 } 652 653 static int 654 aac_rkt_get_istatus(struct aac_softc *sc) 655 { 656 657 return (AAC_GETREG4(sc, AAC_RKT_ODBR)); 658 } 659 660 /* 661 * Clear some interrupt reason bits 662 */ 663 static void 664 aac_sa_clear_istatus(struct aac_softc *sc, int mask) 665 { 666 667 AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask); 668 } 669 670 static void 671 aac_rx_clear_istatus(struct aac_softc *sc, int mask) 672 { 673 674 AAC_SETREG4(sc, AAC_RX_ODBR, mask); 675 } 676 677 static void 678 aac_rkt_clear_istatus(struct aac_softc *sc, int mask) 679 { 680 681 AAC_SETREG4(sc, AAC_RKT_ODBR, mask); 682 } 683 684 /* 685 * Populate the mailbox and set the command word 686 */ 687 static void 688 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command, 689 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 690 u_int32_t arg3) 691 { 692 693 AAC_SETREG4(sc, AAC_SA_MAILBOX, command); 694 AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0); 695 AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1); 696 AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2); 697 AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3); 698 } 699 700 static void 701 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command, 702 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 703 u_int32_t arg3) 704 { 705 706 AAC_SETREG4(sc, AAC_RX_MAILBOX, command); 707 AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0); 708 AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1); 709 AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2); 710 AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3); 711 } 712 713 static void 714 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command, 715 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 716 u_int32_t arg3) 717 { 718 719 AAC_SETREG4(sc, AAC_RKT_MAILBOX, command); 720 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0); 721 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1); 722 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2); 723 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3); 724 } 725 726 /* 727 * Fetch the specified mailbox 728 */ 729 static uint32_t 730 aac_sa_get_mailbox(struct aac_softc *sc, int mb) 731 { 732 733 return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4))); 734 } 735 736 static uint32_t 737 aac_rx_get_mailbox(struct aac_softc *sc, int mb) 738 { 739 740 return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4))); 741 } 742 743 static uint32_t 744 aac_rkt_get_mailbox(struct aac_softc *sc, int mb) 745 { 746 747 return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4))); 748 } 749 750 /* 751 * Set/clear interrupt masks 752 */ 753 static void 754 aac_sa_set_interrupts(struct aac_softc *sc, int enable) 755 { 756 757 if (enable) 758 AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS); 759 else 760 AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0); 761 } 762 763 static void 764 aac_rx_set_interrupts(struct aac_softc *sc, int enable) 765 { 766 767 if (enable) { 768 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 769 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM); 770 else 771 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS); 772 } else { 773 AAC_SETREG4(sc, AAC_RX_OIMR, ~0); 774 } 775 } 776 777 static void 778 aac_rkt_set_interrupts(struct aac_softc *sc, int enable) 779 { 780 781 if (enable) { 782 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 783 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM); 784 else 785 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS); 786 } else { 787 AAC_SETREG4(sc, AAC_RKT_OIMR, ~0); 788 } 789 } 790 791 /* 792 * New comm. interface: Send command functions 793 */ 794 static int 795 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac) 796 { 797 u_int32_t index, device; 798 799 index = AAC_GETREG4(sc, AAC_RX_IQUE); 800 if (index == 0xffffffffL) 801 index = AAC_GETREG4(sc, AAC_RX_IQUE); 802 if (index == 0xffffffffL) 803 return index; 804 #ifdef notyet 805 aac_enqueue_busy(ac); 806 #endif 807 device = index; 808 AAC_SETREG4(sc, device, 809 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 810 device += 4; 811 if (sizeof(bus_addr_t) > 4) { 812 AAC_SETREG4(sc, device, 813 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 814 } else { 815 AAC_SETREG4(sc, device, 0); 816 } 817 device += 4; 818 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 819 AAC_SETREG4(sc, AAC_RX_IQUE, index); 820 return 0; 821 } 822 823 static int 824 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac) 825 { 826 u_int32_t index, device; 827 828 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 829 if (index == 0xffffffffL) 830 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 831 if (index == 0xffffffffL) 832 return index; 833 #ifdef notyet 834 aac_enqueue_busy(ac); 835 #endif 836 device = index; 837 AAC_SETREG4(sc, device, 838 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 839 device += 4; 840 if (sizeof(bus_addr_t) > 4) { 841 AAC_SETREG4(sc, device, 842 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 843 } else { 844 AAC_SETREG4(sc, device, 0); 845 } 846 device += 4; 847 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 848 AAC_SETREG4(sc, AAC_RKT_IQUE, index); 849 return 0; 850 } 851 852 /* 853 * New comm. interface: get, set outbound queue index 854 */ 855 static int 856 aac_rx_get_outb_queue(struct aac_softc *sc) 857 { 858 859 return AAC_GETREG4(sc, AAC_RX_OQUE); 860 } 861 862 static int 863 aac_rkt_get_outb_queue(struct aac_softc *sc) 864 { 865 866 return AAC_GETREG4(sc, AAC_RKT_OQUE); 867 } 868 869 static void 870 aac_rx_set_outb_queue(struct aac_softc *sc, int index) 871 { 872 873 AAC_SETREG4(sc, AAC_RX_OQUE, index); 874 } 875 876 static void 877 aac_rkt_set_outb_queue(struct aac_softc *sc, int index) 878 { 879 880 AAC_SETREG4(sc, AAC_RKT_OQUE, index); 881 } 882