xref: /netbsd-src/sys/dev/nand/nand_toshiba.c (revision 57ab95bfce4c6b5143149df13ee2ff751eb4961c)
1*57ab95bfSjmcneill /*	$NetBSD: nand_toshiba.c,v 1.1 2017/11/09 21:50:15 jmcneill Exp $	*/
2*57ab95bfSjmcneill 
3*57ab95bfSjmcneill /*-
4*57ab95bfSjmcneill  * Copyright (c) 2012-2017 The NetBSD Foundation, Inc.
5*57ab95bfSjmcneill  * All rights reserved.
6*57ab95bfSjmcneill  *
7*57ab95bfSjmcneill  * This code is derived from software contributed to The NetBSD Foundation
8*57ab95bfSjmcneill  * by Adam Hoka.
9*57ab95bfSjmcneill  *
10*57ab95bfSjmcneill  * Redistribution and use in source and binary forms, with or without
11*57ab95bfSjmcneill  * modification, are permitted provided that the following conditions
12*57ab95bfSjmcneill  * are met:
13*57ab95bfSjmcneill  * 1. Redistributions of source code must retain the above copyright
14*57ab95bfSjmcneill  *    notice, this list of conditions and the following disclaimer.
15*57ab95bfSjmcneill  * 2. Redistributions in binary form must reproduce the above copyright
16*57ab95bfSjmcneill  *    notice, this list of conditions and the following disclaimer in the
17*57ab95bfSjmcneill  *    documentation and/or other materials provided with the distribution.
18*57ab95bfSjmcneill  *
19*57ab95bfSjmcneill  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20*57ab95bfSjmcneill  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21*57ab95bfSjmcneill  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22*57ab95bfSjmcneill  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23*57ab95bfSjmcneill  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*57ab95bfSjmcneill  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*57ab95bfSjmcneill  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*57ab95bfSjmcneill  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*57ab95bfSjmcneill  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*57ab95bfSjmcneill  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*57ab95bfSjmcneill  * POSSIBILITY OF SUCH DAMAGE.
30*57ab95bfSjmcneill  */
31*57ab95bfSjmcneill 
32*57ab95bfSjmcneill /*
33*57ab95bfSjmcneill  * Device specific functions for legacy Toshiba NAND chips
34*57ab95bfSjmcneill  */
35*57ab95bfSjmcneill 
36*57ab95bfSjmcneill #include <sys/cdefs.h>
37*57ab95bfSjmcneill __KERNEL_RCSID(0, "$NetBSD: nand_toshiba.c,v 1.1 2017/11/09 21:50:15 jmcneill Exp $");
38*57ab95bfSjmcneill 
39*57ab95bfSjmcneill #include "nand.h"
40*57ab95bfSjmcneill #include "onfi.h"
41*57ab95bfSjmcneill 
42*57ab95bfSjmcneill enum {
43*57ab95bfSjmcneill 	NAND_TOSHIBA_PAGEMASK = 0x3,
44*57ab95bfSjmcneill 	NAND_TOSHIBA_OOBMASK = 0x1 << 2,
45*57ab95bfSjmcneill 	NAND_TOSHIBA_BLOCKMASK = 0x3 << 4,
46*57ab95bfSjmcneill 	NAND_TOSHIBA_BITSMASK = 0x1 << 6
47*57ab95bfSjmcneill };
48*57ab95bfSjmcneill 
49*57ab95bfSjmcneill enum {
50*57ab95bfSjmcneill 	NAND_TOSHIBA_PLANENUMMASK = 0x3 << 2
51*57ab95bfSjmcneill };
52*57ab95bfSjmcneill 
53*57ab95bfSjmcneill int
nand_read_parameters_toshiba(device_t self,struct nand_chip * const chip)54*57ab95bfSjmcneill nand_read_parameters_toshiba(device_t self, struct nand_chip * const chip)
55*57ab95bfSjmcneill {
56*57ab95bfSjmcneill 	uint8_t mfgrid;
57*57ab95bfSjmcneill 	uint8_t devid;
58*57ab95bfSjmcneill 	uint8_t params1;
59*57ab95bfSjmcneill 	uint8_t params2;
60*57ab95bfSjmcneill 	uint8_t params3;
61*57ab95bfSjmcneill 
62*57ab95bfSjmcneill 	nand_select(self, true);
63*57ab95bfSjmcneill 	nand_command(self, ONFI_READ_ID);
64*57ab95bfSjmcneill 	nand_address(self, 0x00);
65*57ab95bfSjmcneill 	nand_read_1(self, &mfgrid);
66*57ab95bfSjmcneill 	nand_read_1(self, &devid);
67*57ab95bfSjmcneill 	nand_read_1(self, &params1);
68*57ab95bfSjmcneill 	nand_read_1(self, &params2);
69*57ab95bfSjmcneill 	nand_read_1(self, &params3);
70*57ab95bfSjmcneill 	nand_select(self, false);
71*57ab95bfSjmcneill 
72*57ab95bfSjmcneill 	aprint_debug_dev(self,
73*57ab95bfSjmcneill 	    "ID Definition table: 0x%2.x 0x%2.x 0x%2.x 0x%2.x 0x%2.x\n",
74*57ab95bfSjmcneill 	    mfgrid, devid, params1, params2, params3);
75*57ab95bfSjmcneill 
76*57ab95bfSjmcneill 	if (devid == 0xdc) {
77*57ab95bfSjmcneill 		/* From the documentation */
78*57ab95bfSjmcneill 		chip->nc_addr_cycles_column = 2;
79*57ab95bfSjmcneill 		chip->nc_addr_cycles_row = 3;
80*57ab95bfSjmcneill 		chip->nc_lun_blocks = 2048;
81*57ab95bfSjmcneill 
82*57ab95bfSjmcneill 		switch (params2 & NAND_TOSHIBA_PAGEMASK) {
83*57ab95bfSjmcneill 		case 0x0:
84*57ab95bfSjmcneill 			chip->nc_page_size = 1024;
85*57ab95bfSjmcneill 			break;
86*57ab95bfSjmcneill 		case 0x1:
87*57ab95bfSjmcneill 			chip->nc_page_size = 2048;
88*57ab95bfSjmcneill 			break;
89*57ab95bfSjmcneill 		case 0x2:
90*57ab95bfSjmcneill 			chip->nc_page_size = 4096;
91*57ab95bfSjmcneill 			break;
92*57ab95bfSjmcneill 		case 0x3:
93*57ab95bfSjmcneill 			chip->nc_page_size = 8192;
94*57ab95bfSjmcneill 			break;
95*57ab95bfSjmcneill 		default:
96*57ab95bfSjmcneill 			KASSERTMSG(false, "ID Data parsing bug detected!");
97*57ab95bfSjmcneill 		}
98*57ab95bfSjmcneill 
99*57ab95bfSjmcneill 		chip->nc_spare_size =
100*57ab95bfSjmcneill 		    (8 << __SHIFTOUT(params2, NAND_TOSHIBA_OOBMASK)) *
101*57ab95bfSjmcneill 		    (chip->nc_page_size >> 9);
102*57ab95bfSjmcneill 
103*57ab95bfSjmcneill 		switch ((params2 & NAND_TOSHIBA_BLOCKMASK) >> 4) {
104*57ab95bfSjmcneill 		case 0x0:
105*57ab95bfSjmcneill 			chip->nc_block_size = 64 * 1024;
106*57ab95bfSjmcneill 			break;
107*57ab95bfSjmcneill 		case 0x1:
108*57ab95bfSjmcneill 			chip->nc_block_size = 128 * 1024;
109*57ab95bfSjmcneill 			break;
110*57ab95bfSjmcneill 		case 0x2:
111*57ab95bfSjmcneill 			chip->nc_block_size = 256 * 1024;
112*57ab95bfSjmcneill 			break;
113*57ab95bfSjmcneill 		case 0x3:
114*57ab95bfSjmcneill 			chip->nc_block_size = 512 * 1024;
115*57ab95bfSjmcneill 			break;
116*57ab95bfSjmcneill 		default:
117*57ab95bfSjmcneill 			KASSERTMSG(false, "ID Data parsing bug detected!");
118*57ab95bfSjmcneill 		}
119*57ab95bfSjmcneill 
120*57ab95bfSjmcneill 		switch ((params2 & NAND_TOSHIBA_BITSMASK) >> 6) {
121*57ab95bfSjmcneill 		case 0x0:
122*57ab95bfSjmcneill 			/* its an 8bit chip */
123*57ab95bfSjmcneill 			break;
124*57ab95bfSjmcneill 		case 0x1:
125*57ab95bfSjmcneill 			chip->nc_flags |= NC_BUSWIDTH_16;
126*57ab95bfSjmcneill 			break;
127*57ab95bfSjmcneill 		default:
128*57ab95bfSjmcneill 			KASSERTMSG(false, "ID Data parsing bug detected!");
129*57ab95bfSjmcneill 		}
130*57ab95bfSjmcneill 
131*57ab95bfSjmcneill 		switch ((params3 & NAND_TOSHIBA_PLANENUMMASK) >> 2) {
132*57ab95bfSjmcneill 		case 0x0:
133*57ab95bfSjmcneill 			chip->nc_num_luns = 1;
134*57ab95bfSjmcneill 			break;
135*57ab95bfSjmcneill 		case 0x1:
136*57ab95bfSjmcneill 			chip->nc_num_luns = 2;
137*57ab95bfSjmcneill 			break;
138*57ab95bfSjmcneill 		case 0x2:
139*57ab95bfSjmcneill 			chip->nc_num_luns = 4;
140*57ab95bfSjmcneill 			break;
141*57ab95bfSjmcneill 		case 0x3:
142*57ab95bfSjmcneill 			chip->nc_num_luns = 8;
143*57ab95bfSjmcneill 			break;
144*57ab95bfSjmcneill 		default:
145*57ab95bfSjmcneill 			KASSERTMSG(false, "ID Data parsing bug detected!");
146*57ab95bfSjmcneill 		}
147*57ab95bfSjmcneill 
148*57ab95bfSjmcneill 		chip->nc_size = (uint64_t)chip->nc_lun_blocks *
149*57ab95bfSjmcneill 		    chip->nc_block_size;
150*57ab95bfSjmcneill 	} else {
151*57ab95bfSjmcneill 		return 1;
152*57ab95bfSjmcneill 	}
153*57ab95bfSjmcneill 
154*57ab95bfSjmcneill 	return 0;
155*57ab95bfSjmcneill }
156