1 /* $NetBSD: nand.c,v 1.15 2011/07/15 19:19:57 cliff Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Department of Software Engineering, 5 * University of Szeged, Hungary 6 * Copyright (c) 2010 Adam Hoka <ahoka@NetBSD.org> 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by the Department of Software Engineering, University of Szeged, Hungary 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Common driver for NAND chips implementing the ONFI 2.2 specification */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: nand.c,v 1.15 2011/07/15 19:19:57 cliff Exp $"); 38 39 #include "locators.h" 40 41 #include <sys/param.h> 42 #include <sys/types.h> 43 #include <sys/device.h> 44 #include <sys/kmem.h> 45 #include <sys/atomic.h> 46 47 #include <dev/flash/flash.h> 48 #include <dev/flash/flash_io.h> 49 #include <dev/nand/nand.h> 50 #include <dev/nand/onfi.h> 51 #include <dev/nand/hamming.h> 52 #include <dev/nand/nand_bbt.h> 53 #include <dev/nand/nand_crc.h> 54 55 #include "opt_nand.h" 56 57 int nand_match(device_t, cfdata_t, void *); 58 void nand_attach(device_t, device_t, void *); 59 int nand_detach(device_t, int); 60 bool nand_shutdown(device_t, int); 61 62 int nand_print(void *, const char *); 63 64 static int nand_search(device_t, cfdata_t, const int *, void *); 65 static void nand_address_row(device_t, size_t); 66 static void nand_address_column(device_t, size_t, size_t); 67 static int nand_fill_chip_structure(device_t, struct nand_chip *); 68 static int nand_scan_media(device_t, struct nand_chip *); 69 static bool nand_check_wp(device_t); 70 71 CFATTACH_DECL_NEW(nand, sizeof(struct nand_softc), 72 nand_match, nand_attach, nand_detach, NULL); 73 74 #ifdef NAND_DEBUG 75 int nanddebug = NAND_DEBUG; 76 #endif 77 78 struct flash_interface nand_flash_if = { 79 .type = FLASH_TYPE_NAND, 80 81 .read = nand_flash_read, 82 .write = nand_flash_write, 83 .erase = nand_flash_erase, 84 .block_isbad = nand_flash_isbad, 85 .block_markbad = nand_flash_markbad, 86 87 .submit = nand_flash_submit 88 }; 89 90 #ifdef NAND_VERBOSE 91 const struct nand_manufacturer nand_mfrs[] = { 92 { NAND_MFR_AMD, "AMD" }, 93 { NAND_MFR_FUJITSU, "Fujitsu" }, 94 { NAND_MFR_RENESAS, "Renesas" }, 95 { NAND_MFR_STMICRO, "ST Micro" }, 96 { NAND_MFR_MICRON, "Micron" }, 97 { NAND_MFR_NATIONAL, "National" }, 98 { NAND_MFR_TOSHIBA, "Toshiba" }, 99 { NAND_MFR_HYNIX, "Hynix" }, 100 { NAND_MFR_SAMSUNG, "Samsung" }, 101 { NAND_MFR_UNKNOWN, "Unknown" } 102 }; 103 104 static const char * 105 nand_midtoname(int id) 106 { 107 int i; 108 109 for (i = 0; nand_mfrs[i].id != 0; i++) { 110 if (nand_mfrs[i].id == id) 111 return nand_mfrs[i].name; 112 } 113 114 KASSERT(nand_mfrs[i].id == 0); 115 116 return nand_mfrs[i].name; 117 } 118 #endif 119 120 /* ARGSUSED */ 121 int 122 nand_match(device_t parent, cfdata_t match, void *aux) 123 { 124 /* pseudo device, always attaches */ 125 return 1; 126 } 127 128 void 129 nand_attach(device_t parent, device_t self, void *aux) 130 { 131 struct nand_softc *sc = device_private(self); 132 struct nand_attach_args *naa = aux; 133 struct nand_chip *chip = &sc->sc_chip; 134 135 sc->sc_dev = self; 136 sc->controller_dev = parent; 137 sc->nand_if = naa->naa_nand_if; 138 139 aprint_naive("\n"); 140 141 if (nand_check_wp(self)) { 142 aprint_error("NAND chip is write protected!\n"); 143 return; 144 } 145 146 if (nand_scan_media(self, chip)) { 147 return; 148 } 149 150 nand_flash_if.erasesize = chip->nc_block_size; 151 nand_flash_if.page_size = chip->nc_page_size; 152 nand_flash_if.writesize = chip->nc_page_size; 153 154 /* allocate cache */ 155 chip->nc_oob_cache = kmem_alloc(chip->nc_spare_size, KM_SLEEP); 156 chip->nc_page_cache = kmem_alloc(chip->nc_page_size, KM_SLEEP); 157 158 mutex_init(&sc->sc_device_lock, MUTEX_DEFAULT, IPL_NONE); 159 160 if (flash_sync_thread_init(&sc->sc_flash_io, self, &nand_flash_if)) { 161 goto error; 162 } 163 164 if (!pmf_device_register1(sc->sc_dev, NULL, NULL, nand_shutdown)) 165 aprint_error_dev(sc->sc_dev, 166 "couldn't establish power handler\n"); 167 168 #ifdef NAND_BBT 169 nand_bbt_init(self); 170 nand_bbt_scan(self); 171 #endif 172 173 /* 174 * Attach all our devices 175 */ 176 config_search_ia(nand_search, self, NULL, NULL); 177 178 return; 179 error: 180 kmem_free(chip->nc_oob_cache, chip->nc_spare_size); 181 kmem_free(chip->nc_page_cache, chip->nc_page_size); 182 mutex_destroy(&sc->sc_device_lock); 183 } 184 185 static int 186 nand_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 187 { 188 struct nand_softc *sc = device_private(parent); 189 struct nand_chip *chip = &sc->sc_chip; 190 struct flash_attach_args faa; 191 192 faa.flash_if = &nand_flash_if; 193 194 faa.partinfo.part_offset = cf->cf_loc[FLASHBUSCF_OFFSET]; 195 196 if (cf->cf_loc[FLASHBUSCF_SIZE] == 0) { 197 faa.partinfo.part_size = chip->nc_size - 198 faa.partinfo.part_offset; 199 } else { 200 faa.partinfo.part_size = cf->cf_loc[FLASHBUSCF_SIZE]; 201 } 202 203 if (cf->cf_loc[FLASHBUSCF_READONLY]) 204 faa.partinfo.part_flags = FLASH_PART_READONLY; 205 else 206 faa.partinfo.part_flags = 0; 207 208 if (config_match(parent, cf, &faa)) { 209 if (config_attach(parent, cf, &faa, nand_print) != NULL) { 210 return 0; 211 } else { 212 return 1; 213 } 214 } 215 216 return 1; 217 } 218 219 int 220 nand_detach(device_t self, int flags) 221 { 222 struct nand_softc *sc = device_private(self); 223 struct nand_chip *chip = &sc->sc_chip; 224 int error = 0; 225 226 error = config_detach_children(self, flags); 227 if (error) { 228 return error; 229 } 230 231 flash_sync_thread_destroy(&sc->sc_flash_io); 232 #ifdef NAND_BBT 233 nand_bbt_detach(self); 234 #endif 235 /* free oob cache */ 236 kmem_free(chip->nc_oob_cache, chip->nc_spare_size); 237 kmem_free(chip->nc_page_cache, chip->nc_page_size); 238 kmem_free(chip->nc_ecc_cache, chip->nc_ecc->necc_size); 239 240 mutex_destroy(&sc->sc_device_lock); 241 242 pmf_device_deregister(sc->sc_dev); 243 244 return error; 245 } 246 247 int 248 nand_print(void *aux, const char *pnp) 249 { 250 if (pnp != NULL) 251 aprint_normal("nand at %s\n", pnp); 252 253 return UNCONF; 254 } 255 256 /* ask for a nand driver to attach to the controller */ 257 device_t 258 nand_attach_mi(struct nand_interface *nand_if, device_t parent) 259 { 260 struct nand_attach_args arg; 261 262 KASSERT(nand_if != NULL); 263 264 /* fill the defaults if we have null pointers */ 265 if (nand_if->program_page == NULL) { 266 nand_if->program_page = &nand_default_program_page; 267 } 268 269 if (nand_if->read_page == NULL) { 270 nand_if->read_page = &nand_default_read_page; 271 } 272 273 arg.naa_nand_if = nand_if; 274 return config_found_ia(parent, "nandbus", &arg, nand_print); 275 } 276 277 /* default everything to reasonable values, to ease future api changes */ 278 void 279 nand_init_interface(struct nand_interface *interface) 280 { 281 interface->select = &nand_default_select; 282 interface->command = NULL; 283 interface->address = NULL; 284 interface->read_buf_1 = NULL; 285 interface->read_buf_2 = NULL; 286 interface->read_1 = NULL; 287 interface->read_2 = NULL; 288 interface->write_buf_1 = NULL; 289 interface->write_buf_2 = NULL; 290 interface->write_1 = NULL; 291 interface->write_2 = NULL; 292 interface->busy = NULL; 293 294 /*- 295 * most drivers dont want to change this, but some implement 296 * read/program in one step 297 */ 298 interface->program_page = &nand_default_program_page; 299 interface->read_page = &nand_default_read_page; 300 301 /* default to soft ecc, that should work everywhere */ 302 interface->ecc_compute = &nand_default_ecc_compute; 303 interface->ecc_correct = &nand_default_ecc_correct; 304 interface->ecc_prepare = NULL; 305 interface->ecc.necc_code_size = 3; 306 interface->ecc.necc_block_size = 256; 307 interface->ecc.necc_type = NAND_ECC_TYPE_SW; 308 } 309 310 #if 0 311 /* handle quirks here */ 312 static void 313 nand_quirks(device_t self, struct nand_chip *chip) 314 { 315 /* this is an example only! */ 316 switch (chip->nc_manf_id) { 317 case NAND_MFR_SAMSUNG: 318 if (chip->nc_dev_id == 0x00) { 319 /* do something only samsung chips need */ 320 /* or */ 321 /* chip->nc_quirks |= NC_QUIRK_NO_READ_START */ 322 } 323 } 324 325 return; 326 } 327 #endif 328 329 static int 330 nand_fill_chip_structure_legacy(device_t self, struct nand_chip *chip) 331 { 332 switch (chip->nc_manf_id) { 333 case NAND_MFR_MICRON: 334 return nand_read_parameters_micron(self, chip); 335 default: 336 return 1; 337 } 338 339 return 0; 340 } 341 342 /** 343 * scan media to determine the chip's properties 344 * this function resets the device 345 */ 346 static int 347 nand_scan_media(device_t self, struct nand_chip *chip) 348 { 349 struct nand_softc *sc = device_private(self); 350 struct nand_ecc *ecc; 351 uint8_t onfi_signature[4]; 352 353 nand_select(self, true); 354 nand_command(self, ONFI_RESET); 355 nand_select(self, false); 356 357 /* check if the device implements the ONFI standard */ 358 nand_select(self, true); 359 nand_command(self, ONFI_READ_ID); 360 nand_address(self, 0x20); 361 nand_read_1(self, &onfi_signature[0]); 362 nand_read_1(self, &onfi_signature[1]); 363 nand_read_1(self, &onfi_signature[2]); 364 nand_read_1(self, &onfi_signature[3]); 365 nand_select(self, false); 366 367 if (onfi_signature[0] != 'O' || onfi_signature[1] != 'N' || 368 onfi_signature[2] != 'F' || onfi_signature[3] != 'I') { 369 chip->nc_isonfi = false; 370 371 aprint_normal(": Legacy NAND Flash\n"); 372 373 nand_read_id(self, &chip->nc_manf_id, &chip->nc_dev_id); 374 375 if (nand_fill_chip_structure_legacy(self, chip)) { 376 aprint_error_dev(self, 377 "can't read device parameters for legacy chip\n"); 378 return 1; 379 } 380 } else { 381 chip->nc_isonfi = true; 382 383 aprint_normal(": ONFI NAND Flash\n"); 384 385 nand_read_id(self, &chip->nc_manf_id, &chip->nc_dev_id); 386 387 if (nand_fill_chip_structure(self, chip)) { 388 aprint_error_dev(self, 389 "can't read device parameters\n"); 390 return 1; 391 } 392 } 393 394 #ifdef NAND_VERBOSE 395 aprint_normal_dev(self, 396 "manufacturer id: 0x%.2x (%s), device id: 0x%.2x\n", 397 chip->nc_manf_id, 398 nand_midtoname(chip->nc_manf_id), 399 chip->nc_dev_id); 400 #endif 401 402 aprint_normal_dev(self, 403 "page size: %zu bytes, spare size: %zu bytes, " 404 "block size: %zu bytes\n", 405 chip->nc_page_size, chip->nc_spare_size, chip->nc_block_size); 406 407 aprint_normal_dev(self, 408 "LUN size: %" PRIu32 " blocks, LUNs: %" PRIu8 409 ", total storage size: %zu MB\n", 410 chip->nc_lun_blocks, chip->nc_num_luns, 411 chip->nc_size / 1024 / 1024); 412 413 #ifdef NAND_VERBOSE 414 aprint_normal_dev(self, "column cycles: %" PRIu8 ", row cycles: %" 415 PRIu8 "\n", 416 chip->nc_addr_cycles_column, chip->nc_addr_cycles_row); 417 #endif 418 419 ecc = chip->nc_ecc = &sc->nand_if->ecc; 420 421 /* 422 * calculate the place of ecc data in oob 423 * we try to be compatible with Linux here 424 */ 425 switch (chip->nc_spare_size) { 426 case 8: 427 ecc->necc_offset = 0; 428 break; 429 case 16: 430 ecc->necc_offset = 0; 431 break; 432 case 64: 433 ecc->necc_offset = 40; 434 break; 435 case 128: 436 ecc->necc_offset = 80; 437 break; 438 default: 439 panic("OOB size is unexpected"); 440 } 441 442 ecc->necc_steps = chip->nc_page_size / ecc->necc_block_size; 443 ecc->necc_size = ecc->necc_steps * ecc->necc_code_size; 444 445 /* check if we fit in oob */ 446 if (ecc->necc_offset + ecc->necc_size > chip->nc_spare_size) { 447 panic("NAND ECC bits dont fit in OOB"); 448 } 449 450 /* TODO: mark free oob area available for file systems */ 451 452 chip->nc_ecc_cache = kmem_zalloc(ecc->necc_size, KM_SLEEP); 453 454 /* 455 * calculate badblock marker offset in oob 456 * we try to be compatible with linux here 457 */ 458 if (chip->nc_page_size > 512) 459 chip->nc_badmarker_offs = 0; 460 else 461 chip->nc_badmarker_offs = 5; 462 463 /* Calculate page shift and mask */ 464 chip->nc_page_shift = ffs(chip->nc_page_size) - 1; 465 chip->nc_page_mask = ~(chip->nc_page_size - 1); 466 /* same for block */ 467 chip->nc_block_shift = ffs(chip->nc_block_size) - 1; 468 chip->nc_block_mask = ~(chip->nc_block_size - 1); 469 470 /* look for quirks here if needed in future */ 471 /* nand_quirks(self, chip); */ 472 473 return 0; 474 } 475 476 void 477 nand_read_id(device_t self, uint8_t *manf, uint8_t *dev) 478 { 479 nand_select(self, true); 480 nand_command(self, ONFI_READ_ID); 481 nand_address(self, 0x00); 482 483 nand_read_1(self, manf); 484 nand_read_1(self, dev); 485 486 nand_select(self, false); 487 } 488 489 int 490 nand_read_parameter_page(device_t self, struct onfi_parameter_page *params) 491 { 492 uint8_t *bufp; 493 uint16_t crc; 494 int i;//, tries = 0; 495 496 KASSERT(sizeof(*params) == 256); 497 498 //read_params: 499 // tries++; 500 501 nand_select(self, true); 502 nand_command(self, ONFI_READ_PARAMETER_PAGE); 503 nand_address(self, 0x00); 504 505 nand_busy(self); 506 507 /* TODO check the signature if it contains at least 2 letters */ 508 509 bufp = (uint8_t *)params; 510 /* XXX why i am not using read_buf? */ 511 for (i = 0; i < 256; i++) { 512 nand_read_1(self, &bufp[i]); 513 } 514 nand_select(self, false); 515 516 /* validate the parameter page with the crc */ 517 crc = nand_crc16(bufp, 254); 518 519 if (crc != params->param_integrity_crc) { 520 aprint_error_dev(self, "parameter page crc check failed\n"); 521 /* TODO: we should read the next parameter page copy */ 522 return 1; 523 } 524 525 return 0; 526 } 527 528 static int 529 nand_fill_chip_structure(device_t self, struct nand_chip *chip) 530 { 531 struct onfi_parameter_page params; 532 uint8_t vendor[13], model[21]; 533 int i; 534 535 if (nand_read_parameter_page(self, ¶ms)) { 536 return 1; 537 } 538 539 /* strip manufacturer and model string */ 540 strlcpy(vendor, params.param_manufacturer, sizeof(vendor)); 541 for (i = 11; i > 0 && vendor[i] == ' '; i--) 542 vendor[i] = 0; 543 strlcpy(model, params.param_model, sizeof(model)); 544 for (i = 19; i > 0 && model[i] == ' '; i--) 545 model[i] = 0; 546 547 aprint_normal_dev(self, "vendor: %s, model: %s\n", vendor, model); 548 549 /* XXX TODO multiple LUNs */ 550 if (params.param_numluns != 1) { 551 aprint_error_dev(self, 552 "more than one LUNs are not supported yet!\n"); 553 554 return 1; 555 } 556 557 chip->nc_size = params.param_pagesize * params.param_blocksize * 558 params.param_lunsize * params.param_numluns; 559 560 chip->nc_page_size = params.param_pagesize; 561 chip->nc_block_pages = params.param_blocksize; 562 chip->nc_block_size = params.param_blocksize * params.param_pagesize; 563 chip->nc_spare_size = params.param_sparesize; 564 chip->nc_lun_blocks = params.param_lunsize; 565 chip->nc_num_luns = params.param_numluns; 566 567 /* the lower 4 bits contain the row address cycles */ 568 chip->nc_addr_cycles_row = params.param_addr_cycles & 0x07; 569 /* the upper 4 bits contain the column address cycles */ 570 chip->nc_addr_cycles_column = (params.param_addr_cycles & ~0x07) >> 4; 571 572 if (params.param_features & ONFI_FEATURE_16BIT) 573 chip->nc_flags |= NC_BUSWIDTH_16; 574 575 if (params.param_features & ONFI_FEATURE_EXTENDED_PARAM) 576 chip->nc_flags |= NC_EXTENDED_PARAM; 577 578 return 0; 579 } 580 581 /* ARGSUSED */ 582 bool 583 nand_shutdown(device_t self, int howto) 584 { 585 return true; 586 } 587 588 static void 589 nand_address_column(device_t self, size_t row, size_t column) 590 { 591 struct nand_softc *sc = device_private(self); 592 struct nand_chip *chip = &sc->sc_chip; 593 uint8_t i; 594 595 DPRINTF(("addressing row: 0x%jx column: %zu\n", 596 (uintmax_t )row, column)); 597 598 /* XXX TODO */ 599 row >>= chip->nc_page_shift; 600 601 /* Write the column (subpage) address */ 602 if (chip->nc_flags & NC_BUSWIDTH_16) 603 column >>= 1; 604 for (i = 0; i < chip->nc_addr_cycles_column; i++, column >>= 8) 605 nand_address(self, column & 0xff); 606 607 /* Write the row (page) address */ 608 for (i = 0; i < chip->nc_addr_cycles_row; i++, row >>= 8) 609 nand_address(self, row & 0xff); 610 } 611 612 static void 613 nand_address_row(device_t self, size_t row) 614 { 615 struct nand_softc *sc = device_private(self); 616 struct nand_chip *chip = &sc->sc_chip; 617 int i; 618 619 /* XXX TODO */ 620 row >>= chip->nc_page_shift; 621 622 /* Write the row (page) address */ 623 for (i = 0; i < chip->nc_addr_cycles_row; i++, row >>= 8) 624 nand_address(self, row & 0xff); 625 } 626 627 static inline uint8_t 628 nand_get_status(device_t self) 629 { 630 uint8_t status; 631 632 nand_command(self, ONFI_READ_STATUS); 633 nand_busy(self); 634 nand_read_1(self, &status); 635 636 return status; 637 } 638 639 static bool 640 nand_check_wp(device_t self) 641 { 642 if (nand_get_status(self) & 0x80) 643 return false; 644 else 645 return true; 646 } 647 648 static void 649 nand_prepare_read(device_t self, flash_off_t row, flash_off_t column) 650 { 651 nand_command(self, ONFI_READ); 652 nand_address_column(self, row, column); 653 nand_command(self, ONFI_READ_START); 654 655 nand_busy(self); 656 } 657 658 /* read a page with ecc correction, default implementation */ 659 int 660 nand_default_read_page(device_t self, size_t offset, uint8_t *data) 661 { 662 struct nand_softc *sc = device_private(self); 663 struct nand_chip *chip = &sc->sc_chip; 664 size_t b, bs, e, cs; 665 uint8_t *ecc; 666 int result; 667 668 nand_prepare_read(self, offset, 0); 669 670 bs = chip->nc_ecc->necc_block_size; 671 cs = chip->nc_ecc->necc_code_size; 672 673 /* decide if we access by 8 or 16 bits */ 674 if (chip->nc_flags & NC_BUSWIDTH_16) { 675 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 676 nand_ecc_prepare(self, NAND_ECC_READ); 677 nand_read_buf_2(self, data + b, bs); 678 nand_ecc_compute(self, data + b, 679 chip->nc_ecc_cache + e); 680 } 681 } else { 682 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 683 nand_ecc_prepare(self, NAND_ECC_READ); 684 nand_read_buf_1(self, data + b, bs); 685 nand_ecc_compute(self, data + b, 686 chip->nc_ecc_cache + e); 687 } 688 } 689 690 /* for debugging new drivers */ 691 #if 0 692 nand_dump_data("page", data, chip->nc_page_size); 693 #endif 694 695 nand_read_oob(self, offset, chip->nc_oob_cache); 696 ecc = chip->nc_oob_cache + chip->nc_ecc->necc_offset; 697 698 /* useful for debugging new ecc drivers */ 699 #if 0 700 printf("dumping ecc %d\n--------------\n", chip->nc_ecc->necc_steps); 701 for (e = 0; e < chip->nc_ecc->necc_steps; e++) { 702 printf("0x"); 703 for (b = 0; b < cs; b++) { 704 printf("%.2hhx", ecc[e+b]); 705 } 706 printf(" 0x"); 707 for (b = 0; b < cs; b++) { 708 printf("%.2hhx", chip->nc_ecc_cache[e+b]); 709 } 710 printf("\n"); 711 } 712 printf("--------------\n"); 713 #endif 714 715 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 716 result = nand_ecc_correct(self, data + b, ecc + e, 717 chip->nc_ecc_cache + e); 718 719 switch (result) { 720 case NAND_ECC_OK: 721 break; 722 case NAND_ECC_CORRECTED: 723 aprint_error_dev(self, 724 "data corrected with ECC at page offset 0x%jx " 725 "block %zu\n", (uintmax_t)offset, b); 726 break; 727 case NAND_ECC_TWOBIT: 728 aprint_error_dev(self, 729 "uncorrectable ECC error at page offset 0x%jx " 730 "block %zu\n", (uintmax_t)offset, b); 731 return EIO; 732 break; 733 case NAND_ECC_INVALID: 734 aprint_error_dev(self, 735 "invalid ECC in oob at page offset 0x%jx " 736 "block %zu\n", (uintmax_t)offset, b); 737 return EIO; 738 break; 739 default: 740 panic("invalid ECC correction errno"); 741 } 742 } 743 744 return 0; 745 } 746 747 int 748 nand_default_program_page(device_t self, size_t page, const uint8_t *data) 749 { 750 struct nand_softc *sc = device_private(self); 751 struct nand_chip *chip = &sc->sc_chip; 752 size_t bs, cs, e, b; 753 uint8_t status; 754 uint8_t *ecc; 755 756 nand_command(self, ONFI_PAGE_PROGRAM); 757 nand_address_column(self, page, 0); 758 759 nand_busy(self); 760 761 bs = chip->nc_ecc->necc_block_size; 762 cs = chip->nc_ecc->necc_code_size; 763 ecc = chip->nc_oob_cache + chip->nc_ecc->necc_offset; 764 765 /* XXX code duplication */ 766 /* decide if we access by 8 or 16 bits */ 767 if (chip->nc_flags & NC_BUSWIDTH_16) { 768 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 769 nand_ecc_prepare(self, NAND_ECC_WRITE); 770 nand_write_buf_2(self, data + b, bs); 771 nand_ecc_compute(self, data + b, ecc + e); 772 } 773 /* write oob with ecc correction code */ 774 nand_write_buf_2(self, chip->nc_oob_cache, 775 chip->nc_spare_size); 776 } else { 777 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 778 nand_ecc_prepare(self, NAND_ECC_WRITE); 779 nand_write_buf_1(self, data + b, bs); 780 nand_ecc_compute(self, data + b, ecc + e); 781 } 782 /* write oob with ecc correction code */ 783 nand_write_buf_1(self, chip->nc_oob_cache, 784 chip->nc_spare_size); 785 } 786 787 nand_command(self, ONFI_PAGE_PROGRAM_START); 788 789 nand_busy(self); 790 791 /* for debugging ecc */ 792 #if 0 793 printf("dumping ecc %d\n--------------\n", chip->nc_ecc->necc_steps); 794 for (e = 0; e < chip->nc_ecc->necc_steps; e++) { 795 printf("0x"); 796 for (b = 0; b < cs; b++) { 797 printf("%.2hhx", ecc[e+b]); 798 } 799 printf("\n"); 800 } 801 printf("--------------\n"); 802 #endif 803 804 status = nand_get_status(self); 805 KASSERT(status & ONFI_STATUS_RDY); 806 if (status & ONFI_STATUS_FAIL) { 807 aprint_error_dev(self, "page program failed!\n"); 808 return EIO; 809 } 810 811 return 0; 812 } 813 814 /* read the OOB of a page */ 815 int 816 nand_read_oob(device_t self, size_t page, uint8_t *oob) 817 { 818 struct nand_softc *sc = device_private(self); 819 struct nand_chip *chip = &sc->sc_chip; 820 821 nand_prepare_read(self, page, chip->nc_page_size); 822 823 if (chip->nc_flags & NC_BUSWIDTH_16) 824 nand_read_buf_2(self, oob, chip->nc_spare_size); 825 else 826 nand_read_buf_1(self, oob, chip->nc_spare_size); 827 828 /* for debugging drivers */ 829 #if 0 830 nand_dump_data("oob", oob, chip->nc_spare_size); 831 #endif 832 833 return 0; 834 } 835 836 static int 837 nand_write_oob(device_t self, size_t offset, const void *oob) 838 { 839 struct nand_softc *sc = device_private(self); 840 struct nand_chip *chip = &sc->sc_chip; 841 uint8_t status; 842 843 nand_command(self, ONFI_PAGE_PROGRAM); 844 nand_address_column(self, offset, chip->nc_page_size); 845 nand_command(self, ONFI_PAGE_PROGRAM_START); 846 847 nand_busy(self); 848 849 if (chip->nc_flags & NC_BUSWIDTH_16) 850 nand_write_buf_2(self, oob, chip->nc_spare_size); 851 else 852 nand_write_buf_1(self, oob, chip->nc_spare_size); 853 854 status = nand_get_status(self); 855 KASSERT(status & ONFI_STATUS_RDY); 856 if (status & ONFI_STATUS_FAIL) 857 return EIO; 858 else 859 return 0; 860 } 861 862 void 863 nand_markbad(device_t self, size_t offset) 864 { 865 struct nand_softc *sc = device_private(self); 866 struct nand_chip *chip = &sc->sc_chip; 867 flash_off_t blockoffset, marker; 868 #ifdef NAND_BBT 869 flash_off_t block; 870 871 block = offset / chip->nc_block_size; 872 873 nand_bbt_block_markbad(self, block); 874 #endif 875 blockoffset = offset & chip->nc_block_mask; 876 marker = chip->nc_badmarker_offs & ~0x01; 877 878 /* check if it is already marked bad */ 879 if (nand_isbad(self, blockoffset)) 880 return; 881 882 nand_read_oob(self, blockoffset, chip->nc_oob_cache); 883 884 chip->nc_oob_cache[chip->nc_badmarker_offs] = 0x00; 885 chip->nc_oob_cache[chip->nc_badmarker_offs + 1] = 0x00; 886 887 nand_write_oob(self, blockoffset, chip->nc_oob_cache); 888 } 889 890 bool 891 nand_isfactorybad(device_t self, flash_off_t offset) 892 { 893 struct nand_softc *sc = device_private(self); 894 struct nand_chip *chip = &sc->sc_chip; 895 flash_off_t block, first_page, last_page, page; 896 int i; 897 898 /* Check for factory bad blocks first 899 * Factory bad blocks are marked in the first or last 900 * page of the blocks, see: ONFI 2.2, 3.2.2. 901 */ 902 block = offset / chip->nc_block_size; 903 first_page = block * chip->nc_block_size; 904 last_page = (block + 1) * chip->nc_block_size 905 - chip->nc_page_size; 906 907 for (i = 0, page = first_page; i < 2; i++, page = last_page) { 908 /* address OOB */ 909 nand_prepare_read(self, page, chip->nc_page_size); 910 911 if (chip->nc_flags & NC_BUSWIDTH_16) { 912 uint16_t word; 913 nand_read_2(self, &word); 914 if (word == 0x0000) 915 return true; 916 } else { 917 uint8_t byte; 918 nand_read_1(self, &byte); 919 if (byte == 0x00) 920 return true; 921 } 922 } 923 924 return false; 925 } 926 927 bool 928 nand_iswornoutbad(device_t self, flash_off_t offset) 929 { 930 struct nand_softc *sc = device_private(self); 931 struct nand_chip *chip = &sc->sc_chip; 932 flash_off_t block; 933 934 /* we inspect the first page of the block */ 935 block = offset & chip->nc_block_mask; 936 937 /* Linux/u-boot compatible badblock handling */ 938 if (chip->nc_flags & NC_BUSWIDTH_16) { 939 uint16_t word, mark; 940 941 nand_prepare_read(self, block, 942 chip->nc_page_size + (chip->nc_badmarker_offs & 0xfe)); 943 944 nand_read_2(self, &word); 945 mark = htole16(word); 946 if (chip->nc_badmarker_offs & 0x01) 947 mark >>= 8; 948 if ((mark & 0xff) != 0xff) 949 return true; 950 } else { 951 uint8_t byte; 952 953 nand_prepare_read(self, block, 954 chip->nc_page_size + chip->nc_badmarker_offs); 955 956 nand_read_1(self, &byte); 957 if (byte != 0xff) 958 return true; 959 } 960 961 return false; 962 } 963 964 bool 965 nand_isbad(device_t self, flash_off_t offset) 966 { 967 #ifdef NAND_BBT 968 struct nand_softc *sc = device_private(self); 969 struct nand_chip *chip = &sc->sc_chip; 970 flash_off_t block; 971 972 block = offset / chip->nc_block_size; 973 974 return nand_bbt_block_isbad(self, block); 975 #else 976 /* ONFI host requirement */ 977 if (nand_isfactorybad(self, offset)) 978 return true; 979 980 /* Look for Linux/U-Boot compatible bad marker */ 981 if (nand_iswornoutbad(self, offset)) 982 return true; 983 984 return false; 985 #endif 986 } 987 988 int 989 nand_erase_block(device_t self, size_t offset) 990 { 991 uint8_t status; 992 993 /* xxx calculate first page of block for address? */ 994 995 nand_command(self, ONFI_BLOCK_ERASE); 996 nand_address_row(self, offset); 997 nand_command(self, ONFI_BLOCK_ERASE_START); 998 999 nand_busy(self); 1000 1001 status = nand_get_status(self); 1002 KASSERT(status & ONFI_STATUS_RDY); 1003 if (status & ONFI_STATUS_FAIL) { 1004 aprint_error_dev(self, "block erase failed!\n"); 1005 nand_markbad(self, offset); 1006 return EIO; 1007 } else { 1008 return 0; 1009 } 1010 } 1011 1012 /* default functions for driver development */ 1013 1014 /* default ECC using hamming code of 256 byte chunks */ 1015 int 1016 nand_default_ecc_compute(device_t self, const uint8_t *data, uint8_t *code) 1017 { 1018 hamming_compute_256(data, code); 1019 1020 return 0; 1021 } 1022 1023 int 1024 nand_default_ecc_correct(device_t self, uint8_t *data, const uint8_t *origcode, 1025 const uint8_t *compcode) 1026 { 1027 return hamming_correct_256(data, origcode, compcode); 1028 } 1029 1030 void 1031 nand_default_select(device_t self, bool enable) 1032 { 1033 /* do nothing */ 1034 return; 1035 } 1036 1037 /* implementation of the block device API */ 1038 1039 int 1040 nand_flash_submit(device_t self, struct buf * const bp) 1041 { 1042 struct nand_softc *sc = device_private(self); 1043 1044 return flash_io_submit(&sc->sc_flash_io, bp); 1045 } 1046 1047 /* 1048 * handle (page) unaligned write to nand 1049 */ 1050 static int 1051 nand_flash_write_unaligned(device_t self, flash_off_t offset, size_t len, 1052 size_t *retlen, const uint8_t *buf) 1053 { 1054 struct nand_softc *sc = device_private(self); 1055 struct nand_chip *chip = &sc->sc_chip; 1056 flash_off_t first, last, firstoff; 1057 const uint8_t *bufp; 1058 flash_off_t addr; 1059 size_t left, count; 1060 int error = 0, i; 1061 1062 first = offset & chip->nc_page_mask; 1063 firstoff = offset & ~chip->nc_page_mask; 1064 /* XXX check if this should be len - 1 */ 1065 last = (offset + len) & chip->nc_page_mask; 1066 count = last - first + 1; 1067 1068 addr = first; 1069 *retlen = 0; 1070 1071 mutex_enter(&sc->sc_device_lock); 1072 if (count == 1) { 1073 if (nand_isbad(self, addr)) { 1074 aprint_error_dev(self, 1075 "nand_flash_write_unaligned: " 1076 "bad block encountered\n"); 1077 error = EIO; 1078 goto out; 1079 } 1080 1081 error = nand_read_page(self, addr, chip->nc_page_cache); 1082 if (error) { 1083 goto out; 1084 } 1085 1086 memcpy(chip->nc_page_cache + firstoff, buf, len); 1087 1088 error = nand_program_page(self, addr, chip->nc_page_cache); 1089 if (error) { 1090 goto out; 1091 } 1092 1093 *retlen = len; 1094 goto out; 1095 } 1096 1097 bufp = buf; 1098 left = len; 1099 1100 for (i = 0; i < count && left != 0; i++) { 1101 if (nand_isbad(self, addr)) { 1102 aprint_error_dev(self, 1103 "nand_flash_write_unaligned: " 1104 "bad block encountered\n"); 1105 error = EIO; 1106 goto out; 1107 } 1108 1109 if (i == 0) { 1110 error = nand_read_page(self, 1111 addr, chip->nc_page_cache); 1112 if (error) { 1113 goto out; 1114 } 1115 1116 memcpy(chip->nc_page_cache + firstoff, 1117 bufp, chip->nc_page_size - firstoff); 1118 1119 printf("program page: %s: %d\n", __FILE__, __LINE__); 1120 error = nand_program_page(self, 1121 addr, chip->nc_page_cache); 1122 if (error) { 1123 goto out; 1124 } 1125 1126 bufp += chip->nc_page_size - firstoff; 1127 left -= chip->nc_page_size - firstoff; 1128 *retlen += chip->nc_page_size - firstoff; 1129 1130 } else if (i == count - 1) { 1131 error = nand_read_page(self, 1132 addr, chip->nc_page_cache); 1133 if (error) { 1134 goto out; 1135 } 1136 1137 memcpy(chip->nc_page_cache, bufp, left); 1138 1139 error = nand_program_page(self, 1140 addr, chip->nc_page_cache); 1141 if (error) { 1142 goto out; 1143 } 1144 1145 *retlen += left; 1146 KASSERT(left < chip->nc_page_size); 1147 1148 } else { 1149 /* XXX debug */ 1150 if (left > chip->nc_page_size) { 1151 printf("left: %zu, i: %d, count: %zu\n", 1152 (size_t )left, i, count); 1153 } 1154 KASSERT(left > chip->nc_page_size); 1155 1156 error = nand_program_page(self, addr, bufp); 1157 if (error) { 1158 goto out; 1159 } 1160 1161 bufp += chip->nc_page_size; 1162 left -= chip->nc_page_size; 1163 *retlen += chip->nc_page_size; 1164 } 1165 1166 addr += chip->nc_page_size; 1167 } 1168 1169 KASSERT(*retlen == len); 1170 out: 1171 mutex_exit(&sc->sc_device_lock); 1172 1173 return error; 1174 } 1175 1176 int 1177 nand_flash_write(device_t self, flash_off_t offset, size_t len, size_t *retlen, 1178 const uint8_t *buf) 1179 { 1180 struct nand_softc *sc = device_private(self); 1181 struct nand_chip *chip = &sc->sc_chip; 1182 const uint8_t *bufp; 1183 size_t pages, page; 1184 daddr_t addr; 1185 int error = 0; 1186 1187 if ((offset + len) > chip->nc_size) { 1188 DPRINTF(("nand_flash_write: write (off: 0x%jx, len: %ju)," 1189 " is over device size (0x%jx)\n", 1190 (uintmax_t)offset, (uintmax_t)len, 1191 (uintmax_t)chip->nc_size)); 1192 return EINVAL; 1193 } 1194 1195 if (len % chip->nc_page_size != 0 || 1196 offset % chip->nc_page_size != 0) { 1197 return nand_flash_write_unaligned(self, 1198 offset, len, retlen, buf); 1199 } 1200 1201 pages = len / chip->nc_page_size; 1202 KASSERT(pages != 0); 1203 *retlen = 0; 1204 1205 addr = offset; 1206 bufp = buf; 1207 1208 mutex_enter(&sc->sc_device_lock); 1209 for (page = 0; page < pages; page++) { 1210 /* do we need this check here? */ 1211 if (nand_isbad(self, addr)) { 1212 aprint_error_dev(self, 1213 "nand_flash_write: bad block encountered\n"); 1214 1215 error = EIO; 1216 goto out; 1217 } 1218 1219 error = nand_program_page(self, addr, bufp); 1220 if (error) { 1221 goto out; 1222 } 1223 1224 addr += chip->nc_page_size; 1225 bufp += chip->nc_page_size; 1226 *retlen += chip->nc_page_size; 1227 } 1228 out: 1229 mutex_exit(&sc->sc_device_lock); 1230 DPRINTF(("page programming: retlen: %zu, len: %zu\n", *retlen, len)); 1231 1232 return error; 1233 } 1234 1235 /* 1236 * handle (page) unaligned read from nand 1237 */ 1238 static int 1239 nand_flash_read_unaligned(device_t self, size_t offset, 1240 size_t len, size_t *retlen, uint8_t *buf) 1241 { 1242 struct nand_softc *sc = device_private(self); 1243 struct nand_chip *chip = &sc->sc_chip; 1244 daddr_t first, last, count, firstoff; 1245 uint8_t *bufp; 1246 daddr_t addr; 1247 size_t left; 1248 int error = 0, i; 1249 1250 first = offset & chip->nc_page_mask; 1251 firstoff = offset & ~chip->nc_page_mask; 1252 last = (offset + len) & chip->nc_page_mask; 1253 count = (last - first) / chip->nc_page_size + 1; 1254 1255 addr = first; 1256 bufp = buf; 1257 left = len; 1258 *retlen = 0; 1259 1260 mutex_enter(&sc->sc_device_lock); 1261 if (count == 1) { 1262 error = nand_read_page(self, addr, chip->nc_page_cache); 1263 if (error) { 1264 goto out; 1265 } 1266 1267 memcpy(bufp, chip->nc_page_cache + firstoff, len); 1268 1269 *retlen = len; 1270 goto out; 1271 } 1272 1273 for (i = 0; i < count && left != 0; i++) { 1274 error = nand_read_page(self, addr, chip->nc_page_cache); 1275 if (error) { 1276 goto out; 1277 } 1278 1279 if (i == 0) { 1280 memcpy(bufp, chip->nc_page_cache + firstoff, 1281 chip->nc_page_size - firstoff); 1282 1283 bufp += chip->nc_page_size - firstoff; 1284 left -= chip->nc_page_size - firstoff; 1285 *retlen += chip->nc_page_size - firstoff; 1286 1287 } else if (i == count - 1) { 1288 memcpy(bufp, chip->nc_page_cache, left); 1289 *retlen += left; 1290 KASSERT(left < chip->nc_page_size); 1291 1292 } else { 1293 memcpy(bufp, chip->nc_page_cache, chip->nc_page_size); 1294 1295 bufp += chip->nc_page_size; 1296 left -= chip->nc_page_size; 1297 *retlen += chip->nc_page_size; 1298 } 1299 1300 addr += chip->nc_page_size; 1301 } 1302 KASSERT(*retlen == len); 1303 out: 1304 mutex_exit(&sc->sc_device_lock); 1305 1306 return error; 1307 } 1308 1309 int 1310 nand_flash_read(device_t self, flash_off_t offset, size_t len, size_t *retlen, 1311 uint8_t *buf) 1312 { 1313 struct nand_softc *sc = device_private(self); 1314 struct nand_chip *chip = &sc->sc_chip; 1315 uint8_t *bufp; 1316 size_t addr; 1317 size_t i, pages; 1318 int error = 0; 1319 1320 *retlen = 0; 1321 1322 DPRINTF(("nand_flash_read: off: 0x%jx, len: %zu\n", 1323 (uintmax_t)offset, len)); 1324 1325 if (__predict_false((offset + len) > chip->nc_size)) { 1326 DPRINTF(("nand_flash_read: read (off: 0x%jx, len: %zu)," 1327 " is over device size (%ju)\n", (uintmax_t)offset, 1328 len, (uintmax_t)chip->nc_size)); 1329 return EINVAL; 1330 } 1331 1332 /* Handle unaligned access, shouldnt be needed when using the 1333 * block device, as strategy handles it, so only low level 1334 * accesses will use this path 1335 */ 1336 /* XXX^2 */ 1337 #if 0 1338 if (len < chip->nc_page_size) 1339 panic("TODO page size is larger than read size"); 1340 #endif 1341 1342 if (len % chip->nc_page_size != 0 || 1343 offset % chip->nc_page_size != 0) { 1344 return nand_flash_read_unaligned(self, 1345 offset, len, retlen, buf); 1346 } 1347 1348 bufp = buf; 1349 addr = offset; 1350 pages = len / chip->nc_page_size; 1351 1352 mutex_enter(&sc->sc_device_lock); 1353 for (i = 0; i < pages; i++) { 1354 /* XXX do we need this check here? */ 1355 if (nand_isbad(self, addr)) { 1356 aprint_error_dev(self, "bad block encountered\n"); 1357 error = EIO; 1358 goto out; 1359 } 1360 error = nand_read_page(self, addr, bufp); 1361 if (error) 1362 goto out; 1363 1364 bufp += chip->nc_page_size; 1365 addr += chip->nc_page_size; 1366 *retlen += chip->nc_page_size; 1367 } 1368 out: 1369 mutex_exit(&sc->sc_device_lock); 1370 1371 return error; 1372 } 1373 1374 int 1375 nand_flash_isbad(device_t self, flash_off_t ofs, bool *isbad) 1376 { 1377 struct nand_softc *sc = device_private(self); 1378 struct nand_chip *chip = &sc->sc_chip; 1379 bool result; 1380 1381 if (ofs > chip->nc_size) { 1382 DPRINTF(("nand_flash_isbad: offset 0x%jx is larger than" 1383 " device size (0x%jx)\n", (uintmax_t)ofs, 1384 (uintmax_t)chip->nc_size)); 1385 return EINVAL; 1386 } 1387 1388 if (ofs % chip->nc_block_size != 0) { 1389 DPRINTF(("offset (0x%jx) is not a multiple of block size " 1390 "(%ju)", 1391 (uintmax_t)ofs, (uintmax_t)chip->nc_block_size)); 1392 return EINVAL; 1393 } 1394 1395 mutex_enter(&sc->sc_device_lock); 1396 result = nand_isbad(self, ofs); 1397 mutex_exit(&sc->sc_device_lock); 1398 1399 *isbad = result; 1400 1401 return 0; 1402 } 1403 1404 int 1405 nand_flash_markbad(device_t self, flash_off_t ofs) 1406 { 1407 struct nand_softc *sc = device_private(self); 1408 struct nand_chip *chip = &sc->sc_chip; 1409 1410 if (ofs > chip->nc_size) { 1411 DPRINTF(("nand_flash_markbad: offset 0x%jx is larger than" 1412 " device size (0x%jx)\n", ofs, 1413 (uintmax_t)chip->nc_size)); 1414 return EINVAL; 1415 } 1416 1417 if (ofs % chip->nc_block_size != 0) { 1418 panic("offset (%ju) is not a multiple of block size (%ju)", 1419 (uintmax_t)ofs, (uintmax_t)chip->nc_block_size); 1420 } 1421 1422 mutex_enter(&sc->sc_device_lock); 1423 nand_markbad(self, ofs); 1424 mutex_exit(&sc->sc_device_lock); 1425 1426 return 0; 1427 } 1428 1429 int 1430 nand_flash_erase(device_t self, 1431 struct flash_erase_instruction *ei) 1432 { 1433 struct nand_softc *sc = device_private(self); 1434 struct nand_chip *chip = &sc->sc_chip; 1435 flash_off_t addr; 1436 int error = 0; 1437 1438 if (ei->ei_addr < 0 || ei->ei_len < chip->nc_block_size) 1439 return EINVAL; 1440 1441 if (ei->ei_addr + ei->ei_len > chip->nc_size) { 1442 DPRINTF(("nand_flash_erase: erase address is over the end" 1443 " of the device\n")); 1444 return EINVAL; 1445 } 1446 1447 if (ei->ei_addr % chip->nc_block_size != 0) { 1448 aprint_error_dev(self, 1449 "nand_flash_erase: ei_addr (%ju) is not" 1450 " a multiple of block size (%ju)", 1451 (uintmax_t)ei->ei_addr, 1452 (uintmax_t)chip->nc_block_size); 1453 return EINVAL; 1454 } 1455 1456 if (ei->ei_len % chip->nc_block_size != 0) { 1457 aprint_error_dev(self, 1458 "nand_flash_erase: ei_len (%ju) is not" 1459 " a multiple of block size (%ju)", 1460 (uintmax_t)ei->ei_len, 1461 (uintmax_t)chip->nc_block_size); 1462 return EINVAL; 1463 } 1464 1465 mutex_enter(&sc->sc_device_lock); 1466 addr = ei->ei_addr; 1467 while (addr < ei->ei_addr + ei->ei_len) { 1468 if (nand_isbad(self, addr)) { 1469 aprint_error_dev(self, "bad block encountered\n"); 1470 ei->ei_state = FLASH_ERASE_FAILED; 1471 error = EIO; 1472 goto out; 1473 } 1474 1475 error = nand_erase_block(self, addr); 1476 if (error) { 1477 ei->ei_state = FLASH_ERASE_FAILED; 1478 goto out; 1479 } 1480 1481 addr += chip->nc_block_size; 1482 } 1483 mutex_exit(&sc->sc_device_lock); 1484 1485 ei->ei_state = FLASH_ERASE_DONE; 1486 if (ei->ei_callback != NULL) { 1487 ei->ei_callback(ei); 1488 } 1489 1490 return 0; 1491 out: 1492 mutex_exit(&sc->sc_device_lock); 1493 1494 return error; 1495 } 1496 1497 MODULE(MODULE_CLASS_DRIVER, nand, "flash"); 1498 1499 #ifdef _MODULE 1500 #include "ioconf.c" 1501 #endif 1502 1503 static int 1504 nand_modcmd(modcmd_t cmd, void *opaque) 1505 { 1506 switch (cmd) { 1507 case MODULE_CMD_INIT: 1508 #ifdef _MODULE 1509 return config_init_component(cfdriver_ioconf_nand, 1510 cfattach_ioconf_nand, cfdata_ioconf_nand); 1511 #else 1512 return 0; 1513 #endif 1514 case MODULE_CMD_FINI: 1515 #ifdef _MODULE 1516 return config_fini_component(cfdriver_ioconf_nand, 1517 cfattach_ioconf_nand, cfdata_ioconf_nand); 1518 #else 1519 return 0; 1520 #endif 1521 default: 1522 return ENOTTY; 1523 } 1524 } 1525