1 /* $NetBSD: nand.c,v 1.24 2016/10/04 14:43:55 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Department of Software Engineering, 5 * University of Szeged, Hungary 6 * Copyright (c) 2010 Adam Hoka <ahoka@NetBSD.org> 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by the Department of Software Engineering, University of Szeged, Hungary 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Common driver for NAND chips implementing the ONFI 2.2 specification */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: nand.c,v 1.24 2016/10/04 14:43:55 kiyohara Exp $"); 38 39 #include "locators.h" 40 41 #include <sys/param.h> 42 #include <sys/types.h> 43 #include <sys/device.h> 44 #include <sys/kmem.h> 45 #include <sys/atomic.h> 46 47 #include <dev/flash/flash.h> 48 #include <dev/flash/flash_io.h> 49 #include <dev/nand/nand.h> 50 #include <dev/nand/onfi.h> 51 #include <dev/nand/hamming.h> 52 #include <dev/nand/nand_bbt.h> 53 #include <dev/nand/nand_crc.h> 54 55 #include "opt_nand.h" 56 57 int nand_match(device_t, cfdata_t, void *); 58 void nand_attach(device_t, device_t, void *); 59 int nand_detach(device_t, int); 60 bool nand_shutdown(device_t, int); 61 62 int nand_print(void *, const char *); 63 64 static int nand_search(device_t, cfdata_t, const int *, void *); 65 static void nand_address_row(device_t, size_t); 66 static inline uint8_t nand_get_status(device_t); 67 static void nand_address_column(device_t, size_t, size_t); 68 static int nand_fill_chip_structure(device_t, struct nand_chip *); 69 static int nand_scan_media(device_t, struct nand_chip *); 70 static bool nand_check_wp(device_t); 71 72 CFATTACH_DECL_NEW(nand, sizeof(struct nand_softc), 73 nand_match, nand_attach, nand_detach, NULL); 74 75 #ifdef NAND_DEBUG 76 int nanddebug = NAND_DEBUG; 77 #endif 78 79 struct flash_interface nand_flash_if = { 80 .type = FLASH_TYPE_NAND, 81 82 .read = nand_flash_read, 83 .write = nand_flash_write, 84 .erase = nand_flash_erase, 85 .block_isbad = nand_flash_isbad, 86 .block_markbad = nand_flash_markbad, 87 88 .submit = nand_flash_submit 89 }; 90 91 #ifdef NAND_VERBOSE 92 const struct nand_manufacturer nand_mfrs[] = { 93 { NAND_MFR_AMD, "AMD" }, 94 { NAND_MFR_FUJITSU, "Fujitsu" }, 95 { NAND_MFR_RENESAS, "Renesas" }, 96 { NAND_MFR_STMICRO, "ST Micro" }, 97 { NAND_MFR_MICRON, "Micron" }, 98 { NAND_MFR_NATIONAL, "National" }, 99 { NAND_MFR_TOSHIBA, "Toshiba" }, 100 { NAND_MFR_HYNIX, "Hynix" }, 101 { NAND_MFR_SAMSUNG, "Samsung" }, 102 { NAND_MFR_UNKNOWN, "Unknown" } 103 }; 104 105 static const char * 106 nand_midtoname(int id) 107 { 108 int i; 109 110 for (i = 0; nand_mfrs[i].id != 0; i++) { 111 if (nand_mfrs[i].id == id) 112 return nand_mfrs[i].name; 113 } 114 115 KASSERT(nand_mfrs[i].id == 0); 116 117 return nand_mfrs[i].name; 118 } 119 #endif 120 121 /* ARGSUSED */ 122 int 123 nand_match(device_t parent, cfdata_t match, void *aux) 124 { 125 /* pseudo device, always attaches */ 126 return 1; 127 } 128 129 void 130 nand_attach(device_t parent, device_t self, void *aux) 131 { 132 struct nand_softc *sc = device_private(self); 133 struct nand_attach_args *naa = aux; 134 struct nand_chip *chip = &sc->sc_chip; 135 136 sc->sc_dev = self; 137 sc->controller_dev = parent; 138 sc->nand_if = naa->naa_nand_if; 139 140 aprint_naive("\n"); 141 142 if (nand_check_wp(self)) { 143 aprint_error("NAND chip is write protected!\n"); 144 return; 145 } 146 147 if (nand_scan_media(self, chip)) { 148 return; 149 } 150 151 nand_flash_if.erasesize = chip->nc_block_size; 152 nand_flash_if.page_size = chip->nc_page_size; 153 nand_flash_if.writesize = chip->nc_page_size; 154 155 /* allocate cache */ 156 chip->nc_oob_cache = kmem_alloc(chip->nc_spare_size, KM_SLEEP); 157 chip->nc_page_cache = kmem_alloc(chip->nc_page_size, KM_SLEEP); 158 159 mutex_init(&sc->sc_device_lock, MUTEX_DEFAULT, IPL_NONE); 160 161 if (flash_sync_thread_init(&sc->sc_flash_io, self, &nand_flash_if)) { 162 goto error; 163 } 164 165 if (!pmf_device_register1(sc->sc_dev, NULL, NULL, nand_shutdown)) 166 aprint_error_dev(sc->sc_dev, 167 "couldn't establish power handler\n"); 168 169 #ifdef NAND_BBT 170 nand_bbt_init(self); 171 nand_bbt_scan(self); 172 #endif 173 174 /* 175 * Attach all our devices 176 */ 177 config_search_ia(nand_search, self, NULL, NULL); 178 179 return; 180 error: 181 kmem_free(chip->nc_oob_cache, chip->nc_spare_size); 182 kmem_free(chip->nc_page_cache, chip->nc_page_size); 183 mutex_destroy(&sc->sc_device_lock); 184 } 185 186 static int 187 nand_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 188 { 189 struct nand_softc *sc = device_private(parent); 190 struct nand_chip *chip = &sc->sc_chip; 191 struct flash_attach_args faa; 192 193 faa.flash_if = &nand_flash_if; 194 195 faa.partinfo.part_offset = cf->cf_loc[FLASHBUSCF_OFFSET]; 196 197 if (cf->cf_loc[FLASHBUSCF_SIZE] == 0) { 198 faa.partinfo.part_size = chip->nc_size - 199 faa.partinfo.part_offset; 200 } else { 201 faa.partinfo.part_size = cf->cf_loc[FLASHBUSCF_SIZE]; 202 } 203 204 if (cf->cf_loc[FLASHBUSCF_READONLY]) 205 faa.partinfo.part_flags = FLASH_PART_READONLY; 206 else 207 faa.partinfo.part_flags = 0; 208 209 if (config_match(parent, cf, &faa)) { 210 if (config_attach(parent, cf, &faa, nand_print) != NULL) { 211 return 0; 212 } else { 213 return 1; 214 } 215 } 216 217 return 1; 218 } 219 220 int 221 nand_detach(device_t self, int flags) 222 { 223 struct nand_softc *sc = device_private(self); 224 struct nand_chip *chip = &sc->sc_chip; 225 int error = 0; 226 227 error = config_detach_children(self, flags); 228 if (error) { 229 return error; 230 } 231 232 flash_sync_thread_destroy(&sc->sc_flash_io); 233 #ifdef NAND_BBT 234 nand_bbt_detach(self); 235 #endif 236 /* free oob cache */ 237 kmem_free(chip->nc_oob_cache, chip->nc_spare_size); 238 kmem_free(chip->nc_page_cache, chip->nc_page_size); 239 kmem_free(chip->nc_ecc_cache, chip->nc_ecc->necc_size); 240 241 mutex_destroy(&sc->sc_device_lock); 242 243 pmf_device_deregister(sc->sc_dev); 244 245 return error; 246 } 247 248 int 249 nand_print(void *aux, const char *pnp) 250 { 251 if (pnp != NULL) 252 aprint_normal("nand at %s\n", pnp); 253 254 return UNCONF; 255 } 256 257 /* ask for a nand driver to attach to the controller */ 258 device_t 259 nand_attach_mi(struct nand_interface *nand_if, device_t parent) 260 { 261 struct nand_attach_args arg; 262 263 KASSERT(nand_if != NULL); 264 265 /* fill the defaults if we have null pointers */ 266 if (nand_if->program_page == NULL) { 267 nand_if->program_page = &nand_default_program_page; 268 } 269 270 if (nand_if->read_page == NULL) { 271 nand_if->read_page = &nand_default_read_page; 272 } 273 274 arg.naa_nand_if = nand_if; 275 return config_found_ia(parent, "nandbus", &arg, nand_print); 276 } 277 278 /* default everything to reasonable values, to ease future api changes */ 279 void 280 nand_init_interface(struct nand_interface *interface) 281 { 282 interface->select = &nand_default_select; 283 interface->command = NULL; 284 interface->address = NULL; 285 interface->read_buf_1 = NULL; 286 interface->read_buf_2 = NULL; 287 interface->read_1 = NULL; 288 interface->read_2 = NULL; 289 interface->write_buf_1 = NULL; 290 interface->write_buf_2 = NULL; 291 interface->write_1 = NULL; 292 interface->write_2 = NULL; 293 interface->busy = NULL; 294 295 /*- 296 * most drivers dont want to change this, but some implement 297 * read/program in one step 298 */ 299 interface->program_page = &nand_default_program_page; 300 interface->read_page = &nand_default_read_page; 301 302 /* default to soft ecc, that should work everywhere */ 303 interface->ecc_compute = &nand_default_ecc_compute; 304 interface->ecc_correct = &nand_default_ecc_correct; 305 interface->ecc_prepare = NULL; 306 interface->ecc.necc_code_size = 3; 307 interface->ecc.necc_block_size = 256; 308 interface->ecc.necc_type = NAND_ECC_TYPE_SW; 309 } 310 311 #if 0 312 /* handle quirks here */ 313 static void 314 nand_quirks(device_t self, struct nand_chip *chip) 315 { 316 /* this is an example only! */ 317 switch (chip->nc_manf_id) { 318 case NAND_MFR_SAMSUNG: 319 if (chip->nc_dev_id == 0x00) { 320 /* do something only samsung chips need */ 321 /* or */ 322 /* chip->nc_quirks |= NC_QUIRK_NO_READ_START */ 323 } 324 } 325 326 return; 327 } 328 #endif 329 330 static int 331 nand_fill_chip_structure_legacy(device_t self, struct nand_chip *chip) 332 { 333 switch (chip->nc_manf_id) { 334 case NAND_MFR_MICRON: 335 return nand_read_parameters_micron(self, chip); 336 case NAND_MFR_SAMSUNG: 337 return nand_read_parameters_samsung(self, chip); 338 default: 339 return 1; 340 } 341 342 return 0; 343 } 344 345 /** 346 * scan media to determine the chip's properties 347 * this function resets the device 348 */ 349 static int 350 nand_scan_media(device_t self, struct nand_chip *chip) 351 { 352 struct nand_softc *sc = device_private(self); 353 struct nand_ecc *ecc; 354 uint8_t onfi_signature[4]; 355 356 nand_select(self, true); 357 nand_command(self, ONFI_RESET); 358 KASSERT(nand_get_status(self) & ONFI_STATUS_RDY); 359 nand_select(self, false); 360 361 /* check if the device implements the ONFI standard */ 362 nand_select(self, true); 363 nand_command(self, ONFI_READ_ID); 364 nand_address(self, 0x20); 365 nand_read_1(self, &onfi_signature[0]); 366 nand_read_1(self, &onfi_signature[1]); 367 nand_read_1(self, &onfi_signature[2]); 368 nand_read_1(self, &onfi_signature[3]); 369 nand_select(self, false); 370 371 if (onfi_signature[0] != 'O' || onfi_signature[1] != 'N' || 372 onfi_signature[2] != 'F' || onfi_signature[3] != 'I') { 373 chip->nc_isonfi = false; 374 375 aprint_normal(": Legacy NAND Flash\n"); 376 377 nand_read_id(self, &chip->nc_manf_id, &chip->nc_dev_id); 378 379 if (nand_fill_chip_structure_legacy(self, chip)) { 380 aprint_error_dev(self, 381 "can't read device parameters for legacy chip\n"); 382 return 1; 383 } 384 } else { 385 chip->nc_isonfi = true; 386 387 aprint_normal(": ONFI NAND Flash\n"); 388 389 nand_read_id(self, &chip->nc_manf_id, &chip->nc_dev_id); 390 391 if (nand_fill_chip_structure(self, chip)) { 392 aprint_error_dev(self, 393 "can't read device parameters\n"); 394 return 1; 395 } 396 } 397 398 #ifdef NAND_VERBOSE 399 aprint_normal_dev(self, 400 "manufacturer id: 0x%.2x (%s), device id: 0x%.2x\n", 401 chip->nc_manf_id, 402 nand_midtoname(chip->nc_manf_id), 403 chip->nc_dev_id); 404 #endif 405 406 aprint_normal_dev(self, 407 "page size: %" PRIu32 " bytes, spare size: %" PRIu32 " bytes, " 408 "block size: %" PRIu32 " bytes\n", 409 chip->nc_page_size, chip->nc_spare_size, chip->nc_block_size); 410 411 aprint_normal_dev(self, 412 "LUN size: %" PRIu32 " blocks, LUNs: %" PRIu8 413 ", total storage size: %" PRIu64 " MB\n", 414 chip->nc_lun_blocks, chip->nc_num_luns, 415 chip->nc_size / 1024 / 1024); 416 417 aprint_normal_dev(self, "column cycles: %" PRIu8 ", row cycles: %" 418 PRIu8 ", width: %s\n", 419 chip->nc_addr_cycles_column, chip->nc_addr_cycles_row, 420 (chip->nc_flags & NC_BUSWIDTH_16) ? "x16" : "x8"); 421 422 ecc = chip->nc_ecc = &sc->nand_if->ecc; 423 424 /* 425 * calculate the place of ecc data in oob 426 * we try to be compatible with Linux here 427 */ 428 switch (chip->nc_spare_size) { 429 case 8: 430 ecc->necc_offset = 0; 431 break; 432 case 16: 433 ecc->necc_offset = 0; 434 break; 435 case 32: 436 ecc->necc_offset = 0; 437 break; 438 case 64: 439 ecc->necc_offset = 40; 440 break; 441 case 128: 442 ecc->necc_offset = 80; 443 break; 444 default: 445 panic("OOB size %" PRIu32 " is unexpected", chip->nc_spare_size); 446 } 447 448 ecc->necc_steps = chip->nc_page_size / ecc->necc_block_size; 449 ecc->necc_size = ecc->necc_steps * ecc->necc_code_size; 450 451 /* check if we fit in oob */ 452 if (ecc->necc_offset + ecc->necc_size > chip->nc_spare_size) { 453 panic("NAND ECC bits dont fit in OOB"); 454 } 455 456 /* TODO: mark free oob area available for file systems */ 457 458 chip->nc_ecc_cache = kmem_zalloc(ecc->necc_size, KM_SLEEP); 459 460 /* 461 * calculate badblock marker offset in oob 462 * we try to be compatible with linux here 463 */ 464 if (chip->nc_page_size > 512) 465 chip->nc_badmarker_offs = 0; 466 else 467 chip->nc_badmarker_offs = 5; 468 469 /* Calculate page shift and mask */ 470 chip->nc_page_shift = ffs(chip->nc_page_size) - 1; 471 chip->nc_page_mask = ~(chip->nc_page_size - 1); 472 /* same for block */ 473 chip->nc_block_shift = ffs(chip->nc_block_size) - 1; 474 chip->nc_block_mask = ~(chip->nc_block_size - 1); 475 476 /* look for quirks here if needed in future */ 477 /* nand_quirks(self, chip); */ 478 479 return 0; 480 } 481 482 void 483 nand_read_id(device_t self, uint8_t *manf, uint8_t *dev) 484 { 485 nand_select(self, true); 486 nand_command(self, ONFI_READ_ID); 487 nand_address(self, 0x00); 488 489 nand_read_1(self, manf); 490 nand_read_1(self, dev); 491 492 nand_select(self, false); 493 } 494 495 int 496 nand_read_parameter_page(device_t self, struct onfi_parameter_page *params) 497 { 498 uint8_t *bufp; 499 uint16_t crc; 500 int i;//, tries = 0; 501 502 KASSERT(sizeof(*params) == 256); 503 504 //read_params: 505 // tries++; 506 507 nand_select(self, true); 508 nand_command(self, ONFI_READ_PARAMETER_PAGE); 509 nand_address(self, 0x00); 510 511 nand_busy(self); 512 513 /* TODO check the signature if it contains at least 2 letters */ 514 515 bufp = (uint8_t *)params; 516 /* XXX why i am not using read_buf? */ 517 for (i = 0; i < 256; i++) { 518 nand_read_1(self, &bufp[i]); 519 } 520 nand_select(self, false); 521 522 /* validate the parameter page with the crc */ 523 crc = nand_crc16(bufp, 254); 524 525 if (crc != params->param_integrity_crc) { 526 aprint_error_dev(self, "parameter page crc check failed\n"); 527 /* TODO: we should read the next parameter page copy */ 528 return 1; 529 } 530 531 return 0; 532 } 533 534 static int 535 nand_fill_chip_structure(device_t self, struct nand_chip *chip) 536 { 537 struct onfi_parameter_page params; 538 uint8_t vendor[13], model[21]; 539 int i; 540 541 if (nand_read_parameter_page(self, ¶ms)) { 542 return 1; 543 } 544 545 /* strip manufacturer and model string */ 546 strlcpy(vendor, params.param_manufacturer, sizeof(vendor)); 547 for (i = 11; i > 0 && vendor[i] == ' '; i--) 548 vendor[i] = 0; 549 strlcpy(model, params.param_model, sizeof(model)); 550 for (i = 19; i > 0 && model[i] == ' '; i--) 551 model[i] = 0; 552 553 aprint_normal_dev(self, "vendor: %s, model: %s\n", vendor, model); 554 555 chip->nc_page_size = le32toh(params.param_pagesize); 556 chip->nc_block_size = 557 le32toh(params.param_blocksize) * chip->nc_page_size; 558 chip->nc_spare_size = le16toh(params.param_sparesize); 559 chip->nc_lun_blocks = le32toh(params.param_lunsize); 560 chip->nc_num_luns = params.param_numluns; 561 562 chip->nc_size = 563 chip->nc_block_size * chip->nc_lun_blocks * chip->nc_num_luns; 564 565 /* the lower 4 bits contain the row address cycles */ 566 chip->nc_addr_cycles_row = params.param_addr_cycles & 0x07; 567 /* the upper 4 bits contain the column address cycles */ 568 chip->nc_addr_cycles_column = (params.param_addr_cycles & ~0x07) >> 4; 569 570 uint16_t features = le16toh(params.param_features); 571 if (features & ONFI_FEATURE_16BIT) { 572 chip->nc_flags |= NC_BUSWIDTH_16; 573 } 574 575 if (features & ONFI_FEATURE_EXTENDED_PARAM) { 576 chip->nc_flags |= NC_EXTENDED_PARAM; 577 } 578 579 return 0; 580 } 581 582 /* ARGSUSED */ 583 bool 584 nand_shutdown(device_t self, int howto) 585 { 586 return true; 587 } 588 589 static void 590 nand_address_column(device_t self, size_t row, size_t column) 591 { 592 struct nand_softc *sc = device_private(self); 593 struct nand_chip *chip = &sc->sc_chip; 594 uint8_t i; 595 596 DPRINTF(("addressing row: 0x%jx column: %" PRIu32 "\n", 597 (uintmax_t )row, column)); 598 599 /* XXX TODO */ 600 row >>= chip->nc_page_shift; 601 602 /* Write the column (subpage) address */ 603 if (chip->nc_flags & NC_BUSWIDTH_16) 604 column >>= 1; 605 for (i = 0; i < chip->nc_addr_cycles_column; i++, column >>= 8) 606 nand_address(self, column & 0xff); 607 608 /* Write the row (page) address */ 609 for (i = 0; i < chip->nc_addr_cycles_row; i++, row >>= 8) 610 nand_address(self, row & 0xff); 611 } 612 613 static void 614 nand_address_row(device_t self, size_t row) 615 { 616 struct nand_softc *sc = device_private(self); 617 struct nand_chip *chip = &sc->sc_chip; 618 int i; 619 620 /* XXX TODO */ 621 row >>= chip->nc_page_shift; 622 623 /* Write the row (page) address */ 624 for (i = 0; i < chip->nc_addr_cycles_row; i++, row >>= 8) 625 nand_address(self, row & 0xff); 626 } 627 628 static inline uint8_t 629 nand_get_status(device_t self) 630 { 631 uint8_t status; 632 633 nand_command(self, ONFI_READ_STATUS); 634 nand_busy(self); 635 nand_read_1(self, &status); 636 637 return status; 638 } 639 640 static bool 641 nand_check_wp(device_t self) 642 { 643 if (nand_get_status(self) & 0x80) 644 return false; 645 else 646 return true; 647 } 648 649 static void 650 nand_prepare_read(device_t self, flash_off_t row, flash_off_t column) 651 { 652 nand_command(self, ONFI_READ); 653 nand_address_column(self, row, column); 654 nand_command(self, ONFI_READ_START); 655 656 nand_busy(self); 657 } 658 659 /* read a page with ecc correction, default implementation */ 660 int 661 nand_default_read_page(device_t self, size_t offset, uint8_t *data) 662 { 663 struct nand_softc *sc = device_private(self); 664 struct nand_chip *chip = &sc->sc_chip; 665 size_t b, bs, e, cs; 666 uint8_t *ecc; 667 int result; 668 669 nand_prepare_read(self, offset, 0); 670 671 bs = chip->nc_ecc->necc_block_size; 672 cs = chip->nc_ecc->necc_code_size; 673 674 /* decide if we access by 8 or 16 bits */ 675 if (chip->nc_flags & NC_BUSWIDTH_16) { 676 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 677 nand_ecc_prepare(self, NAND_ECC_READ); 678 nand_read_buf_2(self, data + b, bs); 679 nand_ecc_compute(self, data + b, 680 chip->nc_ecc_cache + e); 681 } 682 } else { 683 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 684 nand_ecc_prepare(self, NAND_ECC_READ); 685 nand_read_buf_1(self, data + b, bs); 686 nand_ecc_compute(self, data + b, 687 chip->nc_ecc_cache + e); 688 } 689 } 690 691 /* for debugging new drivers */ 692 #if 0 693 nand_dump_data("page", data, chip->nc_page_size); 694 #endif 695 696 nand_read_oob(self, offset, chip->nc_oob_cache); 697 ecc = chip->nc_oob_cache + chip->nc_ecc->necc_offset; 698 699 /* useful for debugging new ecc drivers */ 700 #if 0 701 printf("dumping ecc %d\n--------------\n", chip->nc_ecc->necc_steps); 702 for (e = 0; e < chip->nc_ecc->necc_steps; e++) { 703 printf("0x"); 704 for (b = 0; b < cs; b++) { 705 printf("%.2hhx", ecc[e+b]); 706 } 707 printf(" 0x"); 708 for (b = 0; b < cs; b++) { 709 printf("%.2hhx", chip->nc_ecc_cache[e+b]); 710 } 711 printf("\n"); 712 } 713 printf("--------------\n"); 714 #endif 715 716 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 717 result = nand_ecc_correct(self, data + b, ecc + e, 718 chip->nc_ecc_cache + e); 719 720 switch (result) { 721 case NAND_ECC_OK: 722 break; 723 case NAND_ECC_CORRECTED: 724 aprint_error_dev(self, 725 "data corrected with ECC at page offset 0x%jx " 726 "block %zu\n", (uintmax_t)offset, b); 727 break; 728 case NAND_ECC_TWOBIT: 729 aprint_error_dev(self, 730 "uncorrectable ECC error at page offset 0x%jx " 731 "block %zu\n", (uintmax_t)offset, b); 732 return EIO; 733 break; 734 case NAND_ECC_INVALID: 735 aprint_error_dev(self, 736 "invalid ECC in oob at page offset 0x%jx " 737 "block %zu\n", (uintmax_t)offset, b); 738 return EIO; 739 break; 740 default: 741 panic("invalid ECC correction errno"); 742 } 743 } 744 745 return 0; 746 } 747 748 int 749 nand_default_program_page(device_t self, size_t page, const uint8_t *data) 750 { 751 struct nand_softc *sc = device_private(self); 752 struct nand_chip *chip = &sc->sc_chip; 753 size_t bs, cs, e, b; 754 uint8_t status; 755 uint8_t *ecc; 756 757 nand_command(self, ONFI_PAGE_PROGRAM); 758 nand_address_column(self, page, 0); 759 760 nand_busy(self); 761 762 bs = chip->nc_ecc->necc_block_size; 763 cs = chip->nc_ecc->necc_code_size; 764 ecc = chip->nc_oob_cache + chip->nc_ecc->necc_offset; 765 766 /* XXX code duplication */ 767 /* decide if we access by 8 or 16 bits */ 768 if (chip->nc_flags & NC_BUSWIDTH_16) { 769 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 770 nand_ecc_prepare(self, NAND_ECC_WRITE); 771 nand_write_buf_2(self, data + b, bs); 772 nand_ecc_compute(self, data + b, ecc + e); 773 } 774 /* write oob with ecc correction code */ 775 nand_write_buf_2(self, chip->nc_oob_cache, 776 chip->nc_spare_size); 777 } else { 778 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 779 nand_ecc_prepare(self, NAND_ECC_WRITE); 780 nand_write_buf_1(self, data + b, bs); 781 nand_ecc_compute(self, data + b, ecc + e); 782 } 783 /* write oob with ecc correction code */ 784 nand_write_buf_1(self, chip->nc_oob_cache, 785 chip->nc_spare_size); 786 } 787 788 nand_command(self, ONFI_PAGE_PROGRAM_START); 789 790 nand_busy(self); 791 792 /* for debugging ecc */ 793 #if 0 794 printf("dumping ecc %d\n--------------\n", chip->nc_ecc->necc_steps); 795 for (e = 0; e < chip->nc_ecc->necc_steps; e++) { 796 printf("0x"); 797 for (b = 0; b < cs; b++) { 798 printf("%.2hhx", ecc[e+b]); 799 } 800 printf("\n"); 801 } 802 printf("--------------\n"); 803 #endif 804 805 status = nand_get_status(self); 806 KASSERT(status & ONFI_STATUS_RDY); 807 if (status & ONFI_STATUS_FAIL) { 808 aprint_error_dev(self, "page program failed!\n"); 809 return EIO; 810 } 811 812 return 0; 813 } 814 815 /* read the OOB of a page */ 816 int 817 nand_read_oob(device_t self, size_t page, uint8_t *oob) 818 { 819 struct nand_softc *sc = device_private(self); 820 struct nand_chip *chip = &sc->sc_chip; 821 822 nand_prepare_read(self, page, chip->nc_page_size); 823 824 if (chip->nc_flags & NC_BUSWIDTH_16) 825 nand_read_buf_2(self, oob, chip->nc_spare_size); 826 else 827 nand_read_buf_1(self, oob, chip->nc_spare_size); 828 829 /* for debugging drivers */ 830 #if 0 831 nand_dump_data("oob", oob, chip->nc_spare_size); 832 #endif 833 834 return 0; 835 } 836 837 static int 838 nand_write_oob(device_t self, size_t offset, const void *oob) 839 { 840 struct nand_softc *sc = device_private(self); 841 struct nand_chip *chip = &sc->sc_chip; 842 uint8_t status; 843 844 nand_command(self, ONFI_PAGE_PROGRAM); 845 nand_address_column(self, offset, chip->nc_page_size); 846 nand_command(self, ONFI_PAGE_PROGRAM_START); 847 848 nand_busy(self); 849 850 if (chip->nc_flags & NC_BUSWIDTH_16) 851 nand_write_buf_2(self, oob, chip->nc_spare_size); 852 else 853 nand_write_buf_1(self, oob, chip->nc_spare_size); 854 855 status = nand_get_status(self); 856 KASSERT(status & ONFI_STATUS_RDY); 857 if (status & ONFI_STATUS_FAIL) 858 return EIO; 859 else 860 return 0; 861 } 862 863 void 864 nand_markbad(device_t self, size_t offset) 865 { 866 struct nand_softc *sc = device_private(self); 867 struct nand_chip *chip = &sc->sc_chip; 868 flash_off_t blockoffset; 869 #ifdef NAND_BBT 870 flash_off_t block; 871 872 block = offset / chip->nc_block_size; 873 874 nand_bbt_block_markbad(self, block); 875 #endif 876 blockoffset = offset & chip->nc_block_mask; 877 878 /* check if it is already marked bad */ 879 if (nand_isbad(self, blockoffset)) 880 return; 881 882 nand_read_oob(self, blockoffset, chip->nc_oob_cache); 883 884 chip->nc_oob_cache[chip->nc_badmarker_offs] = 0x00; 885 chip->nc_oob_cache[chip->nc_badmarker_offs + 1] = 0x00; 886 887 nand_write_oob(self, blockoffset, chip->nc_oob_cache); 888 } 889 890 bool 891 nand_isfactorybad(device_t self, flash_off_t offset) 892 { 893 struct nand_softc *sc = device_private(self); 894 struct nand_chip *chip = &sc->sc_chip; 895 flash_off_t block, first_page, last_page, page; 896 int i; 897 898 /* Check for factory bad blocks first 899 * Factory bad blocks are marked in the first or last 900 * page of the blocks, see: ONFI 2.2, 3.2.2. 901 */ 902 block = offset / chip->nc_block_size; 903 first_page = block * chip->nc_block_size; 904 last_page = (block + 1) * chip->nc_block_size 905 - chip->nc_page_size; 906 907 for (i = 0, page = first_page; i < 2; i++, page = last_page) { 908 /* address OOB */ 909 nand_prepare_read(self, page, chip->nc_page_size); 910 911 if (chip->nc_flags & NC_BUSWIDTH_16) { 912 uint16_t word; 913 nand_read_2(self, &word); 914 if (word == 0x0000) 915 return true; 916 } else { 917 uint8_t byte; 918 nand_read_1(self, &byte); 919 if (byte == 0x00) 920 return true; 921 } 922 } 923 924 return false; 925 } 926 927 bool 928 nand_iswornoutbad(device_t self, flash_off_t offset) 929 { 930 struct nand_softc *sc = device_private(self); 931 struct nand_chip *chip = &sc->sc_chip; 932 flash_off_t block; 933 934 /* we inspect the first page of the block */ 935 block = offset & chip->nc_block_mask; 936 937 /* Linux/u-boot compatible badblock handling */ 938 if (chip->nc_flags & NC_BUSWIDTH_16) { 939 uint16_t word, mark; 940 941 nand_prepare_read(self, block, 942 chip->nc_page_size + (chip->nc_badmarker_offs & 0xfe)); 943 944 nand_read_2(self, &word); 945 mark = htole16(word); 946 if (chip->nc_badmarker_offs & 0x01) 947 mark >>= 8; 948 if ((mark & 0xff) != 0xff) 949 return true; 950 } else { 951 uint8_t byte; 952 953 nand_prepare_read(self, block, 954 chip->nc_page_size + chip->nc_badmarker_offs); 955 956 nand_read_1(self, &byte); 957 if (byte != 0xff) 958 return true; 959 } 960 961 return false; 962 } 963 964 bool 965 nand_isbad(device_t self, flash_off_t offset) 966 { 967 #ifdef NAND_BBT 968 struct nand_softc *sc = device_private(self); 969 struct nand_chip *chip = &sc->sc_chip; 970 flash_off_t block; 971 972 block = offset / chip->nc_block_size; 973 974 return nand_bbt_block_isbad(self, block); 975 #else 976 /* ONFI host requirement */ 977 if (nand_isfactorybad(self, offset)) 978 return true; 979 980 /* Look for Linux/U-Boot compatible bad marker */ 981 if (nand_iswornoutbad(self, offset)) 982 return true; 983 984 return false; 985 #endif 986 } 987 988 int 989 nand_erase_block(device_t self, size_t offset) 990 { 991 uint8_t status; 992 993 /* xxx calculate first page of block for address? */ 994 995 nand_command(self, ONFI_BLOCK_ERASE); 996 nand_address_row(self, offset); 997 nand_command(self, ONFI_BLOCK_ERASE_START); 998 999 nand_busy(self); 1000 1001 status = nand_get_status(self); 1002 KASSERT(status & ONFI_STATUS_RDY); 1003 if (status & ONFI_STATUS_FAIL) { 1004 aprint_error_dev(self, "block erase failed!\n"); 1005 nand_markbad(self, offset); 1006 return EIO; 1007 } else { 1008 return 0; 1009 } 1010 } 1011 1012 /* default functions for driver development */ 1013 1014 /* default ECC using hamming code of 256 byte chunks */ 1015 int 1016 nand_default_ecc_compute(device_t self, const uint8_t *data, uint8_t *code) 1017 { 1018 hamming_compute_256(data, code); 1019 1020 return 0; 1021 } 1022 1023 int 1024 nand_default_ecc_correct(device_t self, uint8_t *data, const uint8_t *origcode, 1025 const uint8_t *compcode) 1026 { 1027 return hamming_correct_256(data, origcode, compcode); 1028 } 1029 1030 void 1031 nand_default_select(device_t self, bool enable) 1032 { 1033 /* do nothing */ 1034 return; 1035 } 1036 1037 /* implementation of the block device API */ 1038 1039 int 1040 nand_flash_submit(device_t self, struct buf * const bp) 1041 { 1042 struct nand_softc *sc = device_private(self); 1043 1044 return flash_io_submit(&sc->sc_flash_io, bp); 1045 } 1046 1047 /* 1048 * handle (page) unaligned write to nand 1049 */ 1050 static int 1051 nand_flash_write_unaligned(device_t self, flash_off_t offset, size_t len, 1052 size_t *retlen, const uint8_t *buf) 1053 { 1054 struct nand_softc *sc = device_private(self); 1055 struct nand_chip *chip = &sc->sc_chip; 1056 flash_off_t first, last, firstoff; 1057 const uint8_t *bufp; 1058 flash_off_t addr; 1059 size_t left, count; 1060 int error = 0, i; 1061 1062 first = offset & chip->nc_page_mask; 1063 firstoff = offset & ~chip->nc_page_mask; 1064 /* XXX check if this should be len - 1 */ 1065 last = (offset + len) & chip->nc_page_mask; 1066 count = last - first + 1; 1067 1068 addr = first; 1069 *retlen = 0; 1070 1071 mutex_enter(&sc->sc_device_lock); 1072 if (count == 1) { 1073 if (nand_isbad(self, addr)) { 1074 aprint_error_dev(self, 1075 "nand_flash_write_unaligned: " 1076 "bad block encountered\n"); 1077 error = EIO; 1078 goto out; 1079 } 1080 1081 error = nand_read_page(self, addr, chip->nc_page_cache); 1082 if (error) { 1083 goto out; 1084 } 1085 1086 memcpy(chip->nc_page_cache + firstoff, buf, len); 1087 1088 error = nand_program_page(self, addr, chip->nc_page_cache); 1089 if (error) { 1090 goto out; 1091 } 1092 1093 *retlen = len; 1094 goto out; 1095 } 1096 1097 bufp = buf; 1098 left = len; 1099 1100 for (i = 0; i < count && left != 0; i++) { 1101 if (nand_isbad(self, addr)) { 1102 aprint_error_dev(self, 1103 "nand_flash_write_unaligned: " 1104 "bad block encountered\n"); 1105 error = EIO; 1106 goto out; 1107 } 1108 1109 if (i == 0) { 1110 error = nand_read_page(self, 1111 addr, chip->nc_page_cache); 1112 if (error) { 1113 goto out; 1114 } 1115 1116 memcpy(chip->nc_page_cache + firstoff, 1117 bufp, chip->nc_page_size - firstoff); 1118 1119 printf("program page: %s: %d\n", __FILE__, __LINE__); 1120 error = nand_program_page(self, 1121 addr, chip->nc_page_cache); 1122 if (error) { 1123 goto out; 1124 } 1125 1126 bufp += chip->nc_page_size - firstoff; 1127 left -= chip->nc_page_size - firstoff; 1128 *retlen += chip->nc_page_size - firstoff; 1129 1130 } else if (i == count - 1) { 1131 error = nand_read_page(self, 1132 addr, chip->nc_page_cache); 1133 if (error) { 1134 goto out; 1135 } 1136 1137 memcpy(chip->nc_page_cache, bufp, left); 1138 1139 error = nand_program_page(self, 1140 addr, chip->nc_page_cache); 1141 if (error) { 1142 goto out; 1143 } 1144 1145 *retlen += left; 1146 KASSERT(left < chip->nc_page_size); 1147 1148 } else { 1149 /* XXX debug */ 1150 if (left > chip->nc_page_size) { 1151 printf("left: %zu, i: %d, count: %zu\n", 1152 left, i, count); 1153 } 1154 KASSERT(left > chip->nc_page_size); 1155 1156 error = nand_program_page(self, addr, bufp); 1157 if (error) { 1158 goto out; 1159 } 1160 1161 bufp += chip->nc_page_size; 1162 left -= chip->nc_page_size; 1163 *retlen += chip->nc_page_size; 1164 } 1165 1166 addr += chip->nc_page_size; 1167 } 1168 1169 KASSERT(*retlen == len); 1170 out: 1171 mutex_exit(&sc->sc_device_lock); 1172 1173 return error; 1174 } 1175 1176 int 1177 nand_flash_write(device_t self, flash_off_t offset, size_t len, size_t *retlen, 1178 const uint8_t *buf) 1179 { 1180 struct nand_softc *sc = device_private(self); 1181 struct nand_chip *chip = &sc->sc_chip; 1182 const uint8_t *bufp; 1183 size_t pages, page; 1184 daddr_t addr; 1185 int error = 0; 1186 1187 if ((offset + len) > chip->nc_size) { 1188 DPRINTF(("nand_flash_write: write (off: 0x%jx, len: %ju)," 1189 " is over device size (0x%jx)\n", 1190 (uintmax_t)offset, (uintmax_t)len, 1191 (uintmax_t)chip->nc_size)); 1192 return EINVAL; 1193 } 1194 1195 if (len % chip->nc_page_size != 0 || 1196 offset % chip->nc_page_size != 0) { 1197 return nand_flash_write_unaligned(self, 1198 offset, len, retlen, buf); 1199 } 1200 1201 pages = len / chip->nc_page_size; 1202 KASSERT(pages != 0); 1203 *retlen = 0; 1204 1205 addr = offset; 1206 bufp = buf; 1207 1208 mutex_enter(&sc->sc_device_lock); 1209 for (page = 0; page < pages; page++) { 1210 /* do we need this check here? */ 1211 if (nand_isbad(self, addr)) { 1212 aprint_error_dev(self, 1213 "nand_flash_write: bad block encountered\n"); 1214 1215 error = EIO; 1216 goto out; 1217 } 1218 1219 error = nand_program_page(self, addr, bufp); 1220 if (error) { 1221 goto out; 1222 } 1223 1224 addr += chip->nc_page_size; 1225 bufp += chip->nc_page_size; 1226 *retlen += chip->nc_page_size; 1227 } 1228 out: 1229 mutex_exit(&sc->sc_device_lock); 1230 DPRINTF(("page programming: retlen: %" PRIu32 ", len: %" PRIu32 "\n", *retlen, len)); 1231 1232 return error; 1233 } 1234 1235 /* 1236 * handle (page) unaligned read from nand 1237 */ 1238 static int 1239 nand_flash_read_unaligned(device_t self, size_t offset, 1240 size_t len, size_t *retlen, uint8_t *buf) 1241 { 1242 struct nand_softc *sc = device_private(self); 1243 struct nand_chip *chip = &sc->sc_chip; 1244 daddr_t first, last, count, firstoff; 1245 uint8_t *bufp; 1246 daddr_t addr; 1247 size_t left; 1248 int error = 0, i; 1249 1250 first = offset & chip->nc_page_mask; 1251 firstoff = offset & ~chip->nc_page_mask; 1252 last = (offset + len) & chip->nc_page_mask; 1253 count = (last - first) / chip->nc_page_size + 1; 1254 1255 addr = first; 1256 bufp = buf; 1257 left = len; 1258 *retlen = 0; 1259 1260 mutex_enter(&sc->sc_device_lock); 1261 if (count == 1) { 1262 error = nand_read_page(self, addr, chip->nc_page_cache); 1263 if (error) { 1264 goto out; 1265 } 1266 1267 memcpy(bufp, chip->nc_page_cache + firstoff, len); 1268 1269 *retlen = len; 1270 goto out; 1271 } 1272 1273 for (i = 0; i < count && left != 0; i++) { 1274 error = nand_read_page(self, addr, chip->nc_page_cache); 1275 if (error) { 1276 goto out; 1277 } 1278 1279 if (i == 0) { 1280 memcpy(bufp, chip->nc_page_cache + firstoff, 1281 chip->nc_page_size - firstoff); 1282 1283 bufp += chip->nc_page_size - firstoff; 1284 left -= chip->nc_page_size - firstoff; 1285 *retlen += chip->nc_page_size - firstoff; 1286 1287 } else if (i == count - 1) { 1288 memcpy(bufp, chip->nc_page_cache, left); 1289 *retlen += left; 1290 KASSERT(left < chip->nc_page_size); 1291 1292 } else { 1293 memcpy(bufp, chip->nc_page_cache, chip->nc_page_size); 1294 1295 bufp += chip->nc_page_size; 1296 left -= chip->nc_page_size; 1297 *retlen += chip->nc_page_size; 1298 } 1299 1300 addr += chip->nc_page_size; 1301 } 1302 KASSERT(*retlen == len); 1303 out: 1304 mutex_exit(&sc->sc_device_lock); 1305 1306 return error; 1307 } 1308 1309 int 1310 nand_flash_read(device_t self, flash_off_t offset, size_t len, size_t *retlen, 1311 uint8_t *buf) 1312 { 1313 struct nand_softc *sc = device_private(self); 1314 struct nand_chip *chip = &sc->sc_chip; 1315 uint8_t *bufp; 1316 size_t addr; 1317 size_t i, pages; 1318 int error = 0; 1319 1320 *retlen = 0; 1321 1322 DPRINTF(("nand_flash_read: off: 0x%jx, len: %" PRIu32 "\n", 1323 (uintmax_t)offset, len)); 1324 1325 if (__predict_false((offset + len) > chip->nc_size)) { 1326 DPRINTF(("nand_flash_read: read (off: 0x%jx, len: %" PRIu32 ")," 1327 " is over device size (%ju)\n", (uintmax_t)offset, 1328 len, (uintmax_t)chip->nc_size)); 1329 return EINVAL; 1330 } 1331 1332 /* Handle unaligned access, shouldnt be needed when using the 1333 * block device, as strategy handles it, so only low level 1334 * accesses will use this path 1335 */ 1336 /* XXX^2 */ 1337 #if 0 1338 if (len < chip->nc_page_size) 1339 panic("TODO page size is larger than read size"); 1340 #endif 1341 1342 if (len % chip->nc_page_size != 0 || 1343 offset % chip->nc_page_size != 0) { 1344 return nand_flash_read_unaligned(self, 1345 offset, len, retlen, buf); 1346 } 1347 1348 bufp = buf; 1349 addr = offset; 1350 pages = len / chip->nc_page_size; 1351 1352 mutex_enter(&sc->sc_device_lock); 1353 for (i = 0; i < pages; i++) { 1354 /* XXX do we need this check here? */ 1355 if (nand_isbad(self, addr)) { 1356 aprint_error_dev(self, "bad block encountered\n"); 1357 error = EIO; 1358 goto out; 1359 } 1360 error = nand_read_page(self, addr, bufp); 1361 if (error) 1362 goto out; 1363 1364 bufp += chip->nc_page_size; 1365 addr += chip->nc_page_size; 1366 *retlen += chip->nc_page_size; 1367 } 1368 out: 1369 mutex_exit(&sc->sc_device_lock); 1370 1371 return error; 1372 } 1373 1374 int 1375 nand_flash_isbad(device_t self, flash_off_t ofs, bool *is_bad) 1376 { 1377 struct nand_softc *sc = device_private(self); 1378 struct nand_chip *chip = &sc->sc_chip; 1379 bool result; 1380 1381 if (ofs > chip->nc_size) { 1382 DPRINTF(("nand_flash_isbad: offset 0x%jx is larger than" 1383 " device size (0x%jx)\n", (uintmax_t)ofs, 1384 (uintmax_t)chip->nc_size)); 1385 return EINVAL; 1386 } 1387 1388 if (ofs % chip->nc_block_size != 0) { 1389 DPRINTF(("offset (0x%jx) is not a multiple of block size " 1390 "(%ju)", 1391 (uintmax_t)ofs, (uintmax_t)chip->nc_block_size)); 1392 return EINVAL; 1393 } 1394 1395 mutex_enter(&sc->sc_device_lock); 1396 result = nand_isbad(self, ofs); 1397 mutex_exit(&sc->sc_device_lock); 1398 1399 *is_bad = result; 1400 1401 return 0; 1402 } 1403 1404 int 1405 nand_flash_markbad(device_t self, flash_off_t ofs) 1406 { 1407 struct nand_softc *sc = device_private(self); 1408 struct nand_chip *chip = &sc->sc_chip; 1409 1410 if (ofs > chip->nc_size) { 1411 DPRINTF(("nand_flash_markbad: offset 0x%jx is larger than" 1412 " device size (0x%jx)\n", ofs, 1413 (uintmax_t)chip->nc_size)); 1414 return EINVAL; 1415 } 1416 1417 if (ofs % chip->nc_block_size != 0) { 1418 panic("offset (%ju) is not a multiple of block size (%ju)", 1419 (uintmax_t)ofs, (uintmax_t)chip->nc_block_size); 1420 } 1421 1422 mutex_enter(&sc->sc_device_lock); 1423 nand_markbad(self, ofs); 1424 mutex_exit(&sc->sc_device_lock); 1425 1426 return 0; 1427 } 1428 1429 int 1430 nand_flash_erase(device_t self, 1431 struct flash_erase_instruction *ei) 1432 { 1433 struct nand_softc *sc = device_private(self); 1434 struct nand_chip *chip = &sc->sc_chip; 1435 flash_off_t addr; 1436 int error = 0; 1437 1438 if (ei->ei_addr < 0 || ei->ei_len < chip->nc_block_size) 1439 return EINVAL; 1440 1441 if (ei->ei_addr + ei->ei_len > chip->nc_size) { 1442 DPRINTF(("nand_flash_erase: erase address is over the end" 1443 " of the device\n")); 1444 return EINVAL; 1445 } 1446 1447 if (ei->ei_addr % chip->nc_block_size != 0) { 1448 aprint_error_dev(self, 1449 "nand_flash_erase: ei_addr (%ju) is not" 1450 " a multiple of block size (%ju)", 1451 (uintmax_t)ei->ei_addr, 1452 (uintmax_t)chip->nc_block_size); 1453 return EINVAL; 1454 } 1455 1456 if (ei->ei_len % chip->nc_block_size != 0) { 1457 aprint_error_dev(self, 1458 "nand_flash_erase: ei_len (%ju) is not" 1459 " a multiple of block size (%ju)", 1460 (uintmax_t)ei->ei_len, 1461 (uintmax_t)chip->nc_block_size); 1462 return EINVAL; 1463 } 1464 1465 mutex_enter(&sc->sc_device_lock); 1466 addr = ei->ei_addr; 1467 while (addr < ei->ei_addr + ei->ei_len) { 1468 if (nand_isbad(self, addr)) { 1469 aprint_error_dev(self, "bad block encountered\n"); 1470 ei->ei_state = FLASH_ERASE_FAILED; 1471 error = EIO; 1472 goto out; 1473 } 1474 1475 error = nand_erase_block(self, addr); 1476 if (error) { 1477 ei->ei_state = FLASH_ERASE_FAILED; 1478 goto out; 1479 } 1480 1481 addr += chip->nc_block_size; 1482 } 1483 mutex_exit(&sc->sc_device_lock); 1484 1485 ei->ei_state = FLASH_ERASE_DONE; 1486 if (ei->ei_callback != NULL) { 1487 ei->ei_callback(ei); 1488 } 1489 1490 return 0; 1491 out: 1492 mutex_exit(&sc->sc_device_lock); 1493 1494 return error; 1495 } 1496 1497 MODULE(MODULE_CLASS_DRIVER, nand, "flash"); 1498 1499 #ifdef _MODULE 1500 #include "ioconf.c" 1501 #endif 1502 1503 static int 1504 nand_modcmd(modcmd_t cmd, void *opaque) 1505 { 1506 switch (cmd) { 1507 case MODULE_CMD_INIT: 1508 #ifdef _MODULE 1509 return config_init_component(cfdriver_ioconf_nand, 1510 cfattach_ioconf_nand, cfdata_ioconf_nand); 1511 #else 1512 return 0; 1513 #endif 1514 case MODULE_CMD_FINI: 1515 #ifdef _MODULE 1516 return config_fini_component(cfdriver_ioconf_nand, 1517 cfattach_ioconf_nand, cfdata_ioconf_nand); 1518 #else 1519 return 0; 1520 #endif 1521 default: 1522 return ENOTTY; 1523 } 1524 } 1525