1 /* $NetBSD: nand.c,v 1.20 2012/11/02 19:50:22 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Department of Software Engineering, 5 * University of Szeged, Hungary 6 * Copyright (c) 2010 Adam Hoka <ahoka@NetBSD.org> 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by the Department of Software Engineering, University of Szeged, Hungary 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Common driver for NAND chips implementing the ONFI 2.2 specification */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: nand.c,v 1.20 2012/11/02 19:50:22 pgoyette Exp $"); 38 39 #include "locators.h" 40 41 #include <sys/param.h> 42 #include <sys/types.h> 43 #include <sys/device.h> 44 #include <sys/kmem.h> 45 #include <sys/atomic.h> 46 47 #include <dev/flash/flash.h> 48 #include <dev/flash/flash_io.h> 49 #include <dev/nand/nand.h> 50 #include <dev/nand/onfi.h> 51 #include <dev/nand/hamming.h> 52 #include <dev/nand/nand_bbt.h> 53 #include <dev/nand/nand_crc.h> 54 55 #include "opt_nand.h" 56 57 int nand_match(device_t, cfdata_t, void *); 58 void nand_attach(device_t, device_t, void *); 59 int nand_detach(device_t, int); 60 bool nand_shutdown(device_t, int); 61 62 int nand_print(void *, const char *); 63 64 static int nand_search(device_t, cfdata_t, const int *, void *); 65 static void nand_address_row(device_t, size_t); 66 static void nand_address_column(device_t, size_t, size_t); 67 static int nand_fill_chip_structure(device_t, struct nand_chip *); 68 static int nand_scan_media(device_t, struct nand_chip *); 69 static bool nand_check_wp(device_t); 70 71 CFATTACH_DECL_NEW(nand, sizeof(struct nand_softc), 72 nand_match, nand_attach, nand_detach, NULL); 73 74 #ifdef NAND_DEBUG 75 int nanddebug = NAND_DEBUG; 76 #endif 77 78 struct flash_interface nand_flash_if = { 79 .type = FLASH_TYPE_NAND, 80 81 .read = nand_flash_read, 82 .write = nand_flash_write, 83 .erase = nand_flash_erase, 84 .block_isbad = nand_flash_isbad, 85 .block_markbad = nand_flash_markbad, 86 87 .submit = nand_flash_submit 88 }; 89 90 #ifdef NAND_VERBOSE 91 const struct nand_manufacturer nand_mfrs[] = { 92 { NAND_MFR_AMD, "AMD" }, 93 { NAND_MFR_FUJITSU, "Fujitsu" }, 94 { NAND_MFR_RENESAS, "Renesas" }, 95 { NAND_MFR_STMICRO, "ST Micro" }, 96 { NAND_MFR_MICRON, "Micron" }, 97 { NAND_MFR_NATIONAL, "National" }, 98 { NAND_MFR_TOSHIBA, "Toshiba" }, 99 { NAND_MFR_HYNIX, "Hynix" }, 100 { NAND_MFR_SAMSUNG, "Samsung" }, 101 { NAND_MFR_UNKNOWN, "Unknown" } 102 }; 103 104 static const char * 105 nand_midtoname(int id) 106 { 107 int i; 108 109 for (i = 0; nand_mfrs[i].id != 0; i++) { 110 if (nand_mfrs[i].id == id) 111 return nand_mfrs[i].name; 112 } 113 114 KASSERT(nand_mfrs[i].id == 0); 115 116 return nand_mfrs[i].name; 117 } 118 #endif 119 120 /* ARGSUSED */ 121 int 122 nand_match(device_t parent, cfdata_t match, void *aux) 123 { 124 /* pseudo device, always attaches */ 125 return 1; 126 } 127 128 void 129 nand_attach(device_t parent, device_t self, void *aux) 130 { 131 struct nand_softc *sc = device_private(self); 132 struct nand_attach_args *naa = aux; 133 struct nand_chip *chip = &sc->sc_chip; 134 135 sc->sc_dev = self; 136 sc->controller_dev = parent; 137 sc->nand_if = naa->naa_nand_if; 138 139 aprint_naive("\n"); 140 141 if (nand_check_wp(self)) { 142 aprint_error("NAND chip is write protected!\n"); 143 return; 144 } 145 146 if (nand_scan_media(self, chip)) { 147 return; 148 } 149 150 nand_flash_if.erasesize = chip->nc_block_size; 151 nand_flash_if.page_size = chip->nc_page_size; 152 nand_flash_if.writesize = chip->nc_page_size; 153 154 /* allocate cache */ 155 chip->nc_oob_cache = kmem_alloc(chip->nc_spare_size, KM_SLEEP); 156 chip->nc_page_cache = kmem_alloc(chip->nc_page_size, KM_SLEEP); 157 158 mutex_init(&sc->sc_device_lock, MUTEX_DEFAULT, IPL_NONE); 159 160 if (flash_sync_thread_init(&sc->sc_flash_io, self, &nand_flash_if)) { 161 goto error; 162 } 163 164 if (!pmf_device_register1(sc->sc_dev, NULL, NULL, nand_shutdown)) 165 aprint_error_dev(sc->sc_dev, 166 "couldn't establish power handler\n"); 167 168 #ifdef NAND_BBT 169 nand_bbt_init(self); 170 nand_bbt_scan(self); 171 #endif 172 173 /* 174 * Attach all our devices 175 */ 176 config_search_ia(nand_search, self, NULL, NULL); 177 178 return; 179 error: 180 kmem_free(chip->nc_oob_cache, chip->nc_spare_size); 181 kmem_free(chip->nc_page_cache, chip->nc_page_size); 182 mutex_destroy(&sc->sc_device_lock); 183 } 184 185 static int 186 nand_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 187 { 188 struct nand_softc *sc = device_private(parent); 189 struct nand_chip *chip = &sc->sc_chip; 190 struct flash_attach_args faa; 191 192 faa.flash_if = &nand_flash_if; 193 194 faa.partinfo.part_offset = cf->cf_loc[FLASHBUSCF_OFFSET]; 195 196 if (cf->cf_loc[FLASHBUSCF_SIZE] == 0) { 197 faa.partinfo.part_size = chip->nc_size - 198 faa.partinfo.part_offset; 199 } else { 200 faa.partinfo.part_size = cf->cf_loc[FLASHBUSCF_SIZE]; 201 } 202 203 if (cf->cf_loc[FLASHBUSCF_READONLY]) 204 faa.partinfo.part_flags = FLASH_PART_READONLY; 205 else 206 faa.partinfo.part_flags = 0; 207 208 if (config_match(parent, cf, &faa)) { 209 if (config_attach(parent, cf, &faa, nand_print) != NULL) { 210 return 0; 211 } else { 212 return 1; 213 } 214 } 215 216 return 1; 217 } 218 219 int 220 nand_detach(device_t self, int flags) 221 { 222 struct nand_softc *sc = device_private(self); 223 struct nand_chip *chip = &sc->sc_chip; 224 int error = 0; 225 226 error = config_detach_children(self, flags); 227 if (error) { 228 return error; 229 } 230 231 flash_sync_thread_destroy(&sc->sc_flash_io); 232 #ifdef NAND_BBT 233 nand_bbt_detach(self); 234 #endif 235 /* free oob cache */ 236 kmem_free(chip->nc_oob_cache, chip->nc_spare_size); 237 kmem_free(chip->nc_page_cache, chip->nc_page_size); 238 kmem_free(chip->nc_ecc_cache, chip->nc_ecc->necc_size); 239 240 mutex_destroy(&sc->sc_device_lock); 241 242 pmf_device_deregister(sc->sc_dev); 243 244 return error; 245 } 246 247 int 248 nand_print(void *aux, const char *pnp) 249 { 250 if (pnp != NULL) 251 aprint_normal("nand at %s\n", pnp); 252 253 return UNCONF; 254 } 255 256 /* ask for a nand driver to attach to the controller */ 257 device_t 258 nand_attach_mi(struct nand_interface *nand_if, device_t parent) 259 { 260 struct nand_attach_args arg; 261 262 KASSERT(nand_if != NULL); 263 264 /* fill the defaults if we have null pointers */ 265 if (nand_if->program_page == NULL) { 266 nand_if->program_page = &nand_default_program_page; 267 } 268 269 if (nand_if->read_page == NULL) { 270 nand_if->read_page = &nand_default_read_page; 271 } 272 273 arg.naa_nand_if = nand_if; 274 return config_found_ia(parent, "nandbus", &arg, nand_print); 275 } 276 277 /* default everything to reasonable values, to ease future api changes */ 278 void 279 nand_init_interface(struct nand_interface *interface) 280 { 281 interface->select = &nand_default_select; 282 interface->command = NULL; 283 interface->address = NULL; 284 interface->read_buf_1 = NULL; 285 interface->read_buf_2 = NULL; 286 interface->read_1 = NULL; 287 interface->read_2 = NULL; 288 interface->write_buf_1 = NULL; 289 interface->write_buf_2 = NULL; 290 interface->write_1 = NULL; 291 interface->write_2 = NULL; 292 interface->busy = NULL; 293 294 /*- 295 * most drivers dont want to change this, but some implement 296 * read/program in one step 297 */ 298 interface->program_page = &nand_default_program_page; 299 interface->read_page = &nand_default_read_page; 300 301 /* default to soft ecc, that should work everywhere */ 302 interface->ecc_compute = &nand_default_ecc_compute; 303 interface->ecc_correct = &nand_default_ecc_correct; 304 interface->ecc_prepare = NULL; 305 interface->ecc.necc_code_size = 3; 306 interface->ecc.necc_block_size = 256; 307 interface->ecc.necc_type = NAND_ECC_TYPE_SW; 308 } 309 310 #if 0 311 /* handle quirks here */ 312 static void 313 nand_quirks(device_t self, struct nand_chip *chip) 314 { 315 /* this is an example only! */ 316 switch (chip->nc_manf_id) { 317 case NAND_MFR_SAMSUNG: 318 if (chip->nc_dev_id == 0x00) { 319 /* do something only samsung chips need */ 320 /* or */ 321 /* chip->nc_quirks |= NC_QUIRK_NO_READ_START */ 322 } 323 } 324 325 return; 326 } 327 #endif 328 329 static int 330 nand_fill_chip_structure_legacy(device_t self, struct nand_chip *chip) 331 { 332 switch (chip->nc_manf_id) { 333 case NAND_MFR_MICRON: 334 return nand_read_parameters_micron(self, chip); 335 case NAND_MFR_SAMSUNG: 336 return nand_read_parameters_samsung(self, chip); 337 default: 338 return 1; 339 } 340 341 return 0; 342 } 343 344 /** 345 * scan media to determine the chip's properties 346 * this function resets the device 347 */ 348 static int 349 nand_scan_media(device_t self, struct nand_chip *chip) 350 { 351 struct nand_softc *sc = device_private(self); 352 struct nand_ecc *ecc; 353 uint8_t onfi_signature[4]; 354 355 nand_select(self, true); 356 nand_command(self, ONFI_RESET); 357 nand_select(self, false); 358 359 /* check if the device implements the ONFI standard */ 360 nand_select(self, true); 361 nand_command(self, ONFI_READ_ID); 362 nand_address(self, 0x20); 363 nand_read_1(self, &onfi_signature[0]); 364 nand_read_1(self, &onfi_signature[1]); 365 nand_read_1(self, &onfi_signature[2]); 366 nand_read_1(self, &onfi_signature[3]); 367 nand_select(self, false); 368 369 if (onfi_signature[0] != 'O' || onfi_signature[1] != 'N' || 370 onfi_signature[2] != 'F' || onfi_signature[3] != 'I') { 371 chip->nc_isonfi = false; 372 373 aprint_normal(": Legacy NAND Flash\n"); 374 375 nand_read_id(self, &chip->nc_manf_id, &chip->nc_dev_id); 376 377 if (nand_fill_chip_structure_legacy(self, chip)) { 378 aprint_error_dev(self, 379 "can't read device parameters for legacy chip\n"); 380 return 1; 381 } 382 } else { 383 chip->nc_isonfi = true; 384 385 aprint_normal(": ONFI NAND Flash\n"); 386 387 nand_read_id(self, &chip->nc_manf_id, &chip->nc_dev_id); 388 389 if (nand_fill_chip_structure(self, chip)) { 390 aprint_error_dev(self, 391 "can't read device parameters\n"); 392 return 1; 393 } 394 } 395 396 #ifdef NAND_VERBOSE 397 aprint_normal_dev(self, 398 "manufacturer id: 0x%.2x (%s), device id: 0x%.2x\n", 399 chip->nc_manf_id, 400 nand_midtoname(chip->nc_manf_id), 401 chip->nc_dev_id); 402 #endif 403 404 aprint_normal_dev(self, 405 "page size: %" PRIu32 " bytes, spare size: %" PRIu32 " bytes, " 406 "block size: %" PRIu32 " bytes\n", 407 chip->nc_page_size, chip->nc_spare_size, chip->nc_block_size); 408 409 aprint_normal_dev(self, 410 "LUN size: %" PRIu32 " blocks, LUNs: %" PRIu8 411 ", total storage size: %" PRIu64 " MB\n", 412 chip->nc_lun_blocks, chip->nc_num_luns, 413 chip->nc_size / 1024 / 1024); 414 415 #ifdef NAND_VERBOSE 416 aprint_normal_dev(self, "column cycles: %" PRIu8 ", row cycles: %" 417 PRIu8 "\n", 418 chip->nc_addr_cycles_column, chip->nc_addr_cycles_row); 419 #endif 420 421 ecc = chip->nc_ecc = &sc->nand_if->ecc; 422 423 /* 424 * calculate the place of ecc data in oob 425 * we try to be compatible with Linux here 426 */ 427 switch (chip->nc_spare_size) { 428 case 8: 429 ecc->necc_offset = 0; 430 break; 431 case 16: 432 ecc->necc_offset = 0; 433 break; 434 case 32: 435 ecc->necc_offset = 0; 436 break; 437 case 64: 438 ecc->necc_offset = 40; 439 break; 440 case 128: 441 ecc->necc_offset = 80; 442 break; 443 default: 444 panic("OOB size %" PRIu32 " is unexpected", chip->nc_spare_size); 445 } 446 447 ecc->necc_steps = chip->nc_page_size / ecc->necc_block_size; 448 ecc->necc_size = ecc->necc_steps * ecc->necc_code_size; 449 450 /* check if we fit in oob */ 451 if (ecc->necc_offset + ecc->necc_size > chip->nc_spare_size) { 452 panic("NAND ECC bits dont fit in OOB"); 453 } 454 455 /* TODO: mark free oob area available for file systems */ 456 457 chip->nc_ecc_cache = kmem_zalloc(ecc->necc_size, KM_SLEEP); 458 459 /* 460 * calculate badblock marker offset in oob 461 * we try to be compatible with linux here 462 */ 463 if (chip->nc_page_size > 512) 464 chip->nc_badmarker_offs = 0; 465 else 466 chip->nc_badmarker_offs = 5; 467 468 /* Calculate page shift and mask */ 469 chip->nc_page_shift = ffs(chip->nc_page_size) - 1; 470 chip->nc_page_mask = ~(chip->nc_page_size - 1); 471 /* same for block */ 472 chip->nc_block_shift = ffs(chip->nc_block_size) - 1; 473 chip->nc_block_mask = ~(chip->nc_block_size - 1); 474 475 /* look for quirks here if needed in future */ 476 /* nand_quirks(self, chip); */ 477 478 return 0; 479 } 480 481 void 482 nand_read_id(device_t self, uint8_t *manf, uint8_t *dev) 483 { 484 nand_select(self, true); 485 nand_command(self, ONFI_READ_ID); 486 nand_address(self, 0x00); 487 488 nand_read_1(self, manf); 489 nand_read_1(self, dev); 490 491 nand_select(self, false); 492 } 493 494 int 495 nand_read_parameter_page(device_t self, struct onfi_parameter_page *params) 496 { 497 uint8_t *bufp; 498 uint16_t crc; 499 int i;//, tries = 0; 500 501 KASSERT(sizeof(*params) == 256); 502 503 //read_params: 504 // tries++; 505 506 nand_select(self, true); 507 nand_command(self, ONFI_READ_PARAMETER_PAGE); 508 nand_address(self, 0x00); 509 510 nand_busy(self); 511 512 /* TODO check the signature if it contains at least 2 letters */ 513 514 bufp = (uint8_t *)params; 515 /* XXX why i am not using read_buf? */ 516 for (i = 0; i < 256; i++) { 517 nand_read_1(self, &bufp[i]); 518 } 519 nand_select(self, false); 520 521 /* validate the parameter page with the crc */ 522 crc = nand_crc16(bufp, 254); 523 524 if (crc != params->param_integrity_crc) { 525 aprint_error_dev(self, "parameter page crc check failed\n"); 526 /* TODO: we should read the next parameter page copy */ 527 return 1; 528 } 529 530 return 0; 531 } 532 533 static int 534 nand_fill_chip_structure(device_t self, struct nand_chip *chip) 535 { 536 struct onfi_parameter_page params; 537 uint8_t vendor[13], model[21]; 538 int i; 539 540 if (nand_read_parameter_page(self, ¶ms)) { 541 return 1; 542 } 543 544 /* strip manufacturer and model string */ 545 strlcpy(vendor, params.param_manufacturer, sizeof(vendor)); 546 for (i = 11; i > 0 && vendor[i] == ' '; i--) 547 vendor[i] = 0; 548 strlcpy(model, params.param_model, sizeof(model)); 549 for (i = 19; i > 0 && model[i] == ' '; i--) 550 model[i] = 0; 551 552 aprint_normal_dev(self, "vendor: %s, model: %s\n", vendor, model); 553 554 /* XXX TODO multiple LUNs */ 555 if (params.param_numluns != 1) { 556 aprint_error_dev(self, 557 "more than one LUNs are not supported yet!\n"); 558 559 return 1; 560 } 561 562 chip->nc_size = params.param_pagesize * params.param_blocksize * 563 params.param_lunsize * params.param_numluns; 564 565 chip->nc_page_size = params.param_pagesize; 566 chip->nc_block_pages = params.param_blocksize; 567 chip->nc_block_size = params.param_blocksize * params.param_pagesize; 568 chip->nc_spare_size = params.param_sparesize; 569 chip->nc_lun_blocks = params.param_lunsize; 570 chip->nc_num_luns = params.param_numluns; 571 572 /* the lower 4 bits contain the row address cycles */ 573 chip->nc_addr_cycles_row = params.param_addr_cycles & 0x07; 574 /* the upper 4 bits contain the column address cycles */ 575 chip->nc_addr_cycles_column = (params.param_addr_cycles & ~0x07) >> 4; 576 577 if (params.param_features & ONFI_FEATURE_16BIT) 578 chip->nc_flags |= NC_BUSWIDTH_16; 579 580 if (params.param_features & ONFI_FEATURE_EXTENDED_PARAM) 581 chip->nc_flags |= NC_EXTENDED_PARAM; 582 583 return 0; 584 } 585 586 /* ARGSUSED */ 587 bool 588 nand_shutdown(device_t self, int howto) 589 { 590 return true; 591 } 592 593 static void 594 nand_address_column(device_t self, size_t row, size_t column) 595 { 596 struct nand_softc *sc = device_private(self); 597 struct nand_chip *chip = &sc->sc_chip; 598 uint8_t i; 599 600 DPRINTF(("addressing row: 0x%jx column: %" PRIu32 "\n", 601 (uintmax_t )row, column)); 602 603 /* XXX TODO */ 604 row >>= chip->nc_page_shift; 605 606 /* Write the column (subpage) address */ 607 if (chip->nc_flags & NC_BUSWIDTH_16) 608 column >>= 1; 609 for (i = 0; i < chip->nc_addr_cycles_column; i++, column >>= 8) 610 nand_address(self, column & 0xff); 611 612 /* Write the row (page) address */ 613 for (i = 0; i < chip->nc_addr_cycles_row; i++, row >>= 8) 614 nand_address(self, row & 0xff); 615 } 616 617 static void 618 nand_address_row(device_t self, size_t row) 619 { 620 struct nand_softc *sc = device_private(self); 621 struct nand_chip *chip = &sc->sc_chip; 622 int i; 623 624 /* XXX TODO */ 625 row >>= chip->nc_page_shift; 626 627 /* Write the row (page) address */ 628 for (i = 0; i < chip->nc_addr_cycles_row; i++, row >>= 8) 629 nand_address(self, row & 0xff); 630 } 631 632 static inline uint8_t 633 nand_get_status(device_t self) 634 { 635 uint8_t status; 636 637 nand_command(self, ONFI_READ_STATUS); 638 nand_busy(self); 639 nand_read_1(self, &status); 640 641 return status; 642 } 643 644 static bool 645 nand_check_wp(device_t self) 646 { 647 if (nand_get_status(self) & 0x80) 648 return false; 649 else 650 return true; 651 } 652 653 static void 654 nand_prepare_read(device_t self, flash_off_t row, flash_off_t column) 655 { 656 nand_command(self, ONFI_READ); 657 nand_address_column(self, row, column); 658 nand_command(self, ONFI_READ_START); 659 660 nand_busy(self); 661 } 662 663 /* read a page with ecc correction, default implementation */ 664 int 665 nand_default_read_page(device_t self, size_t offset, uint8_t *data) 666 { 667 struct nand_softc *sc = device_private(self); 668 struct nand_chip *chip = &sc->sc_chip; 669 size_t b, bs, e, cs; 670 uint8_t *ecc; 671 int result; 672 673 nand_prepare_read(self, offset, 0); 674 675 bs = chip->nc_ecc->necc_block_size; 676 cs = chip->nc_ecc->necc_code_size; 677 678 /* decide if we access by 8 or 16 bits */ 679 if (chip->nc_flags & NC_BUSWIDTH_16) { 680 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 681 nand_ecc_prepare(self, NAND_ECC_READ); 682 nand_read_buf_2(self, data + b, bs); 683 nand_ecc_compute(self, data + b, 684 chip->nc_ecc_cache + e); 685 } 686 } else { 687 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 688 nand_ecc_prepare(self, NAND_ECC_READ); 689 nand_read_buf_1(self, data + b, bs); 690 nand_ecc_compute(self, data + b, 691 chip->nc_ecc_cache + e); 692 } 693 } 694 695 /* for debugging new drivers */ 696 #if 0 697 nand_dump_data("page", data, chip->nc_page_size); 698 #endif 699 700 nand_read_oob(self, offset, chip->nc_oob_cache); 701 ecc = chip->nc_oob_cache + chip->nc_ecc->necc_offset; 702 703 /* useful for debugging new ecc drivers */ 704 #if 0 705 printf("dumping ecc %d\n--------------\n", chip->nc_ecc->necc_steps); 706 for (e = 0; e < chip->nc_ecc->necc_steps; e++) { 707 printf("0x"); 708 for (b = 0; b < cs; b++) { 709 printf("%.2hhx", ecc[e+b]); 710 } 711 printf(" 0x"); 712 for (b = 0; b < cs; b++) { 713 printf("%.2hhx", chip->nc_ecc_cache[e+b]); 714 } 715 printf("\n"); 716 } 717 printf("--------------\n"); 718 #endif 719 720 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 721 result = nand_ecc_correct(self, data + b, ecc + e, 722 chip->nc_ecc_cache + e); 723 724 switch (result) { 725 case NAND_ECC_OK: 726 break; 727 case NAND_ECC_CORRECTED: 728 aprint_error_dev(self, 729 "data corrected with ECC at page offset 0x%jx " 730 "block %zu\n", (uintmax_t)offset, b); 731 break; 732 case NAND_ECC_TWOBIT: 733 aprint_error_dev(self, 734 "uncorrectable ECC error at page offset 0x%jx " 735 "block %zu\n", (uintmax_t)offset, b); 736 return EIO; 737 break; 738 case NAND_ECC_INVALID: 739 aprint_error_dev(self, 740 "invalid ECC in oob at page offset 0x%jx " 741 "block %zu\n", (uintmax_t)offset, b); 742 return EIO; 743 break; 744 default: 745 panic("invalid ECC correction errno"); 746 } 747 } 748 749 return 0; 750 } 751 752 int 753 nand_default_program_page(device_t self, size_t page, const uint8_t *data) 754 { 755 struct nand_softc *sc = device_private(self); 756 struct nand_chip *chip = &sc->sc_chip; 757 size_t bs, cs, e, b; 758 uint8_t status; 759 uint8_t *ecc; 760 761 nand_command(self, ONFI_PAGE_PROGRAM); 762 nand_address_column(self, page, 0); 763 764 nand_busy(self); 765 766 bs = chip->nc_ecc->necc_block_size; 767 cs = chip->nc_ecc->necc_code_size; 768 ecc = chip->nc_oob_cache + chip->nc_ecc->necc_offset; 769 770 /* XXX code duplication */ 771 /* decide if we access by 8 or 16 bits */ 772 if (chip->nc_flags & NC_BUSWIDTH_16) { 773 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 774 nand_ecc_prepare(self, NAND_ECC_WRITE); 775 nand_write_buf_2(self, data + b, bs); 776 nand_ecc_compute(self, data + b, ecc + e); 777 } 778 /* write oob with ecc correction code */ 779 nand_write_buf_2(self, chip->nc_oob_cache, 780 chip->nc_spare_size); 781 } else { 782 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 783 nand_ecc_prepare(self, NAND_ECC_WRITE); 784 nand_write_buf_1(self, data + b, bs); 785 nand_ecc_compute(self, data + b, ecc + e); 786 } 787 /* write oob with ecc correction code */ 788 nand_write_buf_1(self, chip->nc_oob_cache, 789 chip->nc_spare_size); 790 } 791 792 nand_command(self, ONFI_PAGE_PROGRAM_START); 793 794 nand_busy(self); 795 796 /* for debugging ecc */ 797 #if 0 798 printf("dumping ecc %d\n--------------\n", chip->nc_ecc->necc_steps); 799 for (e = 0; e < chip->nc_ecc->necc_steps; e++) { 800 printf("0x"); 801 for (b = 0; b < cs; b++) { 802 printf("%.2hhx", ecc[e+b]); 803 } 804 printf("\n"); 805 } 806 printf("--------------\n"); 807 #endif 808 809 status = nand_get_status(self); 810 KASSERT(status & ONFI_STATUS_RDY); 811 if (status & ONFI_STATUS_FAIL) { 812 aprint_error_dev(self, "page program failed!\n"); 813 return EIO; 814 } 815 816 return 0; 817 } 818 819 /* read the OOB of a page */ 820 int 821 nand_read_oob(device_t self, size_t page, uint8_t *oob) 822 { 823 struct nand_softc *sc = device_private(self); 824 struct nand_chip *chip = &sc->sc_chip; 825 826 nand_prepare_read(self, page, chip->nc_page_size); 827 828 if (chip->nc_flags & NC_BUSWIDTH_16) 829 nand_read_buf_2(self, oob, chip->nc_spare_size); 830 else 831 nand_read_buf_1(self, oob, chip->nc_spare_size); 832 833 /* for debugging drivers */ 834 #if 0 835 nand_dump_data("oob", oob, chip->nc_spare_size); 836 #endif 837 838 return 0; 839 } 840 841 static int 842 nand_write_oob(device_t self, size_t offset, const void *oob) 843 { 844 struct nand_softc *sc = device_private(self); 845 struct nand_chip *chip = &sc->sc_chip; 846 uint8_t status; 847 848 nand_command(self, ONFI_PAGE_PROGRAM); 849 nand_address_column(self, offset, chip->nc_page_size); 850 nand_command(self, ONFI_PAGE_PROGRAM_START); 851 852 nand_busy(self); 853 854 if (chip->nc_flags & NC_BUSWIDTH_16) 855 nand_write_buf_2(self, oob, chip->nc_spare_size); 856 else 857 nand_write_buf_1(self, oob, chip->nc_spare_size); 858 859 status = nand_get_status(self); 860 KASSERT(status & ONFI_STATUS_RDY); 861 if (status & ONFI_STATUS_FAIL) 862 return EIO; 863 else 864 return 0; 865 } 866 867 void 868 nand_markbad(device_t self, size_t offset) 869 { 870 struct nand_softc *sc = device_private(self); 871 struct nand_chip *chip = &sc->sc_chip; 872 flash_off_t blockoffset, marker; 873 #ifdef NAND_BBT 874 flash_off_t block; 875 876 block = offset / chip->nc_block_size; 877 878 nand_bbt_block_markbad(self, block); 879 #endif 880 blockoffset = offset & chip->nc_block_mask; 881 marker = chip->nc_badmarker_offs & ~0x01; 882 883 /* check if it is already marked bad */ 884 if (nand_isbad(self, blockoffset)) 885 return; 886 887 nand_read_oob(self, blockoffset, chip->nc_oob_cache); 888 889 chip->nc_oob_cache[chip->nc_badmarker_offs] = 0x00; 890 chip->nc_oob_cache[chip->nc_badmarker_offs + 1] = 0x00; 891 892 nand_write_oob(self, blockoffset, chip->nc_oob_cache); 893 } 894 895 bool 896 nand_isfactorybad(device_t self, flash_off_t offset) 897 { 898 struct nand_softc *sc = device_private(self); 899 struct nand_chip *chip = &sc->sc_chip; 900 flash_off_t block, first_page, last_page, page; 901 int i; 902 903 /* Check for factory bad blocks first 904 * Factory bad blocks are marked in the first or last 905 * page of the blocks, see: ONFI 2.2, 3.2.2. 906 */ 907 block = offset / chip->nc_block_size; 908 first_page = block * chip->nc_block_size; 909 last_page = (block + 1) * chip->nc_block_size 910 - chip->nc_page_size; 911 912 for (i = 0, page = first_page; i < 2; i++, page = last_page) { 913 /* address OOB */ 914 nand_prepare_read(self, page, chip->nc_page_size); 915 916 if (chip->nc_flags & NC_BUSWIDTH_16) { 917 uint16_t word; 918 nand_read_2(self, &word); 919 if (word == 0x0000) 920 return true; 921 } else { 922 uint8_t byte; 923 nand_read_1(self, &byte); 924 if (byte == 0x00) 925 return true; 926 } 927 } 928 929 return false; 930 } 931 932 bool 933 nand_iswornoutbad(device_t self, flash_off_t offset) 934 { 935 struct nand_softc *sc = device_private(self); 936 struct nand_chip *chip = &sc->sc_chip; 937 flash_off_t block; 938 939 /* we inspect the first page of the block */ 940 block = offset & chip->nc_block_mask; 941 942 /* Linux/u-boot compatible badblock handling */ 943 if (chip->nc_flags & NC_BUSWIDTH_16) { 944 uint16_t word, mark; 945 946 nand_prepare_read(self, block, 947 chip->nc_page_size + (chip->nc_badmarker_offs & 0xfe)); 948 949 nand_read_2(self, &word); 950 mark = htole16(word); 951 if (chip->nc_badmarker_offs & 0x01) 952 mark >>= 8; 953 if ((mark & 0xff) != 0xff) 954 return true; 955 } else { 956 uint8_t byte; 957 958 nand_prepare_read(self, block, 959 chip->nc_page_size + chip->nc_badmarker_offs); 960 961 nand_read_1(self, &byte); 962 if (byte != 0xff) 963 return true; 964 } 965 966 return false; 967 } 968 969 bool 970 nand_isbad(device_t self, flash_off_t offset) 971 { 972 #ifdef NAND_BBT 973 struct nand_softc *sc = device_private(self); 974 struct nand_chip *chip = &sc->sc_chip; 975 flash_off_t block; 976 977 block = offset / chip->nc_block_size; 978 979 return nand_bbt_block_isbad(self, block); 980 #else 981 /* ONFI host requirement */ 982 if (nand_isfactorybad(self, offset)) 983 return true; 984 985 /* Look for Linux/U-Boot compatible bad marker */ 986 if (nand_iswornoutbad(self, offset)) 987 return true; 988 989 return false; 990 #endif 991 } 992 993 int 994 nand_erase_block(device_t self, size_t offset) 995 { 996 uint8_t status; 997 998 /* xxx calculate first page of block for address? */ 999 1000 nand_command(self, ONFI_BLOCK_ERASE); 1001 nand_address_row(self, offset); 1002 nand_command(self, ONFI_BLOCK_ERASE_START); 1003 1004 nand_busy(self); 1005 1006 status = nand_get_status(self); 1007 KASSERT(status & ONFI_STATUS_RDY); 1008 if (status & ONFI_STATUS_FAIL) { 1009 aprint_error_dev(self, "block erase failed!\n"); 1010 nand_markbad(self, offset); 1011 return EIO; 1012 } else { 1013 return 0; 1014 } 1015 } 1016 1017 /* default functions for driver development */ 1018 1019 /* default ECC using hamming code of 256 byte chunks */ 1020 int 1021 nand_default_ecc_compute(device_t self, const uint8_t *data, uint8_t *code) 1022 { 1023 hamming_compute_256(data, code); 1024 1025 return 0; 1026 } 1027 1028 int 1029 nand_default_ecc_correct(device_t self, uint8_t *data, const uint8_t *origcode, 1030 const uint8_t *compcode) 1031 { 1032 return hamming_correct_256(data, origcode, compcode); 1033 } 1034 1035 void 1036 nand_default_select(device_t self, bool enable) 1037 { 1038 /* do nothing */ 1039 return; 1040 } 1041 1042 /* implementation of the block device API */ 1043 1044 int 1045 nand_flash_submit(device_t self, struct buf * const bp) 1046 { 1047 struct nand_softc *sc = device_private(self); 1048 1049 return flash_io_submit(&sc->sc_flash_io, bp); 1050 } 1051 1052 /* 1053 * handle (page) unaligned write to nand 1054 */ 1055 static int 1056 nand_flash_write_unaligned(device_t self, flash_off_t offset, size_t len, 1057 size_t *retlen, const uint8_t *buf) 1058 { 1059 struct nand_softc *sc = device_private(self); 1060 struct nand_chip *chip = &sc->sc_chip; 1061 flash_off_t first, last, firstoff; 1062 const uint8_t *bufp; 1063 flash_off_t addr; 1064 size_t left, count; 1065 int error = 0, i; 1066 1067 first = offset & chip->nc_page_mask; 1068 firstoff = offset & ~chip->nc_page_mask; 1069 /* XXX check if this should be len - 1 */ 1070 last = (offset + len) & chip->nc_page_mask; 1071 count = last - first + 1; 1072 1073 addr = first; 1074 *retlen = 0; 1075 1076 mutex_enter(&sc->sc_device_lock); 1077 if (count == 1) { 1078 if (nand_isbad(self, addr)) { 1079 aprint_error_dev(self, 1080 "nand_flash_write_unaligned: " 1081 "bad block encountered\n"); 1082 error = EIO; 1083 goto out; 1084 } 1085 1086 error = nand_read_page(self, addr, chip->nc_page_cache); 1087 if (error) { 1088 goto out; 1089 } 1090 1091 memcpy(chip->nc_page_cache + firstoff, buf, len); 1092 1093 error = nand_program_page(self, addr, chip->nc_page_cache); 1094 if (error) { 1095 goto out; 1096 } 1097 1098 *retlen = len; 1099 goto out; 1100 } 1101 1102 bufp = buf; 1103 left = len; 1104 1105 for (i = 0; i < count && left != 0; i++) { 1106 if (nand_isbad(self, addr)) { 1107 aprint_error_dev(self, 1108 "nand_flash_write_unaligned: " 1109 "bad block encountered\n"); 1110 error = EIO; 1111 goto out; 1112 } 1113 1114 if (i == 0) { 1115 error = nand_read_page(self, 1116 addr, chip->nc_page_cache); 1117 if (error) { 1118 goto out; 1119 } 1120 1121 memcpy(chip->nc_page_cache + firstoff, 1122 bufp, chip->nc_page_size - firstoff); 1123 1124 printf("program page: %s: %d\n", __FILE__, __LINE__); 1125 error = nand_program_page(self, 1126 addr, chip->nc_page_cache); 1127 if (error) { 1128 goto out; 1129 } 1130 1131 bufp += chip->nc_page_size - firstoff; 1132 left -= chip->nc_page_size - firstoff; 1133 *retlen += chip->nc_page_size - firstoff; 1134 1135 } else if (i == count - 1) { 1136 error = nand_read_page(self, 1137 addr, chip->nc_page_cache); 1138 if (error) { 1139 goto out; 1140 } 1141 1142 memcpy(chip->nc_page_cache, bufp, left); 1143 1144 error = nand_program_page(self, 1145 addr, chip->nc_page_cache); 1146 if (error) { 1147 goto out; 1148 } 1149 1150 *retlen += left; 1151 KASSERT(left < chip->nc_page_size); 1152 1153 } else { 1154 /* XXX debug */ 1155 if (left > chip->nc_page_size) { 1156 printf("left: %zu, i: %d, count: %zu\n", 1157 left, i, count); 1158 } 1159 KASSERT(left > chip->nc_page_size); 1160 1161 error = nand_program_page(self, addr, bufp); 1162 if (error) { 1163 goto out; 1164 } 1165 1166 bufp += chip->nc_page_size; 1167 left -= chip->nc_page_size; 1168 *retlen += chip->nc_page_size; 1169 } 1170 1171 addr += chip->nc_page_size; 1172 } 1173 1174 KASSERT(*retlen == len); 1175 out: 1176 mutex_exit(&sc->sc_device_lock); 1177 1178 return error; 1179 } 1180 1181 int 1182 nand_flash_write(device_t self, flash_off_t offset, size_t len, size_t *retlen, 1183 const uint8_t *buf) 1184 { 1185 struct nand_softc *sc = device_private(self); 1186 struct nand_chip *chip = &sc->sc_chip; 1187 const uint8_t *bufp; 1188 size_t pages, page; 1189 daddr_t addr; 1190 int error = 0; 1191 1192 if ((offset + len) > chip->nc_size) { 1193 DPRINTF(("nand_flash_write: write (off: 0x%jx, len: %ju)," 1194 " is over device size (0x%jx)\n", 1195 (uintmax_t)offset, (uintmax_t)len, 1196 (uintmax_t)chip->nc_size)); 1197 return EINVAL; 1198 } 1199 1200 if (len % chip->nc_page_size != 0 || 1201 offset % chip->nc_page_size != 0) { 1202 return nand_flash_write_unaligned(self, 1203 offset, len, retlen, buf); 1204 } 1205 1206 pages = len / chip->nc_page_size; 1207 KASSERT(pages != 0); 1208 *retlen = 0; 1209 1210 addr = offset; 1211 bufp = buf; 1212 1213 mutex_enter(&sc->sc_device_lock); 1214 for (page = 0; page < pages; page++) { 1215 /* do we need this check here? */ 1216 if (nand_isbad(self, addr)) { 1217 aprint_error_dev(self, 1218 "nand_flash_write: bad block encountered\n"); 1219 1220 error = EIO; 1221 goto out; 1222 } 1223 1224 error = nand_program_page(self, addr, bufp); 1225 if (error) { 1226 goto out; 1227 } 1228 1229 addr += chip->nc_page_size; 1230 bufp += chip->nc_page_size; 1231 *retlen += chip->nc_page_size; 1232 } 1233 out: 1234 mutex_exit(&sc->sc_device_lock); 1235 DPRINTF(("page programming: retlen: %" PRIu32 ", len: %" PRIu32 "\n", *retlen, len)); 1236 1237 return error; 1238 } 1239 1240 /* 1241 * handle (page) unaligned read from nand 1242 */ 1243 static int 1244 nand_flash_read_unaligned(device_t self, size_t offset, 1245 size_t len, size_t *retlen, uint8_t *buf) 1246 { 1247 struct nand_softc *sc = device_private(self); 1248 struct nand_chip *chip = &sc->sc_chip; 1249 daddr_t first, last, count, firstoff; 1250 uint8_t *bufp; 1251 daddr_t addr; 1252 size_t left; 1253 int error = 0, i; 1254 1255 first = offset & chip->nc_page_mask; 1256 firstoff = offset & ~chip->nc_page_mask; 1257 last = (offset + len) & chip->nc_page_mask; 1258 count = (last - first) / chip->nc_page_size + 1; 1259 1260 addr = first; 1261 bufp = buf; 1262 left = len; 1263 *retlen = 0; 1264 1265 mutex_enter(&sc->sc_device_lock); 1266 if (count == 1) { 1267 error = nand_read_page(self, addr, chip->nc_page_cache); 1268 if (error) { 1269 goto out; 1270 } 1271 1272 memcpy(bufp, chip->nc_page_cache + firstoff, len); 1273 1274 *retlen = len; 1275 goto out; 1276 } 1277 1278 for (i = 0; i < count && left != 0; i++) { 1279 error = nand_read_page(self, addr, chip->nc_page_cache); 1280 if (error) { 1281 goto out; 1282 } 1283 1284 if (i == 0) { 1285 memcpy(bufp, chip->nc_page_cache + firstoff, 1286 chip->nc_page_size - firstoff); 1287 1288 bufp += chip->nc_page_size - firstoff; 1289 left -= chip->nc_page_size - firstoff; 1290 *retlen += chip->nc_page_size - firstoff; 1291 1292 } else if (i == count - 1) { 1293 memcpy(bufp, chip->nc_page_cache, left); 1294 *retlen += left; 1295 KASSERT(left < chip->nc_page_size); 1296 1297 } else { 1298 memcpy(bufp, chip->nc_page_cache, chip->nc_page_size); 1299 1300 bufp += chip->nc_page_size; 1301 left -= chip->nc_page_size; 1302 *retlen += chip->nc_page_size; 1303 } 1304 1305 addr += chip->nc_page_size; 1306 } 1307 KASSERT(*retlen == len); 1308 out: 1309 mutex_exit(&sc->sc_device_lock); 1310 1311 return error; 1312 } 1313 1314 int 1315 nand_flash_read(device_t self, flash_off_t offset, size_t len, size_t *retlen, 1316 uint8_t *buf) 1317 { 1318 struct nand_softc *sc = device_private(self); 1319 struct nand_chip *chip = &sc->sc_chip; 1320 uint8_t *bufp; 1321 size_t addr; 1322 size_t i, pages; 1323 int error = 0; 1324 1325 *retlen = 0; 1326 1327 DPRINTF(("nand_flash_read: off: 0x%jx, len: %" PRIu32 "\n", 1328 (uintmax_t)offset, len)); 1329 1330 if (__predict_false((offset + len) > chip->nc_size)) { 1331 DPRINTF(("nand_flash_read: read (off: 0x%jx, len: %" PRIu32 ")," 1332 " is over device size (%ju)\n", (uintmax_t)offset, 1333 len, (uintmax_t)chip->nc_size)); 1334 return EINVAL; 1335 } 1336 1337 /* Handle unaligned access, shouldnt be needed when using the 1338 * block device, as strategy handles it, so only low level 1339 * accesses will use this path 1340 */ 1341 /* XXX^2 */ 1342 #if 0 1343 if (len < chip->nc_page_size) 1344 panic("TODO page size is larger than read size"); 1345 #endif 1346 1347 if (len % chip->nc_page_size != 0 || 1348 offset % chip->nc_page_size != 0) { 1349 return nand_flash_read_unaligned(self, 1350 offset, len, retlen, buf); 1351 } 1352 1353 bufp = buf; 1354 addr = offset; 1355 pages = len / chip->nc_page_size; 1356 1357 mutex_enter(&sc->sc_device_lock); 1358 for (i = 0; i < pages; i++) { 1359 /* XXX do we need this check here? */ 1360 if (nand_isbad(self, addr)) { 1361 aprint_error_dev(self, "bad block encountered\n"); 1362 error = EIO; 1363 goto out; 1364 } 1365 error = nand_read_page(self, addr, bufp); 1366 if (error) 1367 goto out; 1368 1369 bufp += chip->nc_page_size; 1370 addr += chip->nc_page_size; 1371 *retlen += chip->nc_page_size; 1372 } 1373 out: 1374 mutex_exit(&sc->sc_device_lock); 1375 1376 return error; 1377 } 1378 1379 int 1380 nand_flash_isbad(device_t self, flash_off_t ofs, bool *is_bad) 1381 { 1382 struct nand_softc *sc = device_private(self); 1383 struct nand_chip *chip = &sc->sc_chip; 1384 bool result; 1385 1386 if (ofs > chip->nc_size) { 1387 DPRINTF(("nand_flash_isbad: offset 0x%jx is larger than" 1388 " device size (0x%jx)\n", (uintmax_t)ofs, 1389 (uintmax_t)chip->nc_size)); 1390 return EINVAL; 1391 } 1392 1393 if (ofs % chip->nc_block_size != 0) { 1394 DPRINTF(("offset (0x%jx) is not a multiple of block size " 1395 "(%ju)", 1396 (uintmax_t)ofs, (uintmax_t)chip->nc_block_size)); 1397 return EINVAL; 1398 } 1399 1400 mutex_enter(&sc->sc_device_lock); 1401 result = nand_isbad(self, ofs); 1402 mutex_exit(&sc->sc_device_lock); 1403 1404 *is_bad = result; 1405 1406 return 0; 1407 } 1408 1409 int 1410 nand_flash_markbad(device_t self, flash_off_t ofs) 1411 { 1412 struct nand_softc *sc = device_private(self); 1413 struct nand_chip *chip = &sc->sc_chip; 1414 1415 if (ofs > chip->nc_size) { 1416 DPRINTF(("nand_flash_markbad: offset 0x%jx is larger than" 1417 " device size (0x%jx)\n", ofs, 1418 (uintmax_t)chip->nc_size)); 1419 return EINVAL; 1420 } 1421 1422 if (ofs % chip->nc_block_size != 0) { 1423 panic("offset (%ju) is not a multiple of block size (%ju)", 1424 (uintmax_t)ofs, (uintmax_t)chip->nc_block_size); 1425 } 1426 1427 mutex_enter(&sc->sc_device_lock); 1428 nand_markbad(self, ofs); 1429 mutex_exit(&sc->sc_device_lock); 1430 1431 return 0; 1432 } 1433 1434 int 1435 nand_flash_erase(device_t self, 1436 struct flash_erase_instruction *ei) 1437 { 1438 struct nand_softc *sc = device_private(self); 1439 struct nand_chip *chip = &sc->sc_chip; 1440 flash_off_t addr; 1441 int error = 0; 1442 1443 if (ei->ei_addr < 0 || ei->ei_len < chip->nc_block_size) 1444 return EINVAL; 1445 1446 if (ei->ei_addr + ei->ei_len > chip->nc_size) { 1447 DPRINTF(("nand_flash_erase: erase address is over the end" 1448 " of the device\n")); 1449 return EINVAL; 1450 } 1451 1452 if (ei->ei_addr % chip->nc_block_size != 0) { 1453 aprint_error_dev(self, 1454 "nand_flash_erase: ei_addr (%ju) is not" 1455 " a multiple of block size (%ju)", 1456 (uintmax_t)ei->ei_addr, 1457 (uintmax_t)chip->nc_block_size); 1458 return EINVAL; 1459 } 1460 1461 if (ei->ei_len % chip->nc_block_size != 0) { 1462 aprint_error_dev(self, 1463 "nand_flash_erase: ei_len (%ju) is not" 1464 " a multiple of block size (%ju)", 1465 (uintmax_t)ei->ei_len, 1466 (uintmax_t)chip->nc_block_size); 1467 return EINVAL; 1468 } 1469 1470 mutex_enter(&sc->sc_device_lock); 1471 addr = ei->ei_addr; 1472 while (addr < ei->ei_addr + ei->ei_len) { 1473 if (nand_isbad(self, addr)) { 1474 aprint_error_dev(self, "bad block encountered\n"); 1475 ei->ei_state = FLASH_ERASE_FAILED; 1476 error = EIO; 1477 goto out; 1478 } 1479 1480 error = nand_erase_block(self, addr); 1481 if (error) { 1482 ei->ei_state = FLASH_ERASE_FAILED; 1483 goto out; 1484 } 1485 1486 addr += chip->nc_block_size; 1487 } 1488 mutex_exit(&sc->sc_device_lock); 1489 1490 ei->ei_state = FLASH_ERASE_DONE; 1491 if (ei->ei_callback != NULL) { 1492 ei->ei_callback(ei); 1493 } 1494 1495 return 0; 1496 out: 1497 mutex_exit(&sc->sc_device_lock); 1498 1499 return error; 1500 } 1501 1502 MODULE(MODULE_CLASS_DRIVER, nand, "flash"); 1503 1504 #ifdef _MODULE 1505 #include "ioconf.c" 1506 #endif 1507 1508 static int 1509 nand_modcmd(modcmd_t cmd, void *opaque) 1510 { 1511 switch (cmd) { 1512 case MODULE_CMD_INIT: 1513 #ifdef _MODULE 1514 return config_init_component(cfdriver_ioconf_nand, 1515 cfattach_ioconf_nand, cfdata_ioconf_nand); 1516 #else 1517 return 0; 1518 #endif 1519 case MODULE_CMD_FINI: 1520 #ifdef _MODULE 1521 return config_fini_component(cfdriver_ioconf_nand, 1522 cfattach_ioconf_nand, cfdata_ioconf_nand); 1523 #else 1524 return 0; 1525 #endif 1526 default: 1527 return ENOTTY; 1528 } 1529 } 1530