1 /* $NetBSD: nand.c,v 1.26 2017/11/09 21:50:15 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Department of Software Engineering, 5 * University of Szeged, Hungary 6 * Copyright (c) 2010 Adam Hoka <ahoka@NetBSD.org> 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by the Department of Software Engineering, University of Szeged, Hungary 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Common driver for NAND chips implementing the ONFI 2.2 specification */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: nand.c,v 1.26 2017/11/09 21:50:15 jmcneill Exp $"); 38 39 #include "locators.h" 40 41 #include <sys/param.h> 42 #include <sys/types.h> 43 #include <sys/device.h> 44 #include <sys/kmem.h> 45 #include <sys/atomic.h> 46 47 #include <dev/flash/flash.h> 48 #include <dev/flash/flash_io.h> 49 #include <dev/nand/nand.h> 50 #include <dev/nand/onfi.h> 51 #include <dev/nand/hamming.h> 52 #include <dev/nand/nand_bbt.h> 53 #include <dev/nand/nand_crc.h> 54 55 #include "opt_nand.h" 56 57 int nand_match(device_t, cfdata_t, void *); 58 void nand_attach(device_t, device_t, void *); 59 int nand_detach(device_t, int); 60 bool nand_shutdown(device_t, int); 61 62 int nand_print(void *, const char *); 63 64 static int nand_search(device_t, cfdata_t, const int *, void *); 65 static void nand_address_row(device_t, size_t); 66 static inline uint8_t nand_get_status(device_t); 67 static void nand_address_column(device_t, size_t, size_t); 68 static int nand_fill_chip_structure(device_t, struct nand_chip *); 69 static int nand_scan_media(device_t, struct nand_chip *); 70 static bool nand_check_wp(device_t); 71 72 CFATTACH_DECL_NEW(nand, sizeof(struct nand_softc), 73 nand_match, nand_attach, nand_detach, NULL); 74 75 #ifdef NAND_DEBUG 76 int nanddebug = NAND_DEBUG; 77 #endif 78 79 struct flash_interface nand_flash_if = { 80 .type = FLASH_TYPE_NAND, 81 82 .read = nand_flash_read, 83 .write = nand_flash_write, 84 .erase = nand_flash_erase, 85 .block_isbad = nand_flash_isbad, 86 .block_markbad = nand_flash_markbad, 87 88 .submit = nand_flash_submit 89 }; 90 91 const struct nand_manufacturer nand_mfrs[] = { 92 { NAND_MFR_AMD, "AMD" }, 93 { NAND_MFR_FUJITSU, "Fujitsu" }, 94 { NAND_MFR_RENESAS, "Renesas" }, 95 { NAND_MFR_STMICRO, "ST Micro" }, 96 { NAND_MFR_MICRON, "Micron" }, 97 { NAND_MFR_NATIONAL, "National" }, 98 { NAND_MFR_TOSHIBA, "Toshiba" }, 99 { NAND_MFR_HYNIX, "Hynix" }, 100 { NAND_MFR_SAMSUNG, "Samsung" }, 101 { NAND_MFR_UNKNOWN, "Unknown" } 102 }; 103 104 static const char * 105 nand_midtoname(int id) 106 { 107 int i; 108 109 for (i = 0; nand_mfrs[i].id != 0; i++) { 110 if (nand_mfrs[i].id == id) 111 return nand_mfrs[i].name; 112 } 113 114 KASSERT(nand_mfrs[i].id == 0); 115 116 return nand_mfrs[i].name; 117 } 118 119 /* ARGSUSED */ 120 int 121 nand_match(device_t parent, cfdata_t match, void *aux) 122 { 123 /* pseudo device, always attaches */ 124 return 1; 125 } 126 127 void 128 nand_attach(device_t parent, device_t self, void *aux) 129 { 130 struct nand_softc *sc = device_private(self); 131 struct nand_attach_args *naa = aux; 132 struct nand_chip *chip = &sc->sc_chip; 133 134 sc->sc_dev = self; 135 sc->controller_dev = parent; 136 sc->nand_if = naa->naa_nand_if; 137 138 aprint_naive("\n"); 139 140 if (nand_check_wp(self)) { 141 aprint_error("NAND chip is write protected!\n"); 142 return; 143 } 144 145 if (nand_scan_media(self, chip)) { 146 return; 147 } 148 149 nand_flash_if.erasesize = chip->nc_block_size; 150 nand_flash_if.page_size = chip->nc_page_size; 151 nand_flash_if.writesize = chip->nc_page_size; 152 153 /* allocate cache */ 154 chip->nc_oob_cache = kmem_alloc(chip->nc_spare_size, KM_SLEEP); 155 chip->nc_page_cache = kmem_alloc(chip->nc_page_size, KM_SLEEP); 156 157 mutex_init(&sc->sc_device_lock, MUTEX_DEFAULT, IPL_NONE); 158 159 if (flash_sync_thread_init(&sc->sc_flash_io, self, &nand_flash_if)) { 160 goto error; 161 } 162 163 if (!pmf_device_register1(sc->sc_dev, NULL, NULL, nand_shutdown)) 164 aprint_error_dev(sc->sc_dev, 165 "couldn't establish power handler\n"); 166 167 #ifdef NAND_BBT 168 nand_bbt_init(self); 169 nand_bbt_scan(self); 170 #endif 171 172 /* 173 * Attach all our devices 174 */ 175 config_search_ia(nand_search, self, NULL, NULL); 176 177 return; 178 error: 179 kmem_free(chip->nc_oob_cache, chip->nc_spare_size); 180 kmem_free(chip->nc_page_cache, chip->nc_page_size); 181 mutex_destroy(&sc->sc_device_lock); 182 } 183 184 static int 185 nand_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 186 { 187 struct nand_softc *sc = device_private(parent); 188 struct nand_chip *chip = &sc->sc_chip; 189 struct flash_attach_args faa; 190 191 faa.flash_if = &nand_flash_if; 192 193 faa.partinfo.part_offset = cf->cf_loc[FLASHBUSCF_OFFSET]; 194 195 if (cf->cf_loc[FLASHBUSCF_SIZE] == 0) { 196 faa.partinfo.part_size = chip->nc_size - 197 faa.partinfo.part_offset; 198 } else { 199 faa.partinfo.part_size = cf->cf_loc[FLASHBUSCF_SIZE]; 200 } 201 202 if (cf->cf_loc[FLASHBUSCF_READONLY]) 203 faa.partinfo.part_flags = FLASH_PART_READONLY; 204 else 205 faa.partinfo.part_flags = 0; 206 207 if (config_match(parent, cf, &faa)) { 208 if (config_attach(parent, cf, &faa, nand_print) != NULL) { 209 return 0; 210 } else { 211 return 1; 212 } 213 } 214 215 return 1; 216 } 217 218 int 219 nand_detach(device_t self, int flags) 220 { 221 struct nand_softc *sc = device_private(self); 222 struct nand_chip *chip = &sc->sc_chip; 223 int error = 0; 224 225 error = config_detach_children(self, flags); 226 if (error) { 227 return error; 228 } 229 230 flash_sync_thread_destroy(&sc->sc_flash_io); 231 #ifdef NAND_BBT 232 nand_bbt_detach(self); 233 #endif 234 /* free oob cache */ 235 kmem_free(chip->nc_oob_cache, chip->nc_spare_size); 236 kmem_free(chip->nc_page_cache, chip->nc_page_size); 237 kmem_free(chip->nc_ecc_cache, chip->nc_ecc->necc_size); 238 239 mutex_destroy(&sc->sc_device_lock); 240 241 pmf_device_deregister(sc->sc_dev); 242 243 return error; 244 } 245 246 int 247 nand_print(void *aux, const char *pnp) 248 { 249 if (pnp != NULL) 250 aprint_normal("nand at %s\n", pnp); 251 252 return UNCONF; 253 } 254 255 /* ask for a nand driver to attach to the controller */ 256 device_t 257 nand_attach_mi(struct nand_interface *nand_if, device_t parent) 258 { 259 struct nand_attach_args arg; 260 261 KASSERT(nand_if != NULL); 262 263 /* fill the defaults if we have null pointers */ 264 if (nand_if->program_page == NULL) { 265 nand_if->program_page = &nand_default_program_page; 266 } 267 268 if (nand_if->read_page == NULL) { 269 nand_if->read_page = &nand_default_read_page; 270 } 271 272 arg.naa_nand_if = nand_if; 273 return config_found_ia(parent, "nandbus", &arg, nand_print); 274 } 275 276 /* default everything to reasonable values, to ease future api changes */ 277 void 278 nand_init_interface(struct nand_interface *interface) 279 { 280 interface->select = &nand_default_select; 281 interface->command = NULL; 282 interface->address = NULL; 283 interface->read_buf_1 = NULL; 284 interface->read_buf_2 = NULL; 285 interface->read_1 = NULL; 286 interface->read_2 = NULL; 287 interface->write_buf_1 = NULL; 288 interface->write_buf_2 = NULL; 289 interface->write_1 = NULL; 290 interface->write_2 = NULL; 291 interface->busy = NULL; 292 293 /*- 294 * most drivers dont want to change this, but some implement 295 * read/program in one step 296 */ 297 interface->program_page = &nand_default_program_page; 298 interface->read_page = &nand_default_read_page; 299 300 /* default to soft ecc, that should work everywhere */ 301 interface->ecc_compute = &nand_default_ecc_compute; 302 interface->ecc_correct = &nand_default_ecc_correct; 303 interface->ecc_prepare = NULL; 304 interface->ecc.necc_code_size = 3; 305 interface->ecc.necc_block_size = 256; 306 interface->ecc.necc_type = NAND_ECC_TYPE_SW; 307 } 308 309 #if 0 310 /* handle quirks here */ 311 static void 312 nand_quirks(device_t self, struct nand_chip *chip) 313 { 314 /* this is an example only! */ 315 switch (chip->nc_manf_id) { 316 case NAND_MFR_SAMSUNG: 317 if (chip->nc_dev_id == 0x00) { 318 /* do something only samsung chips need */ 319 /* or */ 320 /* chip->nc_quirks |= NC_QUIRK_NO_READ_START */ 321 } 322 } 323 324 return; 325 } 326 #endif 327 328 static int 329 nand_fill_chip_structure_legacy(device_t self, struct nand_chip *chip) 330 { 331 switch (chip->nc_manf_id) { 332 case NAND_MFR_MICRON: 333 return nand_read_parameters_micron(self, chip); 334 case NAND_MFR_SAMSUNG: 335 return nand_read_parameters_samsung(self, chip); 336 case NAND_MFR_TOSHIBA: 337 return nand_read_parameters_toshiba(self, chip); 338 default: 339 return 1; 340 } 341 342 return 0; 343 } 344 345 /** 346 * scan media to determine the chip's properties 347 * this function resets the device 348 */ 349 static int 350 nand_scan_media(device_t self, struct nand_chip *chip) 351 { 352 struct nand_softc *sc = device_private(self); 353 struct nand_ecc *ecc; 354 uint8_t onfi_signature[4]; 355 356 nand_select(self, true); 357 nand_command(self, ONFI_RESET); 358 KASSERT(nand_get_status(self) & ONFI_STATUS_RDY); 359 nand_select(self, false); 360 361 /* check if the device implements the ONFI standard */ 362 nand_select(self, true); 363 nand_command(self, ONFI_READ_ID); 364 nand_address(self, 0x20); 365 nand_read_1(self, &onfi_signature[0]); 366 nand_read_1(self, &onfi_signature[1]); 367 nand_read_1(self, &onfi_signature[2]); 368 nand_read_1(self, &onfi_signature[3]); 369 nand_select(self, false); 370 371 #ifdef NAND_DEBUG 372 device_printf(self, "signature: %02x %02x %02x %02x\n", 373 onfi_signature[0], onfi_signature[1], 374 onfi_signature[2], onfi_signature[3]); 375 #endif 376 377 if (onfi_signature[0] != 'O' || onfi_signature[1] != 'N' || 378 onfi_signature[2] != 'F' || onfi_signature[3] != 'I') { 379 chip->nc_isonfi = false; 380 381 aprint_normal(": Legacy NAND Flash\n"); 382 383 nand_read_id(self, &chip->nc_manf_id, &chip->nc_dev_id); 384 385 if (nand_fill_chip_structure_legacy(self, chip)) { 386 aprint_error_dev(self, 387 "can't read device parameters for legacy chip\n"); 388 return 1; 389 } 390 } else { 391 chip->nc_isonfi = true; 392 393 aprint_normal(": ONFI NAND Flash\n"); 394 395 nand_read_id(self, &chip->nc_manf_id, &chip->nc_dev_id); 396 397 if (nand_fill_chip_structure(self, chip)) { 398 aprint_error_dev(self, 399 "can't read device parameters\n"); 400 return 1; 401 } 402 } 403 404 aprint_normal_dev(self, 405 "manufacturer id: 0x%.2x (%s), device id: 0x%.2x\n", 406 chip->nc_manf_id, 407 nand_midtoname(chip->nc_manf_id), 408 chip->nc_dev_id); 409 410 aprint_normal_dev(self, 411 "page size: %" PRIu32 " bytes, spare size: %" PRIu32 " bytes, " 412 "block size: %" PRIu32 " bytes\n", 413 chip->nc_page_size, chip->nc_spare_size, chip->nc_block_size); 414 415 aprint_normal_dev(self, 416 "LUN size: %" PRIu32 " blocks, LUNs: %" PRIu8 417 ", total storage size: %" PRIu64 " MB\n", 418 chip->nc_lun_blocks, chip->nc_num_luns, 419 chip->nc_size / 1024 / 1024); 420 421 aprint_normal_dev(self, "column cycles: %" PRIu8 ", row cycles: %" 422 PRIu8 ", width: %s\n", 423 chip->nc_addr_cycles_column, chip->nc_addr_cycles_row, 424 (chip->nc_flags & NC_BUSWIDTH_16) ? "x16" : "x8"); 425 426 ecc = chip->nc_ecc = &sc->nand_if->ecc; 427 428 /* 429 * calculate the place of ecc data in oob 430 * we try to be compatible with Linux here 431 */ 432 switch (chip->nc_spare_size) { 433 case 8: 434 ecc->necc_offset = 0; 435 break; 436 case 16: 437 ecc->necc_offset = 0; 438 break; 439 case 32: 440 ecc->necc_offset = 0; 441 break; 442 case 64: 443 ecc->necc_offset = 40; 444 break; 445 case 128: 446 ecc->necc_offset = 80; 447 break; 448 default: 449 panic("OOB size %" PRIu32 " is unexpected", chip->nc_spare_size); 450 } 451 452 ecc->necc_steps = chip->nc_page_size / ecc->necc_block_size; 453 ecc->necc_size = ecc->necc_steps * ecc->necc_code_size; 454 455 /* check if we fit in oob */ 456 if (ecc->necc_offset + ecc->necc_size > chip->nc_spare_size) { 457 panic("NAND ECC bits dont fit in OOB"); 458 } 459 460 /* TODO: mark free oob area available for file systems */ 461 462 chip->nc_ecc_cache = kmem_zalloc(ecc->necc_size, KM_SLEEP); 463 464 /* 465 * calculate badblock marker offset in oob 466 * we try to be compatible with linux here 467 */ 468 if (chip->nc_page_size > 512) 469 chip->nc_badmarker_offs = 0; 470 else 471 chip->nc_badmarker_offs = 5; 472 473 /* Calculate page shift and mask */ 474 chip->nc_page_shift = ffs(chip->nc_page_size) - 1; 475 chip->nc_page_mask = ~(chip->nc_page_size - 1); 476 /* same for block */ 477 chip->nc_block_shift = ffs(chip->nc_block_size) - 1; 478 chip->nc_block_mask = ~(chip->nc_block_size - 1); 479 480 /* look for quirks here if needed in future */ 481 /* nand_quirks(self, chip); */ 482 483 return 0; 484 } 485 486 void 487 nand_read_id(device_t self, uint8_t *manf, uint8_t *dev) 488 { 489 nand_select(self, true); 490 nand_command(self, ONFI_READ_ID); 491 nand_address(self, 0x00); 492 493 nand_read_1(self, manf); 494 nand_read_1(self, dev); 495 496 nand_select(self, false); 497 } 498 499 int 500 nand_read_parameter_page(device_t self, struct onfi_parameter_page *params) 501 { 502 uint8_t *bufp; 503 uint16_t crc; 504 int i;//, tries = 0; 505 506 KASSERT(sizeof(*params) == 256); 507 508 //read_params: 509 // tries++; 510 511 nand_select(self, true); 512 nand_command(self, ONFI_READ_PARAMETER_PAGE); 513 nand_address(self, 0x00); 514 515 nand_busy(self); 516 517 /* TODO check the signature if it contains at least 2 letters */ 518 519 bufp = (uint8_t *)params; 520 /* XXX why i am not using read_buf? */ 521 for (i = 0; i < 256; i++) { 522 nand_read_1(self, &bufp[i]); 523 } 524 nand_select(self, false); 525 526 /* validate the parameter page with the crc */ 527 crc = nand_crc16(bufp, 254); 528 529 if (crc != params->param_integrity_crc) { 530 aprint_error_dev(self, "parameter page crc check failed\n"); 531 /* TODO: we should read the next parameter page copy */ 532 return 1; 533 } 534 535 return 0; 536 } 537 538 static int 539 nand_fill_chip_structure(device_t self, struct nand_chip *chip) 540 { 541 struct onfi_parameter_page params; 542 uint8_t vendor[13], model[21]; 543 int i; 544 545 if (nand_read_parameter_page(self, ¶ms)) { 546 return 1; 547 } 548 549 /* strip manufacturer and model string */ 550 strlcpy(vendor, params.param_manufacturer, sizeof(vendor)); 551 for (i = 11; i > 0 && vendor[i] == ' '; i--) 552 vendor[i] = 0; 553 strlcpy(model, params.param_model, sizeof(model)); 554 for (i = 19; i > 0 && model[i] == ' '; i--) 555 model[i] = 0; 556 557 aprint_normal_dev(self, "vendor: %s, model: %s\n", vendor, model); 558 559 chip->nc_page_size = le32toh(params.param_pagesize); 560 chip->nc_block_size = 561 le32toh(params.param_blocksize) * chip->nc_page_size; 562 chip->nc_spare_size = le16toh(params.param_sparesize); 563 chip->nc_lun_blocks = le32toh(params.param_lunsize); 564 chip->nc_num_luns = params.param_numluns; 565 566 chip->nc_size = 567 chip->nc_block_size * chip->nc_lun_blocks * chip->nc_num_luns; 568 569 /* the lower 4 bits contain the row address cycles */ 570 chip->nc_addr_cycles_row = params.param_addr_cycles & 0x07; 571 /* the upper 4 bits contain the column address cycles */ 572 chip->nc_addr_cycles_column = (params.param_addr_cycles & ~0x07) >> 4; 573 574 uint16_t features = le16toh(params.param_features); 575 if (features & ONFI_FEATURE_16BIT) { 576 chip->nc_flags |= NC_BUSWIDTH_16; 577 } 578 579 if (features & ONFI_FEATURE_EXTENDED_PARAM) { 580 chip->nc_flags |= NC_EXTENDED_PARAM; 581 } 582 583 return 0; 584 } 585 586 /* ARGSUSED */ 587 bool 588 nand_shutdown(device_t self, int howto) 589 { 590 return true; 591 } 592 593 static void 594 nand_address_column(device_t self, size_t row, size_t column) 595 { 596 struct nand_softc *sc = device_private(self); 597 struct nand_chip *chip = &sc->sc_chip; 598 uint8_t i; 599 600 DPRINTF(("addressing row: 0x%jx column: %" PRIu32 "\n", 601 (uintmax_t )row, column)); 602 603 /* XXX TODO */ 604 row >>= chip->nc_page_shift; 605 606 /* Write the column (subpage) address */ 607 if (chip->nc_flags & NC_BUSWIDTH_16) 608 column >>= 1; 609 for (i = 0; i < chip->nc_addr_cycles_column; i++, column >>= 8) 610 nand_address(self, column & 0xff); 611 612 /* Write the row (page) address */ 613 for (i = 0; i < chip->nc_addr_cycles_row; i++, row >>= 8) 614 nand_address(self, row & 0xff); 615 } 616 617 static void 618 nand_address_row(device_t self, size_t row) 619 { 620 struct nand_softc *sc = device_private(self); 621 struct nand_chip *chip = &sc->sc_chip; 622 int i; 623 624 /* XXX TODO */ 625 row >>= chip->nc_page_shift; 626 627 /* Write the row (page) address */ 628 for (i = 0; i < chip->nc_addr_cycles_row; i++, row >>= 8) 629 nand_address(self, row & 0xff); 630 } 631 632 static inline uint8_t 633 nand_get_status(device_t self) 634 { 635 uint8_t status; 636 637 nand_command(self, ONFI_READ_STATUS); 638 nand_busy(self); 639 nand_read_1(self, &status); 640 641 return status; 642 } 643 644 static bool 645 nand_check_wp(device_t self) 646 { 647 if (nand_get_status(self) & ONFI_STATUS_WP) 648 return false; 649 else 650 return true; 651 } 652 653 static void 654 nand_prepare_read(device_t self, flash_off_t row, flash_off_t column) 655 { 656 nand_command(self, ONFI_READ); 657 nand_address_column(self, row, column); 658 nand_command(self, ONFI_READ_START); 659 660 nand_busy(self); 661 } 662 663 /* read a page with ecc correction, default implementation */ 664 int 665 nand_default_read_page(device_t self, size_t offset, uint8_t *data) 666 { 667 struct nand_softc *sc = device_private(self); 668 struct nand_chip *chip = &sc->sc_chip; 669 size_t b, bs, e, cs; 670 uint8_t *ecc; 671 int result; 672 673 nand_prepare_read(self, offset, 0); 674 675 bs = chip->nc_ecc->necc_block_size; 676 cs = chip->nc_ecc->necc_code_size; 677 678 /* decide if we access by 8 or 16 bits */ 679 if (chip->nc_flags & NC_BUSWIDTH_16) { 680 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 681 nand_ecc_prepare(self, NAND_ECC_READ); 682 nand_read_buf_2(self, data + b, bs); 683 nand_ecc_compute(self, data + b, 684 chip->nc_ecc_cache + e); 685 } 686 } else { 687 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 688 nand_ecc_prepare(self, NAND_ECC_READ); 689 nand_read_buf_1(self, data + b, bs); 690 nand_ecc_compute(self, data + b, 691 chip->nc_ecc_cache + e); 692 } 693 } 694 695 /* for debugging new drivers */ 696 #if 0 697 nand_dump_data("page", data, chip->nc_page_size); 698 #endif 699 700 nand_read_oob(self, offset, chip->nc_oob_cache); 701 ecc = chip->nc_oob_cache + chip->nc_ecc->necc_offset; 702 703 /* useful for debugging new ecc drivers */ 704 #if 0 705 printf("dumping ecc %d\n--------------\n", chip->nc_ecc->necc_steps); 706 for (e = 0; e < chip->nc_ecc->necc_steps; e++) { 707 printf("0x"); 708 for (b = 0; b < cs; b++) { 709 printf("%.2hhx", ecc[e+b]); 710 } 711 printf(" 0x"); 712 for (b = 0; b < cs; b++) { 713 printf("%.2hhx", chip->nc_ecc_cache[e+b]); 714 } 715 printf("\n"); 716 } 717 printf("--------------\n"); 718 #endif 719 720 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 721 result = nand_ecc_correct(self, data + b, ecc + e, 722 chip->nc_ecc_cache + e); 723 724 switch (result) { 725 case NAND_ECC_OK: 726 break; 727 case NAND_ECC_CORRECTED: 728 aprint_error_dev(self, 729 "data corrected with ECC at page offset 0x%jx " 730 "block %zu\n", (uintmax_t)offset, b); 731 break; 732 case NAND_ECC_TWOBIT: 733 aprint_error_dev(self, 734 "uncorrectable ECC error at page offset 0x%jx " 735 "block %zu\n", (uintmax_t)offset, b); 736 return EIO; 737 break; 738 case NAND_ECC_INVALID: 739 aprint_error_dev(self, 740 "invalid ECC in oob at page offset 0x%jx " 741 "block %zu\n", (uintmax_t)offset, b); 742 return EIO; 743 break; 744 default: 745 panic("invalid ECC correction errno"); 746 } 747 } 748 749 return 0; 750 } 751 752 int 753 nand_default_program_page(device_t self, size_t page, const uint8_t *data) 754 { 755 struct nand_softc *sc = device_private(self); 756 struct nand_chip *chip = &sc->sc_chip; 757 size_t bs, cs, e, b; 758 uint8_t status; 759 uint8_t *ecc; 760 761 nand_command(self, ONFI_PAGE_PROGRAM); 762 nand_address_column(self, page, 0); 763 764 nand_busy(self); 765 766 bs = chip->nc_ecc->necc_block_size; 767 cs = chip->nc_ecc->necc_code_size; 768 ecc = chip->nc_oob_cache + chip->nc_ecc->necc_offset; 769 770 /* XXX code duplication */ 771 /* decide if we access by 8 or 16 bits */ 772 if (chip->nc_flags & NC_BUSWIDTH_16) { 773 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 774 nand_ecc_prepare(self, NAND_ECC_WRITE); 775 nand_write_buf_2(self, data + b, bs); 776 nand_ecc_compute(self, data + b, ecc + e); 777 } 778 /* write oob with ecc correction code */ 779 nand_write_buf_2(self, chip->nc_oob_cache, 780 chip->nc_spare_size); 781 } else { 782 for (b = 0, e = 0; b < chip->nc_page_size; b += bs, e += cs) { 783 nand_ecc_prepare(self, NAND_ECC_WRITE); 784 nand_write_buf_1(self, data + b, bs); 785 nand_ecc_compute(self, data + b, ecc + e); 786 } 787 /* write oob with ecc correction code */ 788 nand_write_buf_1(self, chip->nc_oob_cache, 789 chip->nc_spare_size); 790 } 791 792 nand_command(self, ONFI_PAGE_PROGRAM_START); 793 794 nand_busy(self); 795 796 /* for debugging ecc */ 797 #if 0 798 printf("dumping ecc %d\n--------------\n", chip->nc_ecc->necc_steps); 799 for (e = 0; e < chip->nc_ecc->necc_steps; e++) { 800 printf("0x"); 801 for (b = 0; b < cs; b++) { 802 printf("%.2hhx", ecc[e+b]); 803 } 804 printf("\n"); 805 } 806 printf("--------------\n"); 807 #endif 808 809 status = nand_get_status(self); 810 KASSERT(status & ONFI_STATUS_RDY); 811 if (status & ONFI_STATUS_FAIL) { 812 aprint_error_dev(self, "page program failed!\n"); 813 return EIO; 814 } 815 816 return 0; 817 } 818 819 /* read the OOB of a page */ 820 int 821 nand_read_oob(device_t self, size_t page, uint8_t *oob) 822 { 823 struct nand_softc *sc = device_private(self); 824 struct nand_chip *chip = &sc->sc_chip; 825 826 nand_prepare_read(self, page, chip->nc_page_size); 827 828 if (chip->nc_flags & NC_BUSWIDTH_16) 829 nand_read_buf_2(self, oob, chip->nc_spare_size); 830 else 831 nand_read_buf_1(self, oob, chip->nc_spare_size); 832 833 /* for debugging drivers */ 834 #if 0 835 nand_dump_data("oob", oob, chip->nc_spare_size); 836 #endif 837 838 return 0; 839 } 840 841 static int 842 nand_write_oob(device_t self, size_t offset, const void *oob) 843 { 844 struct nand_softc *sc = device_private(self); 845 struct nand_chip *chip = &sc->sc_chip; 846 uint8_t status; 847 848 nand_command(self, ONFI_PAGE_PROGRAM); 849 nand_address_column(self, offset, chip->nc_page_size); 850 nand_command(self, ONFI_PAGE_PROGRAM_START); 851 852 nand_busy(self); 853 854 if (chip->nc_flags & NC_BUSWIDTH_16) 855 nand_write_buf_2(self, oob, chip->nc_spare_size); 856 else 857 nand_write_buf_1(self, oob, chip->nc_spare_size); 858 859 status = nand_get_status(self); 860 KASSERT(status & ONFI_STATUS_RDY); 861 if (status & ONFI_STATUS_FAIL) 862 return EIO; 863 else 864 return 0; 865 } 866 867 void 868 nand_markbad(device_t self, size_t offset) 869 { 870 struct nand_softc *sc = device_private(self); 871 struct nand_chip *chip = &sc->sc_chip; 872 flash_off_t blockoffset; 873 #ifdef NAND_BBT 874 flash_off_t block; 875 876 block = offset / chip->nc_block_size; 877 878 nand_bbt_block_markbad(self, block); 879 #endif 880 blockoffset = offset & chip->nc_block_mask; 881 882 /* check if it is already marked bad */ 883 if (nand_isbad(self, blockoffset)) 884 return; 885 886 nand_read_oob(self, blockoffset, chip->nc_oob_cache); 887 888 chip->nc_oob_cache[chip->nc_badmarker_offs] = 0x00; 889 chip->nc_oob_cache[chip->nc_badmarker_offs + 1] = 0x00; 890 891 nand_write_oob(self, blockoffset, chip->nc_oob_cache); 892 } 893 894 bool 895 nand_isfactorybad(device_t self, flash_off_t offset) 896 { 897 struct nand_softc *sc = device_private(self); 898 struct nand_chip *chip = &sc->sc_chip; 899 flash_off_t block, first_page, last_page, page; 900 int i; 901 902 /* Check for factory bad blocks first 903 * Factory bad blocks are marked in the first or last 904 * page of the blocks, see: ONFI 2.2, 3.2.2. 905 */ 906 block = offset / chip->nc_block_size; 907 first_page = block * chip->nc_block_size; 908 last_page = (block + 1) * chip->nc_block_size 909 - chip->nc_page_size; 910 911 for (i = 0, page = first_page; i < 2; i++, page = last_page) { 912 /* address OOB */ 913 nand_prepare_read(self, page, chip->nc_page_size); 914 915 if (chip->nc_flags & NC_BUSWIDTH_16) { 916 uint16_t word; 917 nand_read_2(self, &word); 918 if (word == 0x0000) 919 return true; 920 } else { 921 uint8_t byte; 922 nand_read_1(self, &byte); 923 if (byte == 0x00) 924 return true; 925 } 926 } 927 928 return false; 929 } 930 931 bool 932 nand_iswornoutbad(device_t self, flash_off_t offset) 933 { 934 struct nand_softc *sc = device_private(self); 935 struct nand_chip *chip = &sc->sc_chip; 936 flash_off_t block; 937 938 /* we inspect the first page of the block */ 939 block = offset & chip->nc_block_mask; 940 941 /* Linux/u-boot compatible badblock handling */ 942 if (chip->nc_flags & NC_BUSWIDTH_16) { 943 uint16_t word, mark; 944 945 nand_prepare_read(self, block, 946 chip->nc_page_size + (chip->nc_badmarker_offs & 0xfe)); 947 948 nand_read_2(self, &word); 949 mark = htole16(word); 950 if (chip->nc_badmarker_offs & 0x01) 951 mark >>= 8; 952 if ((mark & 0xff) != 0xff) 953 return true; 954 } else { 955 uint8_t byte; 956 957 nand_prepare_read(self, block, 958 chip->nc_page_size + chip->nc_badmarker_offs); 959 960 nand_read_1(self, &byte); 961 if (byte != 0xff) 962 return true; 963 } 964 965 return false; 966 } 967 968 bool 969 nand_isbad(device_t self, flash_off_t offset) 970 { 971 #ifdef NAND_BBT 972 struct nand_softc *sc = device_private(self); 973 struct nand_chip *chip = &sc->sc_chip; 974 flash_off_t block; 975 976 block = offset / chip->nc_block_size; 977 978 return nand_bbt_block_isbad(self, block); 979 #else 980 /* ONFI host requirement */ 981 if (nand_isfactorybad(self, offset)) 982 return true; 983 984 /* Look for Linux/U-Boot compatible bad marker */ 985 if (nand_iswornoutbad(self, offset)) 986 return true; 987 988 return false; 989 #endif 990 } 991 992 int 993 nand_erase_block(device_t self, size_t offset) 994 { 995 uint8_t status; 996 997 /* xxx calculate first page of block for address? */ 998 999 nand_command(self, ONFI_BLOCK_ERASE); 1000 nand_address_row(self, offset); 1001 nand_command(self, ONFI_BLOCK_ERASE_START); 1002 1003 nand_busy(self); 1004 1005 status = nand_get_status(self); 1006 KASSERT(status & ONFI_STATUS_RDY); 1007 if (status & ONFI_STATUS_FAIL) { 1008 aprint_error_dev(self, "block erase failed!\n"); 1009 nand_markbad(self, offset); 1010 return EIO; 1011 } else { 1012 return 0; 1013 } 1014 } 1015 1016 /* default functions for driver development */ 1017 1018 /* default ECC using hamming code of 256 byte chunks */ 1019 int 1020 nand_default_ecc_compute(device_t self, const uint8_t *data, uint8_t *code) 1021 { 1022 hamming_compute_256(data, code); 1023 1024 return 0; 1025 } 1026 1027 int 1028 nand_default_ecc_correct(device_t self, uint8_t *data, const uint8_t *origcode, 1029 const uint8_t *compcode) 1030 { 1031 return hamming_correct_256(data, origcode, compcode); 1032 } 1033 1034 void 1035 nand_default_select(device_t self, bool enable) 1036 { 1037 /* do nothing */ 1038 return; 1039 } 1040 1041 /* implementation of the block device API */ 1042 1043 int 1044 nand_flash_submit(device_t self, struct buf * const bp) 1045 { 1046 struct nand_softc *sc = device_private(self); 1047 1048 return flash_io_submit(&sc->sc_flash_io, bp); 1049 } 1050 1051 /* 1052 * handle (page) unaligned write to nand 1053 */ 1054 static int 1055 nand_flash_write_unaligned(device_t self, flash_off_t offset, size_t len, 1056 size_t *retlen, const uint8_t *buf) 1057 { 1058 struct nand_softc *sc = device_private(self); 1059 struct nand_chip *chip = &sc->sc_chip; 1060 flash_off_t first, last, firstoff; 1061 const uint8_t *bufp; 1062 flash_off_t addr; 1063 size_t left, count; 1064 int error = 0, i; 1065 1066 first = offset & chip->nc_page_mask; 1067 firstoff = offset & ~chip->nc_page_mask; 1068 /* XXX check if this should be len - 1 */ 1069 last = (offset + len) & chip->nc_page_mask; 1070 count = last - first + 1; 1071 1072 addr = first; 1073 *retlen = 0; 1074 1075 mutex_enter(&sc->sc_device_lock); 1076 if (count == 1) { 1077 if (nand_isbad(self, addr)) { 1078 aprint_error_dev(self, 1079 "nand_flash_write_unaligned: " 1080 "bad block encountered\n"); 1081 error = EIO; 1082 goto out; 1083 } 1084 1085 error = nand_read_page(self, addr, chip->nc_page_cache); 1086 if (error) { 1087 goto out; 1088 } 1089 1090 memcpy(chip->nc_page_cache + firstoff, buf, len); 1091 1092 error = nand_program_page(self, addr, chip->nc_page_cache); 1093 if (error) { 1094 goto out; 1095 } 1096 1097 *retlen = len; 1098 goto out; 1099 } 1100 1101 bufp = buf; 1102 left = len; 1103 1104 for (i = 0; i < count && left != 0; i++) { 1105 if (nand_isbad(self, addr)) { 1106 aprint_error_dev(self, 1107 "nand_flash_write_unaligned: " 1108 "bad block encountered\n"); 1109 error = EIO; 1110 goto out; 1111 } 1112 1113 if (i == 0) { 1114 error = nand_read_page(self, 1115 addr, chip->nc_page_cache); 1116 if (error) { 1117 goto out; 1118 } 1119 1120 memcpy(chip->nc_page_cache + firstoff, 1121 bufp, chip->nc_page_size - firstoff); 1122 1123 printf("program page: %s: %d\n", __FILE__, __LINE__); 1124 error = nand_program_page(self, 1125 addr, chip->nc_page_cache); 1126 if (error) { 1127 goto out; 1128 } 1129 1130 bufp += chip->nc_page_size - firstoff; 1131 left -= chip->nc_page_size - firstoff; 1132 *retlen += chip->nc_page_size - firstoff; 1133 1134 } else if (i == count - 1) { 1135 error = nand_read_page(self, 1136 addr, chip->nc_page_cache); 1137 if (error) { 1138 goto out; 1139 } 1140 1141 memcpy(chip->nc_page_cache, bufp, left); 1142 1143 error = nand_program_page(self, 1144 addr, chip->nc_page_cache); 1145 if (error) { 1146 goto out; 1147 } 1148 1149 *retlen += left; 1150 KASSERT(left < chip->nc_page_size); 1151 1152 } else { 1153 /* XXX debug */ 1154 if (left > chip->nc_page_size) { 1155 printf("left: %zu, i: %d, count: %zu\n", 1156 left, i, count); 1157 } 1158 KASSERT(left > chip->nc_page_size); 1159 1160 error = nand_program_page(self, addr, bufp); 1161 if (error) { 1162 goto out; 1163 } 1164 1165 bufp += chip->nc_page_size; 1166 left -= chip->nc_page_size; 1167 *retlen += chip->nc_page_size; 1168 } 1169 1170 addr += chip->nc_page_size; 1171 } 1172 1173 KASSERT(*retlen == len); 1174 out: 1175 mutex_exit(&sc->sc_device_lock); 1176 1177 return error; 1178 } 1179 1180 int 1181 nand_flash_write(device_t self, flash_off_t offset, size_t len, size_t *retlen, 1182 const uint8_t *buf) 1183 { 1184 struct nand_softc *sc = device_private(self); 1185 struct nand_chip *chip = &sc->sc_chip; 1186 const uint8_t *bufp; 1187 size_t pages, page; 1188 daddr_t addr; 1189 int error = 0; 1190 1191 if ((offset + len) > chip->nc_size) { 1192 DPRINTF(("nand_flash_write: write (off: 0x%jx, len: %ju)," 1193 " is over device size (0x%jx)\n", 1194 (uintmax_t)offset, (uintmax_t)len, 1195 (uintmax_t)chip->nc_size)); 1196 return EINVAL; 1197 } 1198 1199 if (len % chip->nc_page_size != 0 || 1200 offset % chip->nc_page_size != 0) { 1201 return nand_flash_write_unaligned(self, 1202 offset, len, retlen, buf); 1203 } 1204 1205 pages = len / chip->nc_page_size; 1206 KASSERT(pages != 0); 1207 *retlen = 0; 1208 1209 addr = offset; 1210 bufp = buf; 1211 1212 mutex_enter(&sc->sc_device_lock); 1213 for (page = 0; page < pages; page++) { 1214 /* do we need this check here? */ 1215 if (nand_isbad(self, addr)) { 1216 aprint_error_dev(self, 1217 "nand_flash_write: bad block encountered\n"); 1218 1219 error = EIO; 1220 goto out; 1221 } 1222 1223 error = nand_program_page(self, addr, bufp); 1224 if (error) { 1225 goto out; 1226 } 1227 1228 addr += chip->nc_page_size; 1229 bufp += chip->nc_page_size; 1230 *retlen += chip->nc_page_size; 1231 } 1232 out: 1233 mutex_exit(&sc->sc_device_lock); 1234 DPRINTF(("page programming: retlen: %" PRIu32 ", len: %" PRIu32 "\n", *retlen, len)); 1235 1236 return error; 1237 } 1238 1239 /* 1240 * handle (page) unaligned read from nand 1241 */ 1242 static int 1243 nand_flash_read_unaligned(device_t self, size_t offset, 1244 size_t len, size_t *retlen, uint8_t *buf) 1245 { 1246 struct nand_softc *sc = device_private(self); 1247 struct nand_chip *chip = &sc->sc_chip; 1248 daddr_t first, last, count, firstoff; 1249 uint8_t *bufp; 1250 daddr_t addr; 1251 size_t left; 1252 int error = 0, i; 1253 1254 first = offset & chip->nc_page_mask; 1255 firstoff = offset & ~chip->nc_page_mask; 1256 last = (offset + len) & chip->nc_page_mask; 1257 count = (last - first) / chip->nc_page_size + 1; 1258 1259 addr = first; 1260 bufp = buf; 1261 left = len; 1262 *retlen = 0; 1263 1264 mutex_enter(&sc->sc_device_lock); 1265 if (count == 1) { 1266 error = nand_read_page(self, addr, chip->nc_page_cache); 1267 if (error) { 1268 goto out; 1269 } 1270 1271 memcpy(bufp, chip->nc_page_cache + firstoff, len); 1272 1273 *retlen = len; 1274 goto out; 1275 } 1276 1277 for (i = 0; i < count && left != 0; i++) { 1278 error = nand_read_page(self, addr, chip->nc_page_cache); 1279 if (error) { 1280 goto out; 1281 } 1282 1283 if (i == 0) { 1284 memcpy(bufp, chip->nc_page_cache + firstoff, 1285 chip->nc_page_size - firstoff); 1286 1287 bufp += chip->nc_page_size - firstoff; 1288 left -= chip->nc_page_size - firstoff; 1289 *retlen += chip->nc_page_size - firstoff; 1290 1291 } else if (i == count - 1) { 1292 memcpy(bufp, chip->nc_page_cache, left); 1293 *retlen += left; 1294 KASSERT(left < chip->nc_page_size); 1295 1296 } else { 1297 memcpy(bufp, chip->nc_page_cache, chip->nc_page_size); 1298 1299 bufp += chip->nc_page_size; 1300 left -= chip->nc_page_size; 1301 *retlen += chip->nc_page_size; 1302 } 1303 1304 addr += chip->nc_page_size; 1305 } 1306 KASSERT(*retlen == len); 1307 out: 1308 mutex_exit(&sc->sc_device_lock); 1309 1310 return error; 1311 } 1312 1313 int 1314 nand_flash_read(device_t self, flash_off_t offset, size_t len, size_t *retlen, 1315 uint8_t *buf) 1316 { 1317 struct nand_softc *sc = device_private(self); 1318 struct nand_chip *chip = &sc->sc_chip; 1319 uint8_t *bufp; 1320 size_t addr; 1321 size_t i, pages; 1322 int error = 0; 1323 1324 *retlen = 0; 1325 1326 DPRINTF(("nand_flash_read: off: 0x%jx, len: %" PRIu32 "\n", 1327 (uintmax_t)offset, len)); 1328 1329 if (__predict_false((offset + len) > chip->nc_size)) { 1330 DPRINTF(("nand_flash_read: read (off: 0x%jx, len: %" PRIu32 ")," 1331 " is over device size (%ju)\n", (uintmax_t)offset, 1332 len, (uintmax_t)chip->nc_size)); 1333 return EINVAL; 1334 } 1335 1336 /* Handle unaligned access, shouldnt be needed when using the 1337 * block device, as strategy handles it, so only low level 1338 * accesses will use this path 1339 */ 1340 /* XXX^2 */ 1341 #if 0 1342 if (len < chip->nc_page_size) 1343 panic("TODO page size is larger than read size"); 1344 #endif 1345 1346 if (len % chip->nc_page_size != 0 || 1347 offset % chip->nc_page_size != 0) { 1348 return nand_flash_read_unaligned(self, 1349 offset, len, retlen, buf); 1350 } 1351 1352 bufp = buf; 1353 addr = offset; 1354 pages = len / chip->nc_page_size; 1355 1356 mutex_enter(&sc->sc_device_lock); 1357 for (i = 0; i < pages; i++) { 1358 /* XXX do we need this check here? */ 1359 if (nand_isbad(self, addr)) { 1360 aprint_error_dev(self, "bad block encountered\n"); 1361 error = EIO; 1362 goto out; 1363 } 1364 error = nand_read_page(self, addr, bufp); 1365 if (error) 1366 goto out; 1367 1368 bufp += chip->nc_page_size; 1369 addr += chip->nc_page_size; 1370 *retlen += chip->nc_page_size; 1371 } 1372 out: 1373 mutex_exit(&sc->sc_device_lock); 1374 1375 return error; 1376 } 1377 1378 int 1379 nand_flash_isbad(device_t self, flash_off_t ofs, bool *is_bad) 1380 { 1381 struct nand_softc *sc = device_private(self); 1382 struct nand_chip *chip = &sc->sc_chip; 1383 bool result; 1384 1385 if (ofs > chip->nc_size) { 1386 DPRINTF(("nand_flash_isbad: offset 0x%jx is larger than" 1387 " device size (0x%jx)\n", (uintmax_t)ofs, 1388 (uintmax_t)chip->nc_size)); 1389 return EINVAL; 1390 } 1391 1392 if (ofs % chip->nc_block_size != 0) { 1393 DPRINTF(("offset (0x%jx) is not a multiple of block size " 1394 "(%ju)", 1395 (uintmax_t)ofs, (uintmax_t)chip->nc_block_size)); 1396 return EINVAL; 1397 } 1398 1399 mutex_enter(&sc->sc_device_lock); 1400 result = nand_isbad(self, ofs); 1401 mutex_exit(&sc->sc_device_lock); 1402 1403 *is_bad = result; 1404 1405 return 0; 1406 } 1407 1408 int 1409 nand_flash_markbad(device_t self, flash_off_t ofs) 1410 { 1411 struct nand_softc *sc = device_private(self); 1412 struct nand_chip *chip = &sc->sc_chip; 1413 1414 if (ofs > chip->nc_size) { 1415 DPRINTF(("nand_flash_markbad: offset 0x%jx is larger than" 1416 " device size (0x%jx)\n", ofs, 1417 (uintmax_t)chip->nc_size)); 1418 return EINVAL; 1419 } 1420 1421 if (ofs % chip->nc_block_size != 0) { 1422 panic("offset (%ju) is not a multiple of block size (%ju)", 1423 (uintmax_t)ofs, (uintmax_t)chip->nc_block_size); 1424 } 1425 1426 mutex_enter(&sc->sc_device_lock); 1427 nand_markbad(self, ofs); 1428 mutex_exit(&sc->sc_device_lock); 1429 1430 return 0; 1431 } 1432 1433 int 1434 nand_flash_erase(device_t self, 1435 struct flash_erase_instruction *ei) 1436 { 1437 struct nand_softc *sc = device_private(self); 1438 struct nand_chip *chip = &sc->sc_chip; 1439 flash_off_t addr; 1440 int error = 0; 1441 1442 if (ei->ei_addr < 0 || ei->ei_len < chip->nc_block_size) 1443 return EINVAL; 1444 1445 if (ei->ei_addr + ei->ei_len > chip->nc_size) { 1446 DPRINTF(("nand_flash_erase: erase address is over the end" 1447 " of the device\n")); 1448 return EINVAL; 1449 } 1450 1451 if (ei->ei_addr % chip->nc_block_size != 0) { 1452 aprint_error_dev(self, 1453 "nand_flash_erase: ei_addr (%ju) is not" 1454 " a multiple of block size (%ju)", 1455 (uintmax_t)ei->ei_addr, 1456 (uintmax_t)chip->nc_block_size); 1457 return EINVAL; 1458 } 1459 1460 if (ei->ei_len % chip->nc_block_size != 0) { 1461 aprint_error_dev(self, 1462 "nand_flash_erase: ei_len (%ju) is not" 1463 " a multiple of block size (%ju)", 1464 (uintmax_t)ei->ei_len, 1465 (uintmax_t)chip->nc_block_size); 1466 return EINVAL; 1467 } 1468 1469 mutex_enter(&sc->sc_device_lock); 1470 addr = ei->ei_addr; 1471 while (addr < ei->ei_addr + ei->ei_len) { 1472 if (nand_isbad(self, addr)) { 1473 aprint_error_dev(self, "bad block encountered\n"); 1474 ei->ei_state = FLASH_ERASE_FAILED; 1475 error = EIO; 1476 goto out; 1477 } 1478 1479 error = nand_erase_block(self, addr); 1480 if (error) { 1481 ei->ei_state = FLASH_ERASE_FAILED; 1482 goto out; 1483 } 1484 1485 addr += chip->nc_block_size; 1486 } 1487 mutex_exit(&sc->sc_device_lock); 1488 1489 ei->ei_state = FLASH_ERASE_DONE; 1490 if (ei->ei_callback != NULL) { 1491 ei->ei_callback(ei); 1492 } 1493 1494 return 0; 1495 out: 1496 mutex_exit(&sc->sc_device_lock); 1497 1498 return error; 1499 } 1500 1501 MODULE(MODULE_CLASS_DRIVER, nand, "flash"); 1502 1503 #ifdef _MODULE 1504 #include "ioconf.c" 1505 #endif 1506 1507 static int 1508 nand_modcmd(modcmd_t cmd, void *opaque) 1509 { 1510 switch (cmd) { 1511 case MODULE_CMD_INIT: 1512 #ifdef _MODULE 1513 return config_init_component(cfdriver_ioconf_nand, 1514 cfattach_ioconf_nand, cfdata_ioconf_nand); 1515 #else 1516 return 0; 1517 #endif 1518 case MODULE_CMD_FINI: 1519 #ifdef _MODULE 1520 return config_fini_component(cfdriver_ioconf_nand, 1521 cfattach_ioconf_nand, cfdata_ioconf_nand); 1522 #else 1523 return 0; 1524 #endif 1525 default: 1526 return ENOTTY; 1527 } 1528 } 1529