1 /* $NetBSD: vme_two_isr.c,v 1.3 2003/03/07 12:40:12 he Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Split off from vme_two.c specifically to deal with hardware assisted 41 * soft interrupts when the user hasn't specified `vmetwo0' in the 42 * kernel config file (mvme1[67]2 only). 43 */ 44 45 #include "vmetwo.h" 46 47 #include <sys/param.h> 48 #include <sys/kernel.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 #include <sys/lock.h> 53 54 #include <machine/cpu.h> 55 #include <machine/bus.h> 56 57 #include <dev/vme/vmereg.h> 58 #include <dev/vme/vmevar.h> 59 60 #include <dev/mvme/mvmebus.h> 61 #include <dev/mvme/vme_tworeg.h> 62 #include <dev/mvme/vme_twovar.h> 63 64 /* 65 * Non-zero if there is no VMEChip2 on this board. 66 */ 67 int vmetwo_not_present; 68 69 /* 70 * Array of interrupt handlers registered with us for the non-VMEbus 71 * vectored interrupts. Eg. ABORT Switch, SYSFAIL etc. 72 * 73 * We can't just install a caller's handler directly, since these 74 * interrupts have to be manually cleared, so we have a trampoline 75 * which does the clearing automatically. 76 */ 77 static struct vme_two_handler { 78 int (*isr_hand) __P((void *)); 79 void *isr_arg; 80 } vme_two_handlers[(VME2_VECTOR_LOCAL_MAX - VME2_VECTOR_LOCAL_MIN) + 1]; 81 82 #define VMETWO_HANDLERS_SZ (sizeof(vme_two_handlers) / \ 83 sizeof(struct vme_two_handler)) 84 85 static int vmetwo_local_isr_trampoline(void *); 86 static void vmetwo_softintr_assert(void); 87 88 static struct vmetwo_softc *vmetwo_sc; 89 90 int 91 vmetwo_probe(bus_space_tag_t bt, bus_addr_t offset) 92 { 93 bus_space_handle_t bh; 94 95 bus_space_map(bt, offset + VME2REG_LCSR_OFFSET, VME2LCSR_SIZE, 0, &bh); 96 97 if (bus_space_peek_4(bt, bh, VME2LCSR_MISC_STATUS, NULL) != 0) { 98 #if defined(MVME162) || defined(MVME172) 99 #if defined(MVME167) || defined(MVME177) 100 if (machineid == MVME_162 || machineid == MVME_172) 101 #endif 102 { 103 /* 104 * No VMEChip2 on mvme162/172 is not too big a 105 * deal; we can fall back on timer4 in the 106 * mcchip for h/w assisted soft interrupts... 107 */ 108 extern void pcctwosoftintrinit(void); 109 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 110 vmetwo_not_present = 1; 111 pcctwosoftintrinit(); 112 return (0); 113 } 114 #endif 115 #if defined(MVME167) || defined(MVME177) || defined(MVME88K) 116 /* 117 * No VMEChip2 on mvme167/177, however, is a Big Deal. 118 * In fact, it means the hardware's shot since the 119 * VMEChip2 is not a `build-option' on those boards. 120 */ 121 panic("VMEChip2 not responding! Faulty board?"); 122 /* NOTREACHED */ 123 #endif 124 #if defined(MVMEPPC) 125 /* 126 * No VMEChip2 on mvmeppc is no big deal. 127 */ 128 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 129 vmetwo_not_present = 1; 130 return (0); 131 #endif 132 } 133 #if NVMETWO == 0 134 else { 135 /* 136 * The kernel config file has no `vmetwo0' device, but 137 * there is a VMEChip2 on the board. Fix up things 138 * just enough to hook VMEChip2 local interrupts. 139 */ 140 struct vmetwo_softc *sc; 141 142 /* XXX Should check sc != NULL here... */ 143 MALLOC(sc, struct vmetwo_softc *, sizeof(*sc), M_DEVBUF, 144 M_NOWAIT); 145 146 sc->sc_mvmebus.sc_bust = bt; 147 sc->sc_lcrh = bh; 148 vmetwo_intr_init(sc); 149 return 0; 150 } 151 #else 152 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 153 return (1); 154 #endif 155 } 156 157 void 158 vmetwo_intr_init(struct vmetwo_softc *sc) 159 { 160 u_int32_t reg; 161 int i; 162 163 vmetwo_sc = sc; 164 165 /* Clear out the ISR handler array */ 166 for (i = 0; i < VMETWO_HANDLERS_SZ; i++) 167 vme_two_handlers[i].isr_hand = NULL; 168 169 /* 170 * Initialize the chip. 171 * Firstly, disable all VMEChip2 Interrupts 172 */ 173 reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN; 174 vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg); 175 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, 0); 176 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 177 VME2_LOCAL_INTERRUPT_CLEAR_ALL); 178 179 /* Zap all the IRQ level registers */ 180 for (i = 0; i < VME2_NUM_IL_REGS; i++) 181 vme2_lcsr_write(sc, VME2LCSR_INTERRUPT_LEVEL_BASE + (i * 4), 0); 182 183 /* Disable the tick timers */ 184 reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL); 185 reg &= ~VME2_TIMER_CONTROL_EN(0); 186 reg &= ~VME2_TIMER_CONTROL_EN(1); 187 vme2_lcsr_write(sc, VME2LCSR_TIMER_CONTROL, reg); 188 189 /* Set the VMEChip2's vector base register to the required value */ 190 reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE); 191 reg &= ~VME2_VECTOR_BASE_MASK; 192 reg |= VME2_VECTOR_BASE_REG_VALUE; 193 vme2_lcsr_write(sc, VME2LCSR_VECTOR_BASE, reg); 194 195 /* Set the Master Interrupt Enable bit now */ 196 reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN; 197 vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg); 198 199 /* Allow the MD code the chance to do some initialising */ 200 vmetwo_md_intr_init(sc); 201 202 #if defined(MVME167) || defined(MVME177) 203 #if defined(MVME162) || defined(MVME172) 204 if (machineid != MVME_162 && machineid != MVME_172) 205 #endif 206 { 207 /* 208 * Let the NMI handler deal with level 7 ABORT switch 209 * interrupts 210 */ 211 vmetwo_intr_establish(sc, 7, 7, VME2_VEC_ABORT, 1, 212 nmihand, NULL, NULL); 213 } 214 #endif 215 216 /* Setup hardware assisted soft interrupts */ 217 vmetwo_intr_establish(sc, 1, 1, VME2_VEC_SOFT0, 1, 218 (int (*)(void *))softintr_dispatch, NULL, NULL); 219 _softintr_chipset_assert = vmetwo_softintr_assert; 220 } 221 222 static int 223 vmetwo_local_isr_trampoline(arg) 224 void *arg; 225 { 226 struct vme_two_handler *isr; 227 int vec; 228 229 vec = (int) arg; /* 0x08 <= vec <= 0x1f */ 230 231 /* Clear the interrupt source */ 232 vme2_lcsr_write(vmetwo_sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 233 VME2_LOCAL_INTERRUPT(vec)); 234 235 isr = &vme_two_handlers[vec - VME2_VECTOR_LOCAL_OFFSET]; 236 if (isr->isr_hand) 237 (void) (*isr->isr_hand) (isr->isr_arg); 238 else 239 printf("vmetwo: Spurious local interrupt, vector 0x%x\n", vec); 240 241 return (1); 242 } 243 244 void 245 vmetwo_local_intr_establish(pri, vec, hand, arg, evcnt) 246 int pri, vec; 247 int (*hand)(void *); 248 void *arg; 249 struct evcnt *evcnt; 250 { 251 252 vmetwo_intr_establish(vmetwo_sc, pri, pri, vec, 1, hand, arg, evcnt); 253 } 254 255 /* ARGSUSED */ 256 void 257 vmetwo_intr_establish(csc, prior, lvl, vec, first, hand, arg, evcnt) 258 void *csc; 259 int prior, lvl, vec, first; 260 int (*hand)(void *); 261 void *arg; 262 struct evcnt *evcnt; 263 { 264 struct vmetwo_softc *sc = csc; 265 u_int32_t reg; 266 int bitoff; 267 int iloffset, ilshift; 268 int s; 269 270 s = splhigh(); 271 272 #if NVMETWO > 0 273 /* 274 * Sort out interrupts generated locally by the VMEChip2 from 275 * those generated by VMEbus devices... 276 */ 277 if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) { 278 #endif 279 /* 280 * Local interrupts need to be bounced through some 281 * trampoline code which acknowledges/clears them. 282 */ 283 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = hand; 284 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_arg = arg; 285 hand = vmetwo_local_isr_trampoline; 286 arg = (void *) (vec - VME2_VECTOR_BASE); 287 288 /* 289 * Interrupt enable/clear bit offset is 0x08 - 0x1f 290 */ 291 bitoff = vec - VME2_VECTOR_BASE; 292 #if NVMETWO > 0 293 first = 1; /* Force the interrupt to be enabled */ 294 } else { 295 /* 296 * Interrupts originating from the VMEbus are 297 * controlled by an offset of 0x00 - 0x07 298 */ 299 bitoff = lvl - 1; 300 } 301 #endif 302 303 /* Hook the interrupt */ 304 (*sc->sc_isrlink)(sc->sc_isrcookie, hand, arg, prior, vec, evcnt); 305 306 /* 307 * Do we need to tell the VMEChip2 to let the interrupt through? 308 * (This is always true for locally-generated interrupts, but only 309 * needs doing once for each VMEbus interrupt level which is hooked) 310 */ 311 #if NVMETWO > 0 312 if (first) { 313 if (evcnt) 314 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 315 (*sc->sc_isrevcnt)(sc->sc_isrcookie, prior), 316 sc->sc_mvmebus.sc_dev.dv_xname, 317 mvmebus_irq_name[lvl]); 318 #endif 319 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 320 VME2LCSR_INTERRUPT_LEVEL_BASE; 321 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 322 323 /* Program the specified interrupt to signal at 'prior' */ 324 reg = vme2_lcsr_read(sc, iloffset); 325 reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift); 326 reg |= (prior << ilshift); 327 vme2_lcsr_write(sc, iloffset, reg); 328 329 /* Clear it */ 330 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 331 VME2_LOCAL_INTERRUPT(bitoff)); 332 333 /* Enable it. */ 334 reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE); 335 reg |= VME2_LOCAL_INTERRUPT(bitoff); 336 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg); 337 #if NVMETWO > 0 338 } 339 #ifdef DIAGNOSTIC 340 else { 341 /* Verify the interrupt priority is the same */ 342 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 343 VME2LCSR_INTERRUPT_LEVEL_BASE; 344 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 345 346 reg = vme2_lcsr_read(sc, iloffset); 347 reg &= (VME2_INTERRUPT_LEVEL_MASK << ilshift); 348 349 if ((prior << ilshift) != reg) 350 panic("vmetwo_intr_establish: priority mismatch!"); 351 } 352 #endif 353 #endif 354 splx(s); 355 } 356 357 void 358 vmetwo_intr_disestablish(csc, lvl, vec, last, evcnt) 359 void *csc; 360 int lvl, vec, last; 361 struct evcnt *evcnt; 362 { 363 struct vmetwo_softc *sc = csc; 364 u_int32_t reg; 365 int iloffset, ilshift; 366 int bitoff; 367 int s; 368 369 s = splhigh(); 370 371 #if NVMETWO > 0 372 /* 373 * Sort out interrupts generated locally by the VMEChip2 from 374 * those generated by VMEbus devices... 375 */ 376 if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) { 377 #endif 378 /* 379 * Interrupt enable/clear bit offset is 0x08 - 0x1f 380 */ 381 bitoff = vec - VME2_VECTOR_BASE; 382 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = NULL; 383 last = 1; /* Force the interrupt to be cleared */ 384 #if NVMETWO > 0 385 } else { 386 /* 387 * Interrupts originating from the VMEbus are 388 * controlled by an offset of 0x00 - 0x07 389 */ 390 bitoff = lvl - 1; 391 } 392 #endif 393 394 /* 395 * Do we need to tell the VMEChip2 to block the interrupt? 396 * (This is always true for locally-generated interrupts, but only 397 * needs doing once when the last VMEbus handler for any given level 398 * has been unhooked.) 399 */ 400 if (last) { 401 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 402 VME2LCSR_INTERRUPT_LEVEL_BASE; 403 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 404 405 /* Disable it. */ 406 reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE); 407 reg &= ~VME2_LOCAL_INTERRUPT(bitoff); 408 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg); 409 410 /* Set the interrupt's level to zero */ 411 reg = vme2_lcsr_read(sc, iloffset); 412 reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift); 413 vme2_lcsr_write(sc, iloffset, reg); 414 415 /* Clear it */ 416 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 417 VME2_LOCAL_INTERRUPT(vec)); 418 419 if (evcnt) 420 evcnt_detach(evcnt); 421 } 422 /* Un-hook it */ 423 (*sc->sc_isrunlink)(sc->sc_isrcookie, vec); 424 425 splx(s); 426 } 427 428 static void 429 vmetwo_softintr_assert(void) 430 { 431 432 vme2_lcsr_write(vmetwo_sc, VME2LCSR_SOFTINT_SET, VME2_SOFTINT_SET(0)); 433 } 434