1 /* $NetBSD: rgephy.c,v 1.35 2013/12/17 16:00:23 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.35 2013/12/17 16:00:23 martin Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(device_t, cfdata_t, void *); 62 static void rgephy_attach(device_t, device_t, void *); 63 64 struct rgephy_softc { 65 struct mii_softc mii_sc; 66 }; 67 68 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 69 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 70 71 72 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 73 static void rgephy_status(struct mii_softc *); 74 static int rgephy_mii_phy_auto(struct mii_softc *); 75 static void rgephy_reset(struct mii_softc *); 76 static void rgephy_loop(struct mii_softc *); 77 static void rgephy_load_dspcode(struct mii_softc *); 78 79 static const struct mii_phy_funcs rgephy_funcs = { 80 rgephy_service, rgephy_status, rgephy_reset, 81 }; 82 83 static const struct mii_phydesc rgephys[] = { 84 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 85 MII_STR_xxREALTEK_RTL8169S }, 86 87 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 88 MII_STR_REALTEK_RTL8169S }, 89 90 { 0, 0, 91 NULL } 92 }; 93 94 static int 95 rgephy_match(device_t parent, cfdata_t match, void *aux) 96 { 97 struct mii_attach_args *ma = aux; 98 99 if (mii_phy_match(ma, rgephys) != NULL) 100 return 10; 101 102 return 0; 103 } 104 105 static void 106 rgephy_attach(device_t parent, device_t self, void *aux) 107 { 108 struct rgephy_softc *rsc = device_private(self); 109 struct mii_softc *sc = &rsc->mii_sc; 110 struct mii_attach_args *ma = aux; 111 struct mii_data *mii = ma->mii_data; 112 const struct mii_phydesc *mpd; 113 int rev; 114 const char *sep = ""; 115 116 ma = aux; 117 mii = ma->mii_data; 118 119 rev = MII_REV(ma->mii_id2); 120 mpd = mii_phy_match(ma, rgephys); 121 aprint_naive(": Media interface\n"); 122 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 123 124 sc->mii_dev = self; 125 sc->mii_inst = mii->mii_instance; 126 sc->mii_phy = ma->mii_phyno; 127 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 128 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 129 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 130 sc->mii_pdata = mii; 131 sc->mii_flags = mii->mii_flags; 132 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 133 134 sc->mii_funcs = &rgephy_funcs; 135 136 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 137 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 138 139 #ifdef __FreeBSD__ 140 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 141 BMCR_LOOP|BMCR_S100); 142 #endif 143 144 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 145 sc->mii_capabilities &= ~BMSR_ANEG; 146 147 /* 148 * FreeBSD does not check EXSTAT, but instead adds gigabit 149 * media explicitly. Why? 150 */ 151 aprint_normal_dev(self, ""); 152 if (sc->mii_capabilities & BMSR_EXTSTAT) { 153 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 154 } 155 mii_phy_add_media(sc); 156 157 /* rtl8169S does not report auto-sense; add manually. */ 158 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 159 sep =", "; 160 PRINT("auto"); 161 162 #undef ADD 163 #undef PRINT 164 165 rgephy_reset(sc); 166 aprint_normal("\n"); 167 } 168 169 static int 170 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 171 { 172 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 173 int reg, speed, gig, anar; 174 175 switch (cmd) { 176 case MII_POLLSTAT: 177 /* 178 * If we're not polling our PHY instance, just return. 179 */ 180 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 181 return 0; 182 break; 183 184 case MII_MEDIACHG: 185 /* 186 * If the media indicates a different PHY instance, 187 * isolate ourselves. 188 */ 189 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 190 reg = PHY_READ(sc, MII_BMCR); 191 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 192 return 0; 193 } 194 195 /* 196 * If the interface is not up, don't do anything. 197 */ 198 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 199 break; 200 201 rgephy_reset(sc); /* XXX hardware bug work-around */ 202 203 anar = PHY_READ(sc, MII_ANAR); 204 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 205 206 switch (IFM_SUBTYPE(ife->ifm_media)) { 207 case IFM_AUTO: 208 #ifdef foo 209 /* 210 * If we're already in auto mode, just return. 211 */ 212 if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN) 213 return 0; 214 #endif 215 (void)rgephy_mii_phy_auto(sc); 216 break; 217 case IFM_1000_T: 218 speed = BMCR_S1000; 219 goto setit; 220 case IFM_100_TX: 221 speed = BMCR_S100; 222 anar |= ANAR_TX_FD | ANAR_TX; 223 goto setit; 224 case IFM_10_T: 225 speed = BMCR_S10; 226 anar |= ANAR_10_FD | ANAR_10; 227 setit: 228 rgephy_loop(sc); 229 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 230 speed |= BMCR_FDX; 231 gig = GTCR_ADV_1000TFDX; 232 anar &= ~(ANAR_TX | ANAR_10); 233 } else { 234 gig = GTCR_ADV_1000THDX; 235 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 236 } 237 238 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 239 PHY_WRITE(sc, MII_100T2CR, 0); 240 PHY_WRITE(sc, MII_ANAR, anar); 241 PHY_WRITE(sc, MII_BMCR, speed | 242 BMCR_AUTOEN | BMCR_STARTNEG); 243 break; 244 } 245 246 /* 247 * When setting the link manually, one side must 248 * be the master and the other the slave. However 249 * ifmedia doesn't give us a good way to specify 250 * this, so we fake it by using one of the LINK 251 * flags. If LINK0 is set, we program the PHY to 252 * be a master, otherwise it's a slave. 253 */ 254 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 255 PHY_WRITE(sc, MII_100T2CR, 256 gig|GTCR_MAN_MS|GTCR_ADV_MS); 257 } else { 258 PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS); 259 } 260 PHY_WRITE(sc, MII_BMCR, speed | 261 BMCR_AUTOEN | BMCR_STARTNEG); 262 break; 263 case IFM_NONE: 264 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 265 break; 266 case IFM_100_T4: 267 default: 268 return EINVAL; 269 } 270 break; 271 272 case MII_TICK: 273 /* 274 * If we're not currently selected, just return. 275 */ 276 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 277 return 0; 278 279 /* 280 * Is the interface even up? 281 */ 282 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 283 return 0; 284 285 /* 286 * Only used for autonegotiation. 287 */ 288 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 289 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 290 /* 291 * Reset autonegotiation timer to 0 to make sure 292 * the future autonegotiation start with 0. 293 */ 294 sc->mii_ticks = 0; 295 break; 296 } 297 298 /* 299 * Check to see if we have link. If we do, we don't 300 * need to restart the autonegotiation process. Read 301 * the BMSR twice in case it's latched. 302 */ 303 if (sc->mii_mpd_rev >= 2) { 304 /* RTL8211B(L) */ 305 reg = PHY_READ(sc, RGEPHY_MII_SSR); 306 if (reg & RGEPHY_SSR_LINK) { 307 sc->mii_ticks = 0; 308 break; 309 } 310 } else { 311 reg = PHY_READ(sc, RTK_GMEDIASTAT); 312 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 313 sc->mii_ticks = 0; 314 break; 315 } 316 } 317 318 /* Announce link loss right after it happens. */ 319 if (sc->mii_ticks++ == 0) 320 break; 321 322 /* Only retry autonegotiation every mii_anegticks seconds. */ 323 if (sc->mii_ticks <= sc->mii_anegticks) 324 return 0; 325 326 rgephy_mii_phy_auto(sc); 327 break; 328 } 329 330 /* Update the media status. */ 331 rgephy_status(sc); 332 333 /* 334 * Callback if something changed. Note that we need to poke 335 * the DSP on the RealTek PHYs if the media changes. 336 * 337 */ 338 if (sc->mii_media_active != mii->mii_media_active || 339 sc->mii_media_status != mii->mii_media_status || 340 cmd == MII_MEDIACHG) { 341 rgephy_load_dspcode(sc); 342 } 343 mii_phy_update(sc, cmd); 344 return 0; 345 } 346 347 static void 348 rgephy_status(struct mii_softc *sc) 349 { 350 struct mii_data *mii = sc->mii_pdata; 351 int gstat, bmsr, bmcr; 352 uint16_t ssr; 353 354 mii->mii_media_status = IFM_AVALID; 355 mii->mii_media_active = IFM_ETHER; 356 357 if (sc->mii_mpd_rev >= 2) { 358 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 359 if (ssr & RGEPHY_SSR_LINK) 360 mii->mii_media_status |= IFM_ACTIVE; 361 } else { 362 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 363 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 364 mii->mii_media_status |= IFM_ACTIVE; 365 } 366 367 bmsr = PHY_READ(sc, MII_BMSR); 368 bmcr = PHY_READ(sc, MII_BMCR); 369 370 if ((bmcr & BMCR_ISO) != 0) { 371 mii->mii_media_active |= IFM_NONE; 372 mii->mii_media_status = 0; 373 return; 374 } 375 376 if ((bmcr & BMCR_LOOP) != 0) 377 mii->mii_media_active |= IFM_LOOP; 378 379 if ((bmcr & BMCR_AUTOEN) != 0) { 380 if ((bmsr & BMSR_ACOMP) == 0) { 381 /* Erg, still trying, I guess... */ 382 mii->mii_media_active |= IFM_NONE; 383 return; 384 } 385 } 386 387 if (sc->mii_mpd_rev >= 2) { 388 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 389 switch (ssr & RGEPHY_SSR_SPD_MASK) { 390 case RGEPHY_SSR_S1000: 391 mii->mii_media_active |= IFM_1000_T; 392 break; 393 case RGEPHY_SSR_S100: 394 mii->mii_media_active |= IFM_100_TX; 395 break; 396 case RGEPHY_SSR_S10: 397 mii->mii_media_active |= IFM_10_T; 398 break; 399 default: 400 mii->mii_media_active |= IFM_NONE; 401 break; 402 } 403 if (ssr & RGEPHY_SSR_FDX) 404 mii->mii_media_active |= mii_phy_flowstatus(sc) | 405 IFM_FDX; 406 else 407 mii->mii_media_active |= IFM_HDX; 408 } else { 409 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 410 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 411 mii->mii_media_active |= IFM_1000_T; 412 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 413 mii->mii_media_active |= IFM_100_TX; 414 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 415 mii->mii_media_active |= IFM_10_T; 416 else 417 mii->mii_media_active |= IFM_NONE; 418 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 419 mii->mii_media_active |= mii_phy_flowstatus(sc) | 420 IFM_FDX; 421 else 422 mii->mii_media_active |= IFM_HDX; 423 } 424 } 425 426 427 static int 428 rgephy_mii_phy_auto(struct mii_softc *mii) 429 { 430 int anar; 431 432 mii->mii_ticks = 0; 433 rgephy_loop(mii); 434 rgephy_reset(mii); 435 436 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 437 if (mii->mii_flags & MIIF_DOPAUSE) 438 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 439 440 PHY_WRITE(mii, MII_ANAR, anar); 441 DELAY(1000); 442 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 443 DELAY(1000); 444 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 445 DELAY(100); 446 447 return EJUSTRETURN; 448 } 449 450 static void 451 rgephy_loop(struct mii_softc *sc) 452 { 453 uint32_t bmsr; 454 int i; 455 456 if (sc->mii_mpd_rev < 2) { 457 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 458 DELAY(1000); 459 } 460 461 for (i = 0; i < 15000; i++) { 462 bmsr = PHY_READ(sc, MII_BMSR); 463 if ((bmsr & BMSR_LINK) == 0) { 464 #if 0 465 device_printf(sc->mii_dev, "looped %d\n", i); 466 #endif 467 break; 468 } 469 DELAY(10); 470 } 471 } 472 473 #define PHY_SETBIT(x, y, z) \ 474 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 475 #define PHY_CLRBIT(x, y, z) \ 476 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 477 478 /* 479 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 480 * existing revisions of the 8169S/8110S chips need to be tuned in 481 * order to reliably negotiate a 1000Mbps link. This is only needed 482 * for rev 0 and rev 1 of the PHY. Later versions work without 483 * any fixups. 484 */ 485 static void 486 rgephy_load_dspcode(struct mii_softc *sc) 487 { 488 int val; 489 490 if (sc->mii_mpd_rev >= 2) 491 return; 492 493 #if 1 494 PHY_WRITE(sc, 31, 0x0001); 495 PHY_WRITE(sc, 21, 0x1000); 496 PHY_WRITE(sc, 24, 0x65C7); 497 PHY_CLRBIT(sc, 4, 0x0800); 498 val = PHY_READ(sc, 4) & 0xFFF; 499 PHY_WRITE(sc, 4, val); 500 PHY_WRITE(sc, 3, 0x00A1); 501 PHY_WRITE(sc, 2, 0x0008); 502 PHY_WRITE(sc, 1, 0x1020); 503 PHY_WRITE(sc, 0, 0x1000); 504 PHY_SETBIT(sc, 4, 0x0800); 505 PHY_CLRBIT(sc, 4, 0x0800); 506 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 507 PHY_WRITE(sc, 4, val); 508 PHY_WRITE(sc, 3, 0xFF41); 509 PHY_WRITE(sc, 2, 0xDE60); 510 PHY_WRITE(sc, 1, 0x0140); 511 PHY_WRITE(sc, 0, 0x0077); 512 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 513 PHY_WRITE(sc, 4, val); 514 PHY_WRITE(sc, 3, 0xDF01); 515 PHY_WRITE(sc, 2, 0xDF20); 516 PHY_WRITE(sc, 1, 0xFF95); 517 PHY_WRITE(sc, 0, 0xFA00); 518 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 519 PHY_WRITE(sc, 4, val); 520 PHY_WRITE(sc, 3, 0xFF41); 521 PHY_WRITE(sc, 2, 0xDE20); 522 PHY_WRITE(sc, 1, 0x0140); 523 PHY_WRITE(sc, 0, 0x00BB); 524 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 525 PHY_WRITE(sc, 4, val); 526 PHY_WRITE(sc, 3, 0xDF01); 527 PHY_WRITE(sc, 2, 0xDF20); 528 PHY_WRITE(sc, 1, 0xFF95); 529 PHY_WRITE(sc, 0, 0xBF00); 530 PHY_SETBIT(sc, 4, 0x0800); 531 PHY_CLRBIT(sc, 4, 0x0800); 532 PHY_WRITE(sc, 31, 0x0000); 533 #else 534 (void)val; 535 PHY_WRITE(sc, 0x1f, 0x0001); 536 PHY_WRITE(sc, 0x15, 0x1000); 537 PHY_WRITE(sc, 0x18, 0x65c7); 538 PHY_WRITE(sc, 0x04, 0x0000); 539 PHY_WRITE(sc, 0x03, 0x00a1); 540 PHY_WRITE(sc, 0x02, 0x0008); 541 PHY_WRITE(sc, 0x01, 0x1020); 542 PHY_WRITE(sc, 0x00, 0x1000); 543 PHY_WRITE(sc, 0x04, 0x0800); 544 PHY_WRITE(sc, 0x04, 0x0000); 545 PHY_WRITE(sc, 0x04, 0x7000); 546 PHY_WRITE(sc, 0x03, 0xff41); 547 PHY_WRITE(sc, 0x02, 0xde60); 548 PHY_WRITE(sc, 0x01, 0x0140); 549 PHY_WRITE(sc, 0x00, 0x0077); 550 PHY_WRITE(sc, 0x04, 0x7800); 551 PHY_WRITE(sc, 0x04, 0x7000); 552 PHY_WRITE(sc, 0x04, 0xa000); 553 PHY_WRITE(sc, 0x03, 0xdf01); 554 PHY_WRITE(sc, 0x02, 0xdf20); 555 PHY_WRITE(sc, 0x01, 0xff95); 556 PHY_WRITE(sc, 0x00, 0xfa00); 557 PHY_WRITE(sc, 0x04, 0xa800); 558 PHY_WRITE(sc, 0x04, 0xa000); 559 PHY_WRITE(sc, 0x04, 0xb000); 560 PHY_WRITE(sc, 0x0e, 0xff41); 561 PHY_WRITE(sc, 0x02, 0xde20); 562 PHY_WRITE(sc, 0x01, 0x0140); 563 PHY_WRITE(sc, 0x00, 0x00bb); 564 PHY_WRITE(sc, 0x04, 0xb800); 565 PHY_WRITE(sc, 0x04, 0xb000); 566 PHY_WRITE(sc, 0x04, 0xf000); 567 PHY_WRITE(sc, 0x03, 0xdf01); 568 PHY_WRITE(sc, 0x02, 0xdf20); 569 PHY_WRITE(sc, 0x01, 0xff95); 570 PHY_WRITE(sc, 0x00, 0xbf00); 571 PHY_WRITE(sc, 0x04, 0xf800); 572 PHY_WRITE(sc, 0x04, 0xf000); 573 PHY_WRITE(sc, 0x04, 0x0000); 574 PHY_WRITE(sc, 0x1f, 0x0000); 575 PHY_WRITE(sc, 0x0b, 0x0000); 576 577 #endif 578 579 DELAY(40); 580 } 581 582 static void 583 rgephy_reset(struct mii_softc *sc) 584 { 585 uint16_t ssr; 586 587 mii_phy_reset(sc); 588 DELAY(1000); 589 590 if (sc->mii_mpd_rev < 2) { 591 rgephy_load_dspcode(sc); 592 } else if (sc->mii_mpd_rev == 3) { 593 /* RTL8211C(L) */ 594 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 595 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 596 ssr &= ~RGEPHY_SSR_ALDPS; 597 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 598 } 599 } else { 600 PHY_WRITE(sc, 0x1F, 0x0000); 601 PHY_WRITE(sc, 0x0e, 0x0000); 602 } 603 604 /* Reset capabilities */ 605 /* Step1: write our capability */ 606 /* 10/100 capability */ 607 PHY_WRITE(sc, MII_ANAR, 608 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 609 /* 1000 capability */ 610 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 611 612 /* Step2: Restart NWay */ 613 /* NWay enable and Restart NWay */ 614 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 615 } 616