1 /* $NetBSD: mii_bitbang.c,v 1.5 2001/11/13 07:41:37 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Common module for bit-bang'ing the MII. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: mii_bitbang.c,v 1.5 2001/11/13 07:41:37 lukem Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/device.h> 49 50 #include <dev/mii/mii.h> 51 #include <dev/mii/mii_bitbang.h> 52 53 void mii_bitbang_sync(struct device *, mii_bitbang_ops_t); 54 void mii_bitbang_sendbits(struct device *, mii_bitbang_ops_t, 55 u_int32_t, int); 56 57 #define WRITE(x) \ 58 do { \ 59 ops->mbo_write(sc, (x)); \ 60 delay(1); \ 61 } while (/* CONSTCOND */ 0) 62 63 #define READ ops->mbo_read(sc) 64 65 #define MDO ops->mbo_bits[MII_BIT_MDO] 66 #define MDI ops->mbo_bits[MII_BIT_MDI] 67 #define MDC ops->mbo_bits[MII_BIT_MDC] 68 #define MDIRPHY ops->mbo_bits[MII_BIT_DIR_HOST_PHY] 69 #define MDIRHOST ops->mbo_bits[MII_BIT_DIR_PHY_HOST] 70 71 /* 72 * mii_bitbang_sync: 73 * 74 * Synchronize the MII. 75 */ 76 void 77 mii_bitbang_sync(struct device *sc, mii_bitbang_ops_t ops) 78 { 79 int i; 80 u_int32_t v; 81 82 v = MDIRPHY | MDO; 83 84 WRITE(v); 85 for (i = 0; i < 32; i++) { 86 WRITE(v | MDC); 87 WRITE(v); 88 } 89 } 90 91 /* 92 * mii_bitbang_sendbits: 93 * 94 * Send a series of bits to the MII. 95 */ 96 void 97 mii_bitbang_sendbits(struct device *sc, mii_bitbang_ops_t ops, uint32_t data, 98 int nbits) 99 { 100 int i; 101 u_int32_t v; 102 103 v = MDIRPHY; 104 WRITE(v); 105 106 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 107 if (data & i) 108 v |= MDO; 109 else 110 v &= ~MDO; 111 WRITE(v); 112 WRITE(v | MDC); 113 WRITE(v); 114 } 115 } 116 117 /* 118 * mii_bitbang_readreg: 119 * 120 * Read a PHY register by bit-bang'ing the MII. 121 */ 122 int 123 mii_bitbang_readreg(struct device *sc, mii_bitbang_ops_t ops, int phy, int reg) 124 { 125 int val = 0, err = 0, i; 126 127 mii_bitbang_sync(sc, ops); 128 129 mii_bitbang_sendbits(sc, ops, MII_COMMAND_START, 2); 130 mii_bitbang_sendbits(sc, ops, MII_COMMAND_READ, 2); 131 mii_bitbang_sendbits(sc, ops, phy, 5); 132 mii_bitbang_sendbits(sc, ops, reg, 5); 133 134 /* Switch direction to PHY->host, without a clock transition. */ 135 WRITE(MDIRHOST); 136 137 /* Turnaround clock. */ 138 WRITE(MDIRHOST | MDC); 139 WRITE(MDIRHOST); 140 141 /* Check for error. */ 142 err = READ & MDI; 143 144 /* Idle clock. */ 145 WRITE(MDIRHOST | MDC); 146 WRITE(MDIRHOST); 147 148 for (i = 0; i < 16; i++) { 149 val <<= 1; 150 /* Read data prior to clock low-high transition. */ 151 if (err == 0 && (READ & MDI) != 0) 152 val |= 1; 153 154 WRITE(MDIRHOST | MDC); 155 WRITE(MDIRHOST); 156 } 157 158 /* Set direction to host->PHY, without a clock transition. */ 159 WRITE(MDIRPHY); 160 161 return (err ? 0 : val); 162 } 163 164 /* 165 * mii_bitbang_writereg: 166 * 167 * Write a PHY register by bit-bang'ing the MII. 168 */ 169 void 170 mii_bitbang_writereg(struct device *sc, mii_bitbang_ops_t ops, int phy, 171 int reg, int val) 172 { 173 174 mii_bitbang_sync(sc, ops); 175 176 mii_bitbang_sendbits(sc, ops, MII_COMMAND_START, 2); 177 mii_bitbang_sendbits(sc, ops, MII_COMMAND_WRITE, 2); 178 mii_bitbang_sendbits(sc, ops, phy, 5); 179 mii_bitbang_sendbits(sc, ops, reg, 5); 180 mii_bitbang_sendbits(sc, ops, MII_COMMAND_ACK, 2); 181 mii_bitbang_sendbits(sc, ops, val, 16); 182 183 WRITE(MDIRPHY); 184 } 185