xref: /netbsd-src/sys/dev/mii/micphy.c (revision f3cfa6f6ce31685c6c4a758bc430e69eb99f50a4)
1 /*	$NetBSD: micphy.c,v 1.8 2019/03/25 07:34:13 msaitoh Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9  * NASA Ames Research Center, and by Frank van der Linden.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
35  *
36  * Redistribution and use in source and binary forms, with or without
37  * modification, are permitted provided that the following conditions
38  * are met:
39  * 1. Redistributions of source code must retain the above copyright
40  *    notice, this list of conditions and the following disclaimer.
41  * 2. Redistributions in binary form must reproduce the above copyright
42  *    notice, this list of conditions and the following disclaimer in the
43  *    documentation and/or other materials provided with the distribution.
44  *
45  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
46  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
47  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
48  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
49  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
50  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
54  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55  */
56 
57 /*
58  * Driver for Micrel KSZ9021RN PHYs
59  */
60 
61 #include <sys/cdefs.h>
62 __KERNEL_RCSID(0, "$NetBSD: micphy.c,v 1.8 2019/03/25 07:34:13 msaitoh Exp $");
63 
64 #include "opt_mii.h"
65 
66 #include <sys/param.h>
67 #include <sys/systm.h>
68 #include <sys/kernel.h>
69 #include <sys/device.h>
70 #include <sys/socket.h>
71 #include <sys/errno.h>
72 
73 #include <net/if.h>
74 #include <net/if_media.h>
75 
76 #include <dev/mii/mii.h>
77 #include <dev/mii/miivar.h>
78 #include <dev/mii/miidevs.h>
79 
80 static int	micphymatch(device_t, cfdata_t, void *);
81 static void	micphyattach(device_t, device_t, void *);
82 static void	micphy_reset(struct mii_softc *);
83 static int	micphy_service(struct mii_softc *, struct mii_data *, int);
84 
85 CFATTACH_DECL3_NEW(micphy, sizeof(struct mii_softc),
86     micphymatch, micphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL,
87     DVF_DETACH_SHUTDOWN);
88 
89 static int	micphy_service(struct mii_softc *, struct mii_data *, int);
90 static void	micphy_fixup(struct mii_softc *, int, int, device_t);
91 
92 static const struct mii_phy_funcs micphy_funcs = {
93 	micphy_service, ukphy_status, micphy_reset,
94 };
95 
96 static const struct mii_phydesc micphys[] = {
97 	MII_PHY_DESC(MICREL, KSZ8081),
98 	MII_PHY_DESC(MICREL, KSZ9021RNI),
99 	MII_PHY_END,
100 };
101 
102 #define	MII_KSZ8081_PHYCTL2			0x1f
103 
104 static int
105 micphymatch(device_t parent, cfdata_t match, void *aux)
106 {
107 	struct mii_attach_args *ma = aux;
108 
109 	if (mii_phy_match(ma, micphys) != NULL)
110 		return 10;
111 
112 	return 1;
113 }
114 
115 static void
116 micphyattach(device_t parent, device_t self, void *aux)
117 {
118 	struct mii_softc *sc = device_private(self);
119 	struct mii_attach_args *ma = aux;
120 	struct mii_data *mii = ma->mii_data;
121 	int model = MII_MODEL(ma->mii_id2);
122 	int rev = MII_REV(ma->mii_id2);
123 	const struct mii_phydesc *mpd;
124 
125 	mpd = mii_phy_match(ma, micphys);
126 	aprint_naive(": Media interface\n");
127 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev);
128 
129 	sc->mii_dev = self;
130 	sc->mii_inst = mii->mii_instance;
131 	sc->mii_phy = ma->mii_phyno;
132 	sc->mii_funcs = &micphy_funcs;
133 	sc->mii_pdata = mii;
134 	sc->mii_flags = ma->mii_flags;
135 	sc->mii_anegticks = MII_ANEGTICKS;
136 
137 	PHY_RESET(sc);
138 
139 	micphy_fixup(sc, model, rev, parent);
140 
141 	PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
142 	sc->mii_capabilities &= ma->mii_capmask;
143 	if (sc->mii_capabilities & BMSR_EXTSTAT)
144 		PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
145 	aprint_normal_dev(self, "");
146 	if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
147 	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
148 		aprint_error("no media present");
149 	else
150 		mii_phy_add_media(sc);
151 	aprint_normal("\n");
152 }
153 
154 static void
155 micphy_reset(struct mii_softc *sc)
156 {
157 	uint16_t reg;
158 
159 	/*
160 	 * The 8081 has no "sticky bits" that survive a soft reset; several
161 	 * bits in the Phy Control Register 2 must be preserved across the
162 	 * reset. These bits are set up by the bootloader; they control how the
163 	 * phy interfaces to the board (such as clock frequency and LED
164 	 * behavior).
165 	 */
166 	if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8081)
167 		PHY_READ(sc, MII_KSZ8081_PHYCTL2, &reg);
168 	mii_phy_reset(sc);
169 	if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8081)
170 		PHY_WRITE(sc, MII_KSZ8081_PHYCTL2, reg);
171 }
172 
173 static int
174 micphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
175 {
176 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
177 	uint16_t reg;
178 
179 	switch (cmd) {
180 	case MII_POLLSTAT:
181 		/* If we're not polling our PHY instance, just return. */
182 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
183 			return 0;
184 		break;
185 
186 	case MII_MEDIACHG:
187 		/*
188 		 * If the media indicates a different PHY instance,
189 		 * isolate ourselves.
190 		 */
191 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
192 			PHY_READ(sc, MII_BMCR, &reg);
193 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
194 			return 0;
195 		}
196 
197 		/* If the interface is not up, don't do anything. */
198 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
199 			break;
200 
201 		mii_phy_setmedia(sc);
202 		break;
203 
204 	case MII_TICK:
205 		/* If we're not currently selected, just return. */
206 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
207 			return 0;
208 
209 		if (mii_phy_tick(sc) == EJUSTRETURN)
210 			return 0;
211 		break;
212 
213 	case MII_DOWN:
214 		mii_phy_down(sc);
215 		return 0;
216 	}
217 
218 	/* Update the media status. */
219 	mii_phy_status(sc);
220 
221 	/* Callback if something changed. */
222 	mii_phy_update(sc, cmd);
223 	return 0;
224 }
225 
226 #define XREG_CONTROL	0x0b
227 #define XREG_WRITE	0x0c
228 #define XREG_READ	0x0d
229 #define XREG_CTL_SEL_READ	0x0000
230 #define XREG_CTL_SEL_WRITE	0x8000
231 
232 #define REG_RGMII_CLOCK_AND_CONTROL	0x104
233 #define REG_RGMII_RX_DATA		0x105
234 
235 static void
236 micphy_writexreg(struct mii_softc *sc, uint32_t reg, uint32_t wval)
237 {
238 	uint16_t rval __debugused;
239 
240 	PHY_WRITE(sc, XREG_CONTROL, XREG_CTL_SEL_WRITE | reg);
241 	PHY_WRITE(sc, XREG_WRITE, wval);
242 	PHY_WRITE(sc, XREG_CONTROL, XREG_CTL_SEL_READ | reg);
243 	PHY_READ(sc, XREG_READ, &rval);
244 	KDASSERT(wval == rval);
245 }
246 
247 static void
248 micphy_fixup(struct mii_softc *sc, int model, int rev, device_t parent)
249 {
250 	switch (model) {
251 	case MII_MODEL_MICREL_KSZ9021RNI:
252 		if (!device_is_a(parent, "cpsw"))
253 			break;
254 
255 		aprint_normal_dev(sc->mii_dev,
256 		    "adjusting RGMII signal timing for cpsw\n");
257 
258 		// RGMII RX Data Pad Skew
259 		micphy_writexreg(sc, REG_RGMII_RX_DATA, 0x0000);
260 
261 		// RGMII Clock and Control Pad Skew
262 		micphy_writexreg(sc, REG_RGMII_CLOCK_AND_CONTROL, 0x9090);
263 
264 		break;
265 	default:
266 		break;
267 	}
268 
269 	return;
270 }
271