xref: /netbsd-src/sys/dev/mii/ihphy.c (revision bdc22b2e01993381dcefeff2bc9b56ca75a4235c)
1 /*	$NetBSD: ihphy.c,v 1.10 2016/11/02 07:01:54 msaitoh Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9  * NASA Ames Research Center, and by Frank van der Linden.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
35  *
36  * Redistribution and use in source and binary forms, with or without
37  * modification, are permitted provided that the following conditions
38  * are met:
39  * 1. Redistributions of source code must retain the above copyright
40  *    notice, this list of conditions and the following disclaimer.
41  * 2. Redistributions in binary form must reproduce the above copyright
42  *    notice, this list of conditions and the following disclaimer in the
43  *    documentation and/or other materials provided with the distribution.
44  *
45  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
46  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
47  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
48  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
49  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
50  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
54  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55  */
56 
57 /*
58  * Driver for Intel's 82577 (Hanksville) Ethernet 10/100/1000 PHY
59  * Data Sheet: http://download.intel.com/design/network/datashts/319439.pdf
60  */
61 
62 #include <sys/cdefs.h>
63 __KERNEL_RCSID(0, "$NetBSD: ihphy.c,v 1.10 2016/11/02 07:01:54 msaitoh Exp $");
64 
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/kernel.h>
68 #include <sys/device.h>
69 #include <sys/socket.h>
70 #include <sys/errno.h>
71 
72 #include <net/if.h>
73 #include <net/if_media.h>
74 
75 #include <dev/mii/mii.h>
76 #include <dev/mii/miivar.h>
77 #include <dev/mii/miidevs.h>
78 
79 #include <dev/mii/ihphyreg.h>
80 
81 static int	ihphymatch(device_t, cfdata_t, void *);
82 static void	ihphyattach(device_t, device_t, void *);
83 
84 CFATTACH_DECL3_NEW(ihphy, sizeof(struct mii_softc),
85     ihphymatch, ihphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL,
86     DVF_DETACH_SHUTDOWN);
87 
88 static int	ihphy_service(struct mii_softc *, struct mii_data *, int);
89 static void	ihphy_status(struct mii_softc *);
90 static void	ihphy_reset(struct mii_softc *);
91 
92 static const struct mii_phy_funcs ihphy_funcs = {
93 	ihphy_service, ihphy_status, ihphy_reset,
94 };
95 
96 static const struct mii_phydesc ihphys[] = {
97 	{ MII_OUI_INTEL,		MII_MODEL_INTEL_I82577,
98 	  MII_STR_INTEL_I82577 },
99 	{ MII_OUI_INTEL,		MII_MODEL_INTEL_I82579,
100 	  MII_STR_INTEL_I82579 },
101 	{ MII_OUI_INTEL,		MII_MODEL_INTEL_I217,
102 	  MII_STR_INTEL_I217 },
103 
104 	{ 0,				0,
105 	  NULL },
106 };
107 
108 static int
109 ihphymatch(device_t parent, cfdata_t match, void *aux)
110 {
111 	struct mii_attach_args *ma = aux;
112 
113 	if (mii_phy_match(ma, ihphys) != NULL)
114 		return 10;
115 
116 	return 0;
117 }
118 
119 static void
120 ihphyattach(device_t parent, device_t self, void *aux)
121 {
122 	struct mii_softc *sc = device_private(self);
123 	struct mii_attach_args *ma = aux;
124 	struct mii_data *mii = ma->mii_data;
125 	const struct mii_phydesc *mpd;
126 	int reg;
127 
128 	mpd = mii_phy_match(ma, ihphys);
129 	aprint_naive(": Media interface\n");
130 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
131 
132 	sc->mii_dev = self;
133 	sc->mii_inst = mii->mii_instance;
134 	sc->mii_phy = ma->mii_phyno;
135 	sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
136 	sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
137 	sc->mii_mpd_rev = MII_REV(ma->mii_id2);
138 	sc->mii_funcs = &ihphy_funcs;
139 	sc->mii_pdata = mii;
140 	sc->mii_flags = ma->mii_flags;
141 	sc->mii_anegticks = MII_ANEGTICKS;
142 
143 	PHY_RESET(sc);
144 
145 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
146 	if (sc->mii_capabilities & BMSR_EXTSTAT)
147 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
148 	aprint_normal_dev(self, "");
149 	if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
150 	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
151 		aprint_error("no media present");
152 	else
153 		mii_phy_add_media(sc);
154 	aprint_normal("\n");
155 
156 	/*
157 	 * Link setup (as done by Intel's Linux driver for the 82577).
158 	 */
159 	reg = PHY_READ(sc, IHPHY_MII_CFG);
160 	reg |= IHPHY_CFG_TX_CRS;
161 	reg |= IHPHY_CFG_DOWN_SHIFT;
162 	PHY_WRITE(sc, IHPHY_MII_CFG, reg);
163 }
164 
165 static int
166 ihphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
167 {
168 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
169 	int reg;
170 
171 	switch (cmd) {
172 	case MII_POLLSTAT:
173 		/*
174 		 * If we're not polling our PHY instance, just return.
175 		 */
176 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
177 			return 0;
178 		break;
179 
180 	case MII_MEDIACHG:
181 		/*
182 		 * If the media indicates a different PHY instance,
183 		 * isolate ourselves.
184 		 */
185 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
186 			reg = PHY_READ(sc, MII_BMCR);
187 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
188 			return 0;
189 		}
190 
191 		/*
192 		 * If the interface is not up, don't do anything.
193 		 */
194 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
195 			break;
196 
197 		/*
198 		 * If media is deselected, disable link (standby).
199 		 */
200 		reg = PHY_READ(sc, IHPHY_MII_ECR);
201 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_NONE)
202 			reg &= ~IHPHY_ECR_LNK_EN;
203 		else
204 			reg |= IHPHY_ECR_LNK_EN;
205 		PHY_WRITE(sc, IHPHY_MII_ECR, reg);
206 
207 		/*
208 		 * XXX Adjust MDI/MDIX configuration?  Other settings?
209 		 */
210 
211 		mii_phy_setmedia(sc);
212 		break;
213 
214 	case MII_TICK:
215 		/*
216 		 * If we're not currently selected, just return.
217 		 */
218 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
219 			return 0;
220 
221 		if (mii_phy_tick(sc) == EJUSTRETURN)
222 			return 0;
223 		break;
224 
225 	case MII_DOWN:
226 		mii_phy_down(sc);
227 		PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
228 		return 0;
229 	}
230 
231 	/* Update the media status. */
232 	mii_phy_status(sc);
233 
234 	/* Callback if something changed. */
235 	mii_phy_update(sc, cmd);
236 	return 0;
237 }
238 
239 static void
240 ihphy_status(struct mii_softc *sc)
241 {
242 	struct mii_data *mii = sc->mii_pdata;
243 	int esr, bmcr, gtsr;
244 
245 	mii->mii_media_status = IFM_AVALID;
246 	mii->mii_media_active = IFM_ETHER;
247 
248 	esr = PHY_READ(sc, IHPHY_MII_ESR);
249 
250 	if (esr & IHPHY_ESR_LINK)
251 		mii->mii_media_status |= IFM_ACTIVE;
252 
253 	bmcr = PHY_READ(sc, MII_BMCR);
254 	if (bmcr & (BMCR_ISO | BMCR_PDOWN)) {
255 		mii->mii_media_active |= IFM_NONE;
256 		mii->mii_media_status = 0;
257 		return;
258 	}
259 
260 	if (bmcr & BMCR_LOOP)
261 		mii->mii_media_active |= IFM_LOOP;
262 
263 	if (bmcr & BMCR_AUTOEN) {
264 		if ((esr & IHPHY_ESR_ANEG_STAT) == 0) {
265 			/* Erg, still trying, I guess... */
266 			mii->mii_media_active |= IFM_NONE;
267 			return;
268 		}
269 	}
270 
271 	switch (esr & IHPHY_ESR_SPEED) {
272 	case IHPHY_SPEED_1000:
273 		mii->mii_media_active |= IFM_1000_T;
274 		gtsr = PHY_READ(sc, MII_100T2SR);
275 		if (gtsr & GTSR_MS_RES)
276 			mii->mii_media_active |= IFM_ETH_MASTER;
277 		break;
278 
279 	case IHPHY_SPEED_100:
280 		/* 100BASE-T2 and 100BASE-T4 are not supported. */
281 		mii->mii_media_active |= IFM_100_TX;
282 		break;
283 
284 	case IHPHY_SPEED_10:
285 		mii->mii_media_active |= IFM_10_T;
286 		break;
287 
288 	default:
289 		mii->mii_media_active |= IFM_NONE;
290 		mii->mii_media_status = 0;
291 		return;
292 	}
293 
294 	if (esr & IHPHY_ESR_DUPLEX)
295 		mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
296 	else
297 		mii->mii_media_active |= IFM_HDX;
298 }
299 
300 static void
301 ihphy_reset(struct mii_softc *sc)
302 {
303 	int reg, i;
304 
305 	PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_ISO);
306 
307 	/*
308 	 * Regarding reset, the data sheet specifies (page 55):
309 	 *
310 	 * "After PHY reset, a delay of 10 ms is required before
311 	 *  any register access using MDIO."
312 	 */
313 	delay(10000);
314 
315 	/* Wait another 100ms for it to complete. */
316 	for (i = 0; i < 100; i++) {
317 		reg = PHY_READ(sc, MII_BMCR);
318 		if ((reg & BMCR_RESET) == 0)
319 			break;
320 		delay(1000);
321 	}
322 
323 	if (sc->mii_inst != 0)
324 		PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
325 }
326