1 /* $NetBSD: brgphyreg.h,v 1.2 2002/06/22 14:37:58 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/mii/brgphyreg.h,v 1.1 2000/04/22 01:58:17 wpaul Exp 35 */ 36 37 #ifndef _DEV_MII_BRGPHYREG_H_ 38 #define _DEV_MII_BRGPHYREG_H_ 39 40 /* 41 * Broadcom BCM5400 registers 42 */ 43 44 #define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ 45 #define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ 46 #define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ 47 #define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* Tx output disable d*/ 48 #define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ 49 #define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ 50 #define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ 51 #define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ 52 #define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ 53 #define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ 54 #define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ 55 #define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ 56 #define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ 57 #define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ 58 #define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ 59 #define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ 60 #define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ 61 62 #define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ 63 #define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ 64 #define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ 65 #define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ 66 #define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ 67 #define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ 68 #define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ 69 #define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ 70 #define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ 71 #define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ 72 #define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ 73 #define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ 74 #define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ 75 #define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ 76 #define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ 77 78 #define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ 79 80 #define BRGPHY_MII_FCERRCNT 0x13 /* false carrier sense counter */ 81 #define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ 82 83 #define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ 84 #define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ 85 #define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ 86 87 #define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ 88 89 #define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ 90 91 #define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 92 #define BRGPHY_DSP_AGC_A 0x00 93 #define BRGPHY_DSP_AGC_B 0x01 94 #define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 95 #define BRGPHY_DSP_SOFT_DECISION 0x03 96 #define BRGPHY_DSP_PHASE_REG 0x04 97 #define BRGPHY_DSP_SKEW 0x05 98 #define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 99 #define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 100 #define BRGPHY_DSP_LAST_ECHO 0x08 101 #define BRGPHY_DSP_FREQUENCY 0x09 102 #define BRGPHY_DSP_PLL_BANDWIDTH 0x0A 103 #define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B 104 105 #define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 106 #define BRGPHY_DSP_FILTER_FEXT3 0x0B00 107 #define BRGPHY_DSP_FILTER_FEXT2 0x0A00 108 #define BRGPHY_DSP_FILTER_FEXT1 0x0900 109 #define BRGPHY_DSP_FILTER_FEXT0 0x0800 110 #define BRGPHY_DSP_FILTER_NEXT3 0x0700 111 #define BRGPHY_DSP_FILTER_NEXT2 0x0600 112 #define BRGPHY_DSP_FILTER_NEXT1 0x0500 113 #define BRGPHY_DSP_FILTER_NEXT0 0x0400 114 #define BRGPHY_DSP_FILTER_ECHO 0x0300 115 #define BRGPHY_DSP_FILTER_DFE 0x0200 116 #define BRGPHY_DSP_FILTER_FFE 0x0100 117 118 #define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 119 120 #define BRGPHY_DSP_SEL_CH_0 0x0000 121 #define BRGPHY_DSP_SEL_CH_1 0x2000 122 #define BRGPHY_DSP_SEL_CH_2 0x4000 123 #define BRGPHY_DSP_SEL_CH_3 0x6000 124 125 #define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ 126 #define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ 127 #define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ 128 #define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ 129 #define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ 130 #define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ 131 #define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ 132 133 #define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ 134 #define BRGPHY_AUXSTS_ACOMP 0x8000 /* autoneg complete */ 135 #define BRGPHY_AUXSTS_AN_ACK 0x4000 /* autoneg complete ack */ 136 #define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* autoneg complete ack detect */ 137 #define BRGPHY_AUXSTS_AN_NPW 0x1000 /* autoneg next page wait */ 138 #define BRGPHY_AUXSTS_AN_RES 0x0700 /* AN HDC */ 139 #define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ 140 #define BRGPHY_AUXSTS_RF 0x0040 /* remote fault */ 141 #define BRGPHY_AUXSTS_ANP_R 0x0020 /* AN page received */ 142 #define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* LP AN ability */ 143 #define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* LP Next page ability */ 144 #define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ 145 #define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ 146 #define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ 147 148 #define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ 149 #define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ 150 #define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ 151 #define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ 152 #define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ 153 #define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ 154 #define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ 155 156 #define BRGPHY_MII_ISR 0x1A /* interrupt status */ 157 #define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ 158 #define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ 159 #define BRGPHY_ISR_HCT 0x1000 /* counter above 32K */ 160 #define BRGPHY_ISR_LCT 0x0800 /* all counter below 128 */ 161 #define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ 162 #define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ 163 #define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ 164 #define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 165 #define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 166 #define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ 167 #define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ 168 #define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ 169 #define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ 170 #define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ 171 #define BRGPHY_ISR_CRCERR 0x0001 /* CEC error */ 172 173 #define BRGPHY_MII_IMR 0x1B /* interrupt mask */ 174 #define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ 175 #define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ 176 #define BRGPHY_IMR_HCT 0x1000 /* counter above 32K */ 177 #define BRGPHY_IMR_LCT 0x0800 /* all counter below 128 */ 178 #define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ 179 #define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ 180 #define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ 181 #define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 182 #define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 183 #define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ 184 #define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ 185 #define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ 186 #define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ 187 #define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 188 #define BRGPHY_IMR_CRCERR 0x0001 /* CEC error */ 189 190 #define BRGPHY_INTRS \ 191 ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) 192 193 #endif /* _DEV_BRGPHY_MIIREG_H_ */ 194