1 /* $NetBSD: atphy.c,v 1.17 2015/09/08 10:16:53 msaitoh Exp $ */ 2 /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Attansic F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.17 2015/09/08 10:16:53 msaitoh Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 /* Special Control Register */ 52 #define ATPHY_SCR 0x10 53 #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 #define ATPHY_SCR_SQE_TEST 0x0004 56 #define ATPHY_SCR_MAC_PDOWN 0x0008 57 #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 68 /* Special Status Register. */ 69 #define ATPHY_SSR 0x11 70 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 #define ATPHY_SSR_DUPLEX 0x2000 72 #define ATPHY_SSR_SPEED_MASK 0xC000 73 #define ATPHY_SSR_10MBS 0x0000 74 #define ATPHY_SSR_100MBS 0x4000 75 #define ATPHY_SSR_1000MBS 0x8000 76 77 static int atphy_match(device_t, cfdata_t, void *); 78 static void atphy_attach(device_t, device_t, void *); 79 80 static int atphy_service(struct mii_softc *, struct mii_data *, int); 81 static void atphy_reset(struct mii_softc *); 82 static void atphy_status(struct mii_softc *); 83 static int atphy_mii_phy_auto(struct mii_softc *); 84 static bool atphy_is_gige(const struct mii_phydesc *); 85 86 CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc), 87 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 88 89 const struct mii_phy_funcs atphy_funcs = { 90 atphy_service, atphy_status, atphy_reset, 91 }; 92 93 static const struct mii_phydesc etphys[] = { 94 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, 95 MII_STR_ATHEROS_F1 }, 96 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, 97 MII_STR_ATTANSIC_L1 }, 98 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, 99 MII_STR_ATTANSIC_L2 }, 100 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, 101 MII_STR_ATTANSIC_AR8021 }, 102 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8035, 103 MII_STR_ATTANSIC_AR8035 }, 104 { 0, 0, 105 NULL }, 106 }; 107 108 static bool 109 atphy_is_gige(const struct mii_phydesc *mpd) 110 { 111 switch (mpd->mpd_oui) { 112 case MII_OUI_ATTANSIC: 113 switch (mpd->mpd_model) { 114 case MII_MODEL_ATTANSIC_L2: 115 return false; 116 } 117 } 118 119 return true; 120 } 121 122 static int 123 atphy_match(device_t parent, cfdata_t match, void *aux) 124 { 125 struct mii_attach_args *ma = aux; 126 127 if (mii_phy_match(ma, etphys) != NULL) 128 return 10; 129 130 return 0; 131 } 132 133 void 134 atphy_attach(device_t parent, device_t self, void *aux) 135 { 136 struct mii_softc *sc = device_private(self); 137 struct mii_attach_args *ma = aux; 138 struct mii_data *mii = ma->mii_data; 139 const struct mii_phydesc *mpd; 140 uint16_t bmsr; 141 142 mpd = mii_phy_match(ma, etphys); 143 aprint_naive(": Media interface\n"); 144 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 145 146 sc->mii_dev = self; 147 sc->mii_inst = mii->mii_instance; 148 sc->mii_phy = ma->mii_phyno; 149 sc->mii_funcs = &atphy_funcs; 150 sc->mii_pdata = mii; 151 sc->mii_flags = ma->mii_flags; 152 if (atphy_is_gige(mpd)) 153 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 154 else 155 sc->mii_anegticks = MII_ANEGTICKS; 156 157 sc->mii_flags |= MIIF_NOLOOP; 158 159 PHY_RESET(sc); 160 161 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 162 sc->mii_capabilities = bmsr & ma->mii_capmask; 163 if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT)) 164 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 165 166 aprint_normal_dev(self, ""); 167 mii_phy_add_media(sc); 168 aprint_normal("\n"); 169 } 170 171 int 172 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 173 { 174 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 175 uint16_t anar, bmcr, bmsr; 176 177 switch (cmd) { 178 case MII_POLLSTAT: 179 /* 180 * If we're not polling our PHY instance, just return. 181 */ 182 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 183 return 0; 184 break; 185 186 case MII_MEDIACHG: 187 /* 188 * If the media indicates a different PHY instance, 189 * isolate ourselves. 190 */ 191 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 192 bmcr = PHY_READ(sc, MII_BMCR); 193 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 194 return 0; 195 } 196 197 /* 198 * If the interface is not up, don't do anything. 199 */ 200 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 201 break; 202 203 bmcr = 0; 204 switch (IFM_SUBTYPE(ife->ifm_media)) { 205 case IFM_AUTO: 206 case IFM_1000_T: 207 atphy_mii_phy_auto(sc); 208 goto done; 209 case IFM_100_TX: 210 bmcr = BMCR_S100; 211 break; 212 case IFM_10_T: 213 bmcr = BMCR_S10; 214 break; 215 case IFM_NONE: 216 bmcr = PHY_READ(sc, MII_BMCR); 217 /* 218 * XXX 219 * Due to an unknown reason powering down PHY resulted 220 * in unexpected results such as inaccessibility of 221 * hardware of freshly rebooted system. Disable 222 * powering down PHY until I got more information for 223 * Attansic/Atheros PHY hardwares. 224 */ 225 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 226 goto done; 227 default: 228 return EINVAL; 229 } 230 231 anar = mii_anar(IFM_SUBTYPE(ife->ifm_media)); 232 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { 233 bmcr |= BMCR_FDX; 234 /* Enable pause. */ 235 if (sc->mii_flags & MIIF_DOPAUSE) 236 anar |= ANAR_PAUSE_TOWARDS; 237 } 238 239 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 240 EXTSR_1000THDX)) != 0) 241 PHY_WRITE(sc, MII_100T2CR, 0); 242 PHY_WRITE(sc, MII_ANAR, anar); 243 244 /* 245 * Start autonegotiation. 246 */ 247 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 248 done: 249 break; 250 251 case MII_TICK: 252 /* 253 * If we're not currently selected, just return. 254 */ 255 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 256 return 0; 257 258 /* 259 * Is the interface even up? 260 */ 261 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 262 return 0; 263 264 /* 265 * Only used for autonegotiation. 266 */ 267 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 268 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 269 sc->mii_ticks = 0; 270 break; 271 } 272 273 /* 274 * Check for link. 275 * Read the status register twice; BMSR_LINK is latch-low. 276 */ 277 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 278 if (bmsr & BMSR_LINK) { 279 sc->mii_ticks = 0; 280 break; 281 } 282 283 /* Announce link loss right after it happens. */ 284 if (sc->mii_ticks++ == 0) 285 break; 286 287 /* 288 * Only retry autonegotiation every mii_anegticks seconds. 289 */ 290 if (sc->mii_ticks <= sc->mii_anegticks) 291 break; 292 293 atphy_mii_phy_auto(sc); 294 break; 295 } 296 297 /* Update the media status. */ 298 mii_phy_status(sc); 299 300 /* Callback if something changed. */ 301 mii_phy_update(sc, cmd); 302 return 0; 303 } 304 305 static void 306 atphy_status(struct mii_softc *sc) 307 { 308 struct mii_data *mii = sc->mii_pdata; 309 uint32_t bmsr, bmcr, gsr, ssr; 310 311 mii->mii_media_status = IFM_AVALID; 312 mii->mii_media_active = IFM_ETHER; 313 314 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 315 if (bmsr & BMSR_LINK) 316 mii->mii_media_status |= IFM_ACTIVE; 317 318 bmcr = PHY_READ(sc, MII_BMCR); 319 if (bmcr & BMCR_ISO) { 320 mii->mii_media_active |= IFM_NONE; 321 mii->mii_media_status = 0; 322 return; 323 } 324 325 if (bmcr & BMCR_LOOP) 326 mii->mii_media_active |= IFM_LOOP; 327 328 ssr = PHY_READ(sc, ATPHY_SSR); 329 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 330 /* Erg, still trying, I guess... */ 331 mii->mii_media_active |= IFM_NONE; 332 return; 333 } 334 335 switch (ssr & ATPHY_SSR_SPEED_MASK) { 336 case ATPHY_SSR_1000MBS: 337 mii->mii_media_active |= IFM_1000_T; 338 /* 339 * atphy(4) has a valid link so reset mii_ticks. 340 * Resetting mii_ticks is needed in order to 341 * detect link loss after auto-negotiation. 342 */ 343 sc->mii_ticks = 0; 344 break; 345 case ATPHY_SSR_100MBS: 346 mii->mii_media_active |= IFM_100_TX; 347 sc->mii_ticks = 0; 348 break; 349 case ATPHY_SSR_10MBS: 350 mii->mii_media_active |= IFM_10_T; 351 sc->mii_ticks = 0; 352 break; 353 default: 354 mii->mii_media_active |= IFM_NONE; 355 return; 356 } 357 358 if (ssr & ATPHY_SSR_DUPLEX) 359 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 360 else 361 mii->mii_media_active |= IFM_HDX; 362 363 gsr = PHY_READ(sc, MII_100T2SR); 364 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 365 gsr & GTSR_MS_RES) 366 mii->mii_media_active |= IFM_ETH_MASTER; 367 } 368 369 static void 370 atphy_reset(struct mii_softc *sc) 371 { 372 uint32_t reg; 373 int i; 374 375 /* Take PHY out of power down mode. */ 376 PHY_WRITE(sc, 29, 0x29); 377 PHY_WRITE(sc, 30, 0); 378 379 reg = PHY_READ(sc, ATPHY_SCR); 380 /* Enable automatic crossover. */ 381 reg |= ATPHY_SCR_AUTO_X_MODE; 382 /* Disable power down. */ 383 reg &= ~ATPHY_SCR_MAC_PDOWN; 384 /* Enable CRS on Tx. */ 385 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 386 /* Auto correction for reversed cable polarity. */ 387 reg |= ATPHY_SCR_POLARITY_REVERSAL; 388 PHY_WRITE(sc, ATPHY_SCR, reg); 389 390 atphy_mii_phy_auto(sc); 391 392 /* Workaround F1 bug to reset phy. */ 393 reg = PHY_READ(sc, MII_BMCR) | BMCR_RESET; 394 PHY_WRITE(sc, MII_BMCR, reg); 395 396 for (i = 0; i < 1000; i++) { 397 DELAY(1); 398 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) 399 break; 400 } 401 } 402 403 static int 404 atphy_mii_phy_auto(struct mii_softc *sc) 405 { 406 uint16_t anar; 407 408 sc->mii_ticks = 0; 409 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 410 if (sc->mii_flags & MIIF_DOPAUSE) 411 anar |= ANAR_PAUSE_TOWARDS; 412 PHY_WRITE(sc, MII_ANAR, anar); 413 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 414 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 415 GTCR_ADV_1000THDX); 416 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 417 418 return EJUSTRETURN; 419 } 420