1 /* $NetBSD: atphy.c,v 1.10 2011/02/23 03:22:44 jmcneill Exp $ */ 2 /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Attansic F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.10 2011/02/23 03:22:44 jmcneill Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 /* Special Control Register */ 52 #define ATPHY_SCR 0x10 53 #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 #define ATPHY_SCR_SQE_TEST 0x0004 56 #define ATPHY_SCR_MAC_PDOWN 0x0008 57 #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 68 /* Special Status Register. */ 69 #define ATPHY_SSR 0x11 70 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 #define ATPHY_SSR_DUPLEX 0x2000 72 #define ATPHY_SSR_SPEED_MASK 0xC000 73 #define ATPHY_SSR_10MBS 0x0000 74 #define ATPHY_SSR_100MBS 0x4000 75 #define ATPHY_SSR_1000MBS 0x8000 76 77 static int atphy_match(device_t, cfdata_t, void *); 78 static void atphy_attach(device_t, device_t, void *); 79 80 static int atphy_service(struct mii_softc *, struct mii_data *, int); 81 static void atphy_reset(struct mii_softc *); 82 static void atphy_status(struct mii_softc *); 83 static int atphy_mii_phy_auto(struct mii_softc *); 84 85 CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc), 86 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 87 88 const struct mii_phy_funcs atphy_funcs = { 89 atphy_service, atphy_status, atphy_reset, 90 }; 91 92 static const struct mii_phydesc etphys[] = { 93 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, 94 MII_STR_ATHEROS_F1 }, 95 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, 96 MII_STR_ATTANSIC_L1 }, 97 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, 98 MII_STR_ATTANSIC_L2 }, 99 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, 100 MII_STR_ATTANSIC_AR8021 }, 101 { 0, 0, 102 NULL }, 103 }; 104 105 static int 106 atphy_match(device_t parent, cfdata_t match, void *aux) 107 { 108 struct mii_attach_args *ma = aux; 109 110 if (mii_phy_match(ma, etphys) != NULL) 111 return 10; 112 113 return 0; 114 } 115 116 void 117 atphy_attach(device_t parent, device_t self, void *aux) 118 { 119 struct mii_softc *sc = device_private(self); 120 struct mii_attach_args *ma = aux; 121 struct mii_data *mii = ma->mii_data; 122 const struct mii_phydesc *mpd; 123 uint16_t bmsr; 124 125 mpd = mii_phy_match(ma, etphys); 126 aprint_naive(": Media interface\n"); 127 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 128 129 sc->mii_dev = self; 130 sc->mii_inst = mii->mii_instance; 131 sc->mii_phy = ma->mii_phyno; 132 sc->mii_funcs = &atphy_funcs; 133 sc->mii_pdata = mii; 134 sc->mii_flags = ma->mii_flags; 135 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 136 137 sc->mii_flags |= MIIF_NOLOOP; 138 139 PHY_RESET(sc); 140 141 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 142 sc->mii_capabilities = bmsr & ma->mii_capmask; 143 if (sc->mii_capabilities & BMSR_EXTSTAT) 144 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 145 146 aprint_normal_dev(self, ""); 147 mii_phy_add_media(sc); 148 aprint_normal("\n"); 149 } 150 151 int 152 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 153 { 154 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 155 uint16_t anar, bmcr, bmsr; 156 157 switch (cmd) { 158 case MII_POLLSTAT: 159 /* 160 * If we're not polling our PHY instance, just return. 161 */ 162 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 163 return 0; 164 break; 165 166 case MII_MEDIACHG: 167 /* 168 * If the media indicates a different PHY instance, 169 * isolate ourselves. 170 */ 171 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 172 bmcr = PHY_READ(sc, MII_BMCR); 173 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 174 return 0; 175 } 176 177 /* 178 * If the interface is not up, don't do anything. 179 */ 180 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 181 break; 182 183 bmcr = 0; 184 switch (IFM_SUBTYPE(ife->ifm_media)) { 185 case IFM_AUTO: 186 case IFM_1000_T: 187 atphy_mii_phy_auto(sc); 188 goto done; 189 case IFM_100_TX: 190 bmcr = BMCR_S100; 191 break; 192 case IFM_10_T: 193 bmcr = BMCR_S10; 194 break; 195 case IFM_NONE: 196 bmcr = PHY_READ(sc, MII_BMCR); 197 /* 198 * XXX 199 * Due to an unknown reason powering down PHY resulted 200 * in unexpected results such as inaccessibility of 201 * hardware of freshly rebooted system. Disable 202 * powering down PHY until I got more information for 203 * Attansic/Atheros PHY hardwares. 204 */ 205 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 206 goto done; 207 default: 208 return EINVAL; 209 } 210 211 anar = mii_anar(ife->ifm_media); 212 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { 213 bmcr |= BMCR_FDX; 214 /* Enable pause. */ 215 if (sc->mii_flags & MIIF_DOPAUSE) 216 anar |= ANAR_X_PAUSE_TOWARDS; 217 } 218 219 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 220 EXTSR_1000THDX)) != 0) 221 PHY_WRITE(sc, MII_100T2CR, 0); 222 PHY_WRITE(sc, MII_ANAR, anar); 223 224 /* 225 * Start autonegotiation. 226 */ 227 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 228 done: 229 break; 230 231 case MII_TICK: 232 /* 233 * If we're not currently selected, just return. 234 */ 235 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 236 return 0; 237 238 /* 239 * Is the interface even up? 240 */ 241 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 242 return 0; 243 244 /* 245 * Only used for autonegotiation. 246 */ 247 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 248 sc->mii_ticks = 0; 249 break; 250 } 251 252 /* 253 * Check for link. 254 * Read the status register twice; BMSR_LINK is latch-low. 255 */ 256 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 257 if (bmsr & BMSR_LINK) { 258 sc->mii_ticks = 0; 259 break; 260 } 261 262 /* Announce link loss right after it happens. */ 263 if (sc->mii_ticks++ == 0) 264 break; 265 266 /* 267 * Only retry autonegotiation every mii_anegticks seconds. 268 */ 269 if (sc->mii_ticks <= sc->mii_anegticks) 270 break; 271 272 sc->mii_ticks = 0; 273 atphy_mii_phy_auto(sc); 274 break; 275 } 276 277 /* Update the media status. */ 278 mii_phy_status(sc); 279 280 /* Callback if something changed. */ 281 mii_phy_update(sc, cmd); 282 return 0; 283 } 284 285 static void 286 atphy_status(struct mii_softc *sc) 287 { 288 struct mii_data *mii = sc->mii_pdata; 289 uint32_t bmsr, bmcr, gsr, ssr; 290 291 mii->mii_media_status = IFM_AVALID; 292 mii->mii_media_active = IFM_ETHER; 293 294 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 295 if (bmsr & BMSR_LINK) 296 mii->mii_media_status |= IFM_ACTIVE; 297 298 bmcr = PHY_READ(sc, MII_BMCR); 299 if (bmcr & BMCR_ISO) { 300 mii->mii_media_active |= IFM_NONE; 301 mii->mii_media_status = 0; 302 return; 303 } 304 305 if (bmcr & BMCR_LOOP) 306 mii->mii_media_active |= IFM_LOOP; 307 308 ssr = PHY_READ(sc, ATPHY_SSR); 309 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 310 /* Erg, still trying, I guess... */ 311 mii->mii_media_active |= IFM_NONE; 312 return; 313 } 314 315 switch (ssr & ATPHY_SSR_SPEED_MASK) { 316 case ATPHY_SSR_1000MBS: 317 mii->mii_media_active |= IFM_1000_T; 318 /* 319 * atphy(4) has a valid link so reset mii_ticks. 320 * Resetting mii_ticks is needed in order to 321 * detect link loss after auto-negotiation. 322 */ 323 sc->mii_ticks = 0; 324 break; 325 case ATPHY_SSR_100MBS: 326 mii->mii_media_active |= IFM_100_TX; 327 sc->mii_ticks = 0; 328 break; 329 case ATPHY_SSR_10MBS: 330 mii->mii_media_active |= IFM_10_T; 331 sc->mii_ticks = 0; 332 break; 333 default: 334 mii->mii_media_active |= IFM_NONE; 335 return; 336 } 337 338 if (ssr & ATPHY_SSR_DUPLEX) 339 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 340 else 341 mii->mii_media_active |= IFM_HDX; 342 343 gsr = PHY_READ(sc, MII_100T2SR); 344 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 345 gsr & GTSR_MS_RES) 346 mii->mii_media_active |= IFM_ETH_MASTER; 347 } 348 349 static void 350 atphy_reset(struct mii_softc *sc) 351 { 352 uint32_t reg; 353 int i; 354 355 /* Take PHY out of power down mode. */ 356 PHY_WRITE(sc, 29, 0x29); 357 PHY_WRITE(sc, 30, 0); 358 359 reg = PHY_READ(sc, ATPHY_SCR); 360 /* Enable automatic crossover. */ 361 reg |= ATPHY_SCR_AUTO_X_MODE; 362 /* Disable power down. */ 363 reg &= ~ATPHY_SCR_MAC_PDOWN; 364 /* Enable CRS on Tx. */ 365 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 366 /* Auto correction for reversed cable polarity. */ 367 reg |= ATPHY_SCR_POLARITY_REVERSAL; 368 PHY_WRITE(sc, ATPHY_SCR, reg); 369 370 atphy_mii_phy_auto(sc); 371 372 /* Workaround F1 bug to reset phy. */ 373 reg = PHY_READ(sc, MII_BMCR) | BMCR_RESET; 374 PHY_WRITE(sc, MII_BMCR, reg); 375 376 for (i = 0; i < 1000; i++) { 377 DELAY(1); 378 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) 379 break; 380 } 381 } 382 383 static int 384 atphy_mii_phy_auto(struct mii_softc *sc) 385 { 386 uint16_t anar; 387 388 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 389 if (sc->mii_flags & MIIF_DOPAUSE) 390 anar |= ANAR_X_PAUSE_TOWARDS; 391 PHY_WRITE(sc, MII_ANAR, anar); 392 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 393 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 394 GTCR_ADV_1000THDX); 395 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 396 397 return EJUSTRETURN; 398 } 399