1 /* $NetBSD: edc_mca.c,v 1.32 2005/12/11 12:22:18 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jaromir Dolecek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 38 * spec. 39 * 40 * The driver was written with DASD Storage Interface Specification 41 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>. 42 * 43 * TODO: 44 * - improve error recovery 45 * Issue soft reset on error or timeout? 46 * - test with > 1 disk (this is supported by some controllers) 47 * - test with > 1 ESDI controller in machine; shared interrupts 48 * necessary for this to work should be supported - edc_intr() specifically 49 * checks if the interrupt is for this controller 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.32 2005/12/11 12:22:18 christos Exp $"); 54 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/buf.h> 60 #include <sys/bufq.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 #include <sys/malloc.h> 64 #include <sys/endian.h> 65 #include <sys/disklabel.h> 66 #include <sys/disk.h> 67 #include <sys/syslog.h> 68 #include <sys/proc.h> 69 #include <sys/vnode.h> 70 #include <sys/kernel.h> 71 #include <sys/kthread.h> 72 #if NRND > 0 73 #include <sys/rnd.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/mca/mcareg.h> 80 #include <dev/mca/mcavar.h> 81 #include <dev/mca/mcadevs.h> 82 83 #include <dev/mca/edcreg.h> 84 #include <dev/mca/edvar.h> 85 #include <dev/mca/edcvar.h> 86 87 #include "locators.h" 88 89 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 90 #define EDC_MAX_CMD_RES_LEN 8 91 92 struct edc_mca_softc { 93 struct device sc_dev; 94 95 bus_space_tag_t sc_iot; 96 bus_space_handle_t sc_ioh; 97 98 /* DMA related stuff */ 99 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 100 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 101 102 void *sc_ih; /* interrupt handle */ 103 104 int sc_flags; 105 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 106 107 #define DASD_MAXDEVS 8 108 struct ed_softc *sc_ed[DASD_MAXDEVS]; 109 int sc_maxdevs; /* max number of disks attached to this 110 * controller */ 111 112 /* I/O results variables */ 113 volatile int sc_stat; 114 #define STAT_START 0 115 #define STAT_ERROR 1 116 #define STAT_DONE 2 117 volatile int sc_resblk; /* residual block count */ 118 119 /* CMD status block - only set & used in edc_intr() */ 120 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 121 }; 122 123 int edc_mca_probe(struct device *, struct cfdata *, void *); 124 void edc_mca_attach(struct device *, struct device *, void *); 125 126 CFATTACH_DECL(edc_mca, sizeof(struct edc_mca_softc), 127 edc_mca_probe, edc_mca_attach, NULL, NULL); 128 129 static int edc_intr(void *); 130 static void edc_dump_status_block(struct edc_mca_softc *, 131 u_int16_t *, int); 132 static int edc_do_attn(struct edc_mca_softc *, int, int, int); 133 static void edc_cmd_wait(struct edc_mca_softc *, int, int); 134 static void edcworker(void *); 135 static void edc_spawn_worker(void *); 136 137 int 138 edc_mca_probe(parent, match, aux) 139 struct device *parent; 140 struct cfdata *match; 141 void *aux; 142 { 143 struct mca_attach_args *ma = aux; 144 145 switch (ma->ma_id) { 146 case MCA_PRODUCT_IBM_ESDIC: 147 case MCA_PRODUCT_IBM_ESDIC_IG: 148 return (1); 149 default: 150 return (0); 151 } 152 } 153 154 void 155 edc_mca_attach(parent, self, aux) 156 struct device *parent, *self; 157 void *aux; 158 { 159 struct edc_mca_softc *sc = (void *) self; 160 struct mca_attach_args *ma = aux; 161 struct ed_attach_args eda; 162 int pos2, pos3, pos4; 163 int irq, drq, iobase; 164 const char *typestr; 165 int devno, error; 166 int locs[EDCCF_NLOCS]; 167 168 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 169 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 170 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 171 172 /* 173 * POS register 2: (adf pos0) 174 * 175 * 7 6 5 4 3 2 1 0 176 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 177 * \ \ \___ Primary/Alternate Port Addresses: 178 * \ \ 0=0x3510-3517 1=0x3518-0x351f 179 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 180 * \ 0000=0 0001=1 0011=3 0100=4 181 * \_________ Fairness On/Off: 1=On 0=Off 182 * 183 * POS register 3: (adf pos1) 184 * 185 * 7 6 5 4 3 2 1 0 186 * 0 0 \_/ 187 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 188 * 01=16ms 00=Burst Disabled 189 * 190 * POS register 4: (adf pos2) 191 * 192 * 7 6 5 4 3 2 1 0 193 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 194 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 195 * 196 * IRQ is fixed to 14 (0x0e). 197 */ 198 199 switch (ma->ma_id) { 200 case MCA_PRODUCT_IBM_ESDIC: 201 typestr = "IBM ESDI Fixed Disk Controller"; 202 break; 203 case MCA_PRODUCT_IBM_ESDIC_IG: 204 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 205 break; 206 default: 207 typestr = NULL; 208 break; 209 } 210 211 irq = ESDIC_IRQ; 212 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 213 drq = (pos2 & DRQ_MASK) >> 2; 214 215 printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 216 irq, drq, typestr); 217 218 #ifdef DIAGNOSTIC 219 /* 220 * It's not strictly necessary to check this, machine configuration 221 * utility uses only valid addresses. 222 */ 223 if (drq == 2 || drq >= 8) { 224 printf("%s: invalid DMA Arbitration Level %d\n", 225 sc->sc_dev.dv_xname, drq); 226 return; 227 } 228 #endif 229 230 printf("%s: Fairness %s, Release %s, ", 231 sc->sc_dev.dv_xname, 232 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 233 (pos4 & RELEASE_1) ? "6ms" 234 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 235 ); 236 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 237 static const char * const pacint[] = 238 { "disabled", "16ms", "24ms", "31ms"}; 239 printf("DMA burst pacing interval %s\n", 240 pacint[(pos3 & PACING_INT_MASK) >> 4]); 241 } else 242 printf("DMA pacing control disabled\n"); 243 244 sc->sc_iot = ma->ma_iot; 245 246 if (bus_space_map(sc->sc_iot, iobase, 247 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 248 printf("%s: couldn't map registers\n", 249 sc->sc_dev.dv_xname); 250 return; 251 } 252 253 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 254 if (sc->sc_ih == NULL) { 255 printf("%s: couldn't establish interrupt handler\n", 256 sc->sc_dev.dv_xname); 257 return; 258 } 259 260 /* Create a MCA DMA map, used for data transfer */ 261 sc->sc_dmat = ma->ma_dmat; 262 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 263 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 264 &sc->sc_dmamap_xfer, drq)) != 0){ 265 printf("%s: couldn't create DMA map - error %d\n", 266 sc->sc_dev.dv_xname, error); 267 return; 268 } 269 270 /* 271 * Integrated ESDI controller supports only one disk, other 272 * controllers support two disks. 273 */ 274 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 275 sc->sc_maxdevs = 1; 276 else 277 sc->sc_maxdevs = 2; 278 279 /* 280 * Reset controller and attach individual disks. ed attach routine 281 * uses polling so that this works with interrupts disabled. 282 */ 283 284 /* Do a reset to ensure sane state after warm boot. */ 285 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 286 /* hard reset */ 287 printf("%s: controller busy, performing hardware reset ...\n", 288 sc->sc_dev.dv_xname); 289 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 290 BCR_INT_ENABLE|BCR_RESET); 291 } else { 292 /* "SOFT" reset */ 293 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 294 } 295 296 /* 297 * Since interrupts are disabled, it's necessary 298 * to detect the interrupt request and call edc_intr() 299 * explicitly. See also edc_run_cmd(). 300 */ 301 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 302 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 303 edc_intr(sc); 304 305 delay(100); 306 } 307 308 /* be quiet during probes */ 309 sc->sc_flags |= DASD_QUIET; 310 311 /* check for attached disks */ 312 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 313 eda.edc_drive = devno; 314 locs[EDCCF_DRIVE] = devno; 315 sc->sc_ed[devno] = 316 (void *) config_found_sm_loc(self, "edc", locs, &eda, 317 NULL, config_stdsubmatch); 318 319 /* If initialization did not succeed, NULL the pointer. */ 320 if (sc->sc_ed[devno] 321 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 322 sc->sc_ed[devno] = NULL; 323 } 324 325 /* enable full error dumps again */ 326 sc->sc_flags &= ~DASD_QUIET; 327 328 /* 329 * Check if there are any disks attached. If not, disestablish 330 * the interrupt. 331 */ 332 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 333 if (sc->sc_ed[devno]) 334 break; 335 } 336 337 if (devno == sc->sc_maxdevs) { 338 printf("%s: disabling controller (no drives attached)\n", 339 sc->sc_dev.dv_xname); 340 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 341 return; 342 } 343 344 /* 345 * Run the worker thread. 346 */ 347 config_pending_incr(); 348 kthread_create(edc_spawn_worker, (void *) sc); 349 } 350 351 void 352 edc_add_disk(sc, ed) 353 struct edc_mca_softc *sc; 354 struct ed_softc *ed; 355 { 356 sc->sc_ed[ed->sc_devno] = ed; 357 } 358 359 static int 360 edc_intr(arg) 361 void *arg; 362 { 363 struct edc_mca_softc *sc = arg; 364 u_int8_t isr, intr_id; 365 u_int16_t sifr; 366 int cmd=-1, devno; 367 368 /* 369 * Check if the interrupt was for us. 370 */ 371 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 372 return (0); 373 374 /* 375 * Read ISR to find out interrupt type. This also clears the interrupt 376 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 377 * and 4 are reserved and not used. 378 */ 379 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 380 intr_id = isr & ISR_INTR_ID_MASK; 381 382 #ifdef EDC_DEBUG 383 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 384 printf("%s: bogus interrupt id %d\n", sc->sc_dev.dv_xname, 385 (int) intr_id); 386 return (0); 387 } 388 #endif 389 390 /* Get number of device whose intr this was */ 391 devno = (isr & 0xe0) >> 5; 392 393 /* 394 * Get Status block. Higher byte always says how long the status 395 * block is, rest is device number and command code. 396 * Check the status block length against our supported maximum length 397 * and fetch the data. 398 */ 399 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 400 size_t len; 401 int i; 402 403 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 404 len = (sifr & 0xff00) >> 8; 405 #ifdef DEBUG 406 if (len > EDC_MAX_CMD_RES_LEN) 407 panic("%s: maximum Status Length exceeded: %d > %d", 408 sc->sc_dev.dv_xname, 409 len, EDC_MAX_CMD_RES_LEN); 410 #endif 411 412 /* Get command code */ 413 cmd = sifr & SIFR_CMD_MASK; 414 415 /* Read whole status block */ 416 sc->status_block[0] = sifr; 417 for(i=1; i < len; i++) { 418 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 419 & BSR_SIFR_FULL) == 0) 420 ; 421 422 sc->status_block[i] = le16toh( 423 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 424 } 425 /* zero out rest */ 426 if (i < EDC_MAX_CMD_RES_LEN) { 427 memset(&sc->status_block[i], 0, 428 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 429 } 430 } 431 432 switch (intr_id) { 433 case ISR_DATA_TRANSFER_RDY: 434 /* 435 * Ready to do DMA. The DMA controller has already been 436 * setup, now just kick disk controller to do the transfer. 437 */ 438 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 439 BCR_INT_ENABLE|BCR_DMA_ENABLE); 440 break; 441 442 case ISR_COMPLETED: 443 case ISR_COMPLETED_WITH_ECC: 444 case ISR_COMPLETED_RETRIES: 445 case ISR_COMPLETED_WARNING: 446 /* 447 * Copy device config data if appropriate. sc->sc_ed[] 448 * entry might be NULL during probe. 449 */ 450 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 451 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 452 sizeof(sc->sc_ed[devno]->sense_data)); 453 } 454 455 sc->sc_stat = STAT_DONE; 456 break; 457 458 case ISR_RESET_COMPLETED: 459 case ISR_ABORT_COMPLETED: 460 /* nothing to do */ 461 break; 462 463 case ISR_ATTN_ERROR: 464 /* 465 * Basically, this means driver bug or something seriously 466 * hosed. panic rather than extending the lossage. 467 * No status block available, so no further info. 468 */ 469 panic("%s: dev %d: attention error", 470 sc->sc_dev.dv_xname, 471 devno); 472 /* NOTREACHED */ 473 break; 474 475 default: 476 if ((sc->sc_flags & DASD_QUIET) == 0) 477 edc_dump_status_block(sc, sc->status_block, intr_id); 478 479 sc->sc_stat = STAT_ERROR; 480 break; 481 } 482 483 /* 484 * Unless the interrupt is for Data Transfer Ready or 485 * Attention Error, finish by assertion EOI. This makes 486 * attachment aware the interrupt is processed and system 487 * is ready to accept another one. 488 */ 489 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 490 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 491 492 /* If Read or Write Data, wakeup worker thread to finish it */ 493 if (intr_id != ISR_DATA_TRANSFER_RDY) { 494 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 495 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 496 wakeup_one(sc); 497 } 498 499 return (1); 500 } 501 502 /* 503 * This follows the exact order for Attention Request as 504 * written in DASD Storage Interface Specification MC (Rev 2.2). 505 */ 506 static int 507 edc_do_attn(sc, attn_type, devno, intr_id) 508 struct edc_mca_softc *sc; 509 int attn_type, devno, intr_id; 510 { 511 int tries; 512 513 /* 1. Disable interrupts in BCR. */ 514 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 515 516 /* 517 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 518 * a RESET COMPLETED interrupt. 519 */ 520 if (intr_id != ISR_RESET_COMPLETED) { 521 #ifdef EDC_DEBUG 522 if (attn_type == ATN_CMD_REQ 523 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 524 & BSR_INT_PENDING)) 525 panic("%s: edc int pending", sc->sc_dev.dv_xname); 526 #endif 527 528 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 529 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 530 & BSR_BUSY) == 0) 531 break; 532 } 533 534 if (tries == EDC_ATTN_MAXTRIES) { 535 printf("%s: edc_do_attn: timeout waiting for attachment to become available\n", 536 sc->sc_ed[devno]->sc_dev.dv_xname); 537 return (EIO); 538 } 539 } 540 541 /* 542 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 543 */ 544 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 545 546 /* 547 * 4. Enable interrupts via BCR. 548 */ 549 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 550 551 return (0); 552 } 553 554 /* 555 * Wait until command is processed, timeout after 'secs' seconds. 556 * We use mono_time, since we don't need actual RTC, just time 557 * interval. 558 */ 559 static void 560 edc_cmd_wait(sc, secs, poll) 561 struct edc_mca_softc *sc; 562 int secs, poll; 563 { 564 int val; 565 566 if (!poll) { 567 int s; 568 569 /* Not polling, can sleep. Sleep until we are awakened, 570 * but maximum secs seconds. 571 */ 572 s = splbio(); 573 if (sc->sc_stat != STAT_DONE) 574 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 575 splx(s); 576 } 577 578 /* Wait until the command is completely finished */ 579 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 580 & BSR_CMD_INPROGRESS) { 581 if (poll && (val & BSR_INTR)) 582 edc_intr(sc); 583 } 584 } 585 586 /* 587 * Command controller to execute specified command on a device. 588 */ 589 int 590 edc_run_cmd(sc, cmd, devno, cmd_args, cmd_len, poll) 591 struct edc_mca_softc *sc; 592 int cmd; 593 int devno; 594 u_int16_t cmd_args[]; 595 int cmd_len, poll; 596 { 597 int i, error, tries; 598 u_int16_t cmd0; 599 600 sc->sc_stat = STAT_START; 601 602 /* Do Attention Request for Command Request. */ 603 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 604 return (error); 605 606 /* 607 * Construct the command. The bits are like this: 608 * 609 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 610 * \_/ 0 0 1 0 \__/ \_____/ 611 * \ \__________/ \ \_ Command Code (see CMD_*) 612 * \ \ \__ Device: 0 common, 7 controller 613 * \ \__ Options: reserved, bit 10=cache bypass bit 614 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 615 * 616 * We always use device 0 or 1, so difference is made only by Command 617 * Code, Command Options and command length. 618 */ 619 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 620 | (devno << 5) 621 | (cmd_args[0] << 8) | cmd; 622 cmd_args[0] = cmd0; 623 624 /* 625 * Write word of CMD to the CIFR. This sets "Command 626 * Interface Register Full (CMD IN)" in BSR. Once the attachment 627 * detects it, it reads the word and clears CMD IN. This all should 628 * be quite fast, so don't sleep in !poll case neither. 629 */ 630 for(i=0; i < cmd_len; i++) { 631 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 632 htole16(cmd_args[i])); 633 634 /* Wait until CMD IN is cleared. */ 635 tries = 0; 636 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 637 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 638 delay(poll ? 1000 : 1); 639 ; 640 641 if (tries == 10000 642 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 643 & BSR_CIFR_FULL) { 644 printf("%s: device too slow to accept command %d\n", 645 sc->sc_dev.dv_xname, cmd); 646 return (EIO); 647 } 648 } 649 650 /* Wait for command to complete, but maximum 15 seconds. */ 651 edc_cmd_wait(sc, 15, poll); 652 653 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 654 } 655 656 #ifdef EDC_DEBUG 657 static const char * const edc_commands[] = { 658 "Invalid Command", 659 "Read Data", 660 "Write Data", 661 "Read Verify", 662 "Write with Verify", 663 "Seek", 664 "Park Head", 665 "Get Command Complete Status", 666 "Get Device Status", 667 "Get Device Configuration", 668 "Get POS Information", 669 "Translate RBA", 670 "Write Attachment Buffer", 671 "Read Attachment Buffer", 672 "Run Diagnostic Test", 673 "Get Diagnostic Status Block", 674 "Get MFG Header", 675 "Format Unit", 676 "Format Prepare", 677 "Set MAX RBA", 678 "Set Power Saving Mode", 679 "Power Conservation Command", 680 }; 681 682 static const char * const edc_cmd_status[256] = { 683 "Reserved", 684 "Command completed successfully", 685 "Reserved", 686 "Command completed successfully with ECC applied", 687 "Reserved", 688 "Command completed successfully with retries", 689 "Format Command partially completed", /* Status available */ 690 "Command completed successfully with ECC and retries", 691 "Command completed with Warning", /* Command Error is available */ 692 "Aborted", 693 "Reset completed", 694 "Data Transfer Ready", /* No Status Block available */ 695 "Command terminated with failure", /* Device Error is available */ 696 "DMA Error", /* Retry entire command as recovery */ 697 "Command Block Error", 698 "Attention Error (Illegal Attention Code)", 699 /* 0x14 - 0xff reserved */ 700 }; 701 702 static const char * const edc_cmd_error[256] = { 703 "No Error", 704 "Invalid parameter in the command block", 705 "Reserved", 706 "Command not supported", 707 "Command Aborted per request", 708 "Reserved", 709 "Command rejected", /* Attachment diagnostic failure */ 710 "Format Rejected", /* Prepare Format command is required */ 711 "Format Error (Primary Map is not readable)", 712 "Format Error (Secondary map is not readable)", 713 "Format Error (Diagnostic Failure)", 714 "Format Warning (Secondary Map Overflow)", 715 "Reserved" 716 "Format Error (Host Checksum Error)", 717 "Reserved", 718 "Format Warning (Push table overflow)", 719 "Format Warning (More pushes than allowed)", 720 "Reserved", 721 "Format Warning (Error during verifying)", 722 "Invalid device number for the command", 723 /* 0x14-0xff reserved */ 724 }; 725 726 static const char * const edc_dev_errors[] = { 727 "No Error", 728 "Seek Fault", /* Device report */ 729 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 730 "Block not found (ID not found)", 731 "Block not found (AM not found)", 732 "Data ECC Error (hard error)", 733 "ID CRC Error", 734 "RBA Out of Range", 735 "Reserved", 736 "Defective Block", 737 "Reserved", 738 "Selection Error", 739 "Reserved", 740 "Write Fault", 741 "No index or sector pulse", 742 "Device Not Ready", 743 "Seek Error", /* Attachment report */ 744 "Bad Format", 745 "Volume Overflow", 746 "No Data AM Found", 747 "Block not found (No ID AM or ID CRC error occurred)", 748 "Reserved", 749 "Reserved", 750 "No ID found on track (ID search)", 751 /* 0x19 - 0xff reserved */ 752 }; 753 #endif /* EDC_DEBUG */ 754 755 static void 756 edc_dump_status_block(sc, status_block, intr_id) 757 struct edc_mca_softc *sc; 758 u_int16_t *status_block; 759 int intr_id; 760 { 761 #ifdef EDC_DEBUG 762 printf("%s: Command: %s, Status: %s (intr %d)\n", 763 sc->sc_dev.dv_xname, 764 edc_commands[status_block[0] & 0x1f], 765 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 766 intr_id 767 ); 768 #else 769 printf("%s: Command: %d, Status: %d (intr %d)\n", 770 sc->sc_dev.dv_xname, 771 status_block[0] & 0x1f, 772 SB_GET_CMD_STATUS(status_block), 773 intr_id 774 ); 775 #endif 776 printf("%s: # left blocks: %u, last processed RBA: %u\n", 777 sc->sc_dev.dv_xname, 778 status_block[SB_RESBLKCNT_IDX], 779 (status_block[5] << 16) | status_block[4]); 780 781 if (intr_id == ISR_COMPLETED_WARNING) { 782 #ifdef EDC_DEBUG 783 printf("%s: Command Error Code: %s\n", 784 sc->sc_dev.dv_xname, 785 edc_cmd_error[status_block[1] & 0xff]); 786 #else 787 printf("%s: Command Error Code: %d\n", 788 sc->sc_dev.dv_xname, 789 status_block[1] & 0xff); 790 #endif 791 } 792 793 if (intr_id == ISR_CMD_FAILED) { 794 #ifdef EDC_DEBUG 795 char buf[100]; 796 797 printf("%s: Device Error Code: %s\n", 798 sc->sc_dev.dv_xname, 799 edc_dev_errors[status_block[2] & 0xff]); 800 bitmask_snprintf((status_block[2] & 0xff00) >> 8, 801 "\20" 802 "\01SeekOrCmdComplete" 803 "\02Track0Flag" 804 "\03WriteFault" 805 "\04Selected" 806 "\05Ready" 807 "\06Reserved0" 808 "\07STANDBY" 809 "\010Reserved0", 810 buf, sizeof(buf)); 811 printf("%s: Device Status: %s\n", 812 sc->sc_dev.dv_xname, buf); 813 #else 814 printf("%s: Device Error Code: %d, Device Status: %d\n", 815 sc->sc_dev.dv_xname, 816 status_block[2] & 0xff, 817 (status_block[2] & 0xff00) >> 8); 818 #endif 819 } 820 } 821 822 static void 823 edc_spawn_worker(arg) 824 void *arg; 825 { 826 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 827 int error; 828 struct proc *wrk; 829 830 /* Now, everything is ready, start a kthread */ 831 if ((error = kthread_create1(edcworker, sc, &wrk, 832 "%s", sc->sc_dev.dv_xname))) { 833 printf("%s: cannot spawn worker thread: errno=%d\n", 834 sc->sc_dev.dv_xname, error); 835 panic("edc_spawn_worker"); 836 } 837 } 838 839 /* 840 * Main worker thread function. 841 */ 842 void 843 edcworker(arg) 844 void *arg; 845 { 846 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 847 struct ed_softc *ed; 848 struct buf *bp; 849 int i, error; 850 851 config_pending_decr(); 852 853 for(;;) { 854 /* Wait until awakened */ 855 (void) tsleep(sc, PRIBIO, "edcidle", 0); 856 857 for(i=0; i<sc->sc_maxdevs; ) { 858 if ((ed = sc->sc_ed[i]) == NULL) { 859 i++; 860 continue; 861 } 862 863 /* Is there a buf for us ? */ 864 simple_lock(&ed->sc_q_lock); 865 if ((bp = BUFQ_GET(ed->sc_q)) == NULL) { 866 simple_unlock(&ed->sc_q_lock); 867 i++; 868 continue; 869 } 870 simple_unlock(&ed->sc_q_lock); 871 872 /* Instrumentation. */ 873 disk_busy(&ed->sc_dk); 874 875 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 876 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 877 878 if (error) { 879 bp->b_error = error; 880 bp->b_flags |= B_ERROR; 881 } else { 882 /* Set resid, most commonly to zero. */ 883 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 884 } 885 886 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 887 (bp->b_flags & B_READ)); 888 #if NRND > 0 889 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 890 #endif 891 biodone(bp); 892 } 893 } 894 } 895 896 int 897 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 898 size_t bcount, daddr_t rawblkno, int isread, int poll) 899 { 900 u_int16_t cmd_args[4]; 901 int error=0, fl; 902 u_int16_t track; 903 u_int16_t cyl; 904 u_int8_t head; 905 u_int8_t sector; 906 907 mca_disk_busy(); 908 909 /* set WAIT and R/W flag appropriately for the DMA transfer */ 910 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 911 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 912 913 /* Load the buffer for DMA transfer. */ 914 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 915 bcount, NULL, BUS_DMA_STREAMING|fl))) { 916 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 917 ed->sc_dev.dv_xname, error); 918 goto out; 919 } 920 921 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 922 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 923 924 track = rawblkno / ed->sectors; 925 head = track % ed->heads; 926 cyl = track / ed->heads; 927 sector = rawblkno % ed->sectors; 928 929 /* Read or Write Data command */ 930 cmd_args[0] = 2; /* Options 0000010 */ 931 cmd_args[1] = bcount / DEV_BSIZE; 932 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 933 cmd_args[3] = ((cyl & 0x3E0) >> 5); 934 error = edc_run_cmd(sc, 935 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 936 ed->sc_devno, cmd_args, 4, poll); 937 938 /* Sync the DMA memory */ 939 if (!error) { 940 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 941 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 942 } 943 944 /* We are done, unload buffer from DMA map */ 945 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 946 947 out: 948 mca_disk_unbusy(); 949 950 return (error); 951 } 952