1 /* $NetBSD: edc_mca.c,v 1.25 2004/09/01 20:57:58 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jaromir Dolecek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 38 * spec. 39 * 40 * The driver was written with DASD Storage Interface Specification 41 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>. 42 * 43 * TODO: 44 * - improve error recovery 45 * Issue soft reset on error or timeout? 46 * - test with > 1 disk (this is supported by some controllers) 47 * - test with > 1 ESDI controller in machine; shared interrupts 48 * necessary for this to work should be supported - edc_intr() specifically 49 * checks if the interrupt is for this controller 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.25 2004/09/01 20:57:58 drochner Exp $"); 54 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/errno.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/endian.h> 63 #include <sys/disklabel.h> 64 #include <sys/disk.h> 65 #include <sys/syslog.h> 66 #include <sys/proc.h> 67 #include <sys/vnode.h> 68 #include <sys/kernel.h> 69 #include <sys/kthread.h> 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <machine/bus.h> 75 #include <machine/intr.h> 76 77 #include <dev/mca/mcareg.h> 78 #include <dev/mca/mcavar.h> 79 #include <dev/mca/mcadevs.h> 80 81 #include <dev/mca/edcreg.h> 82 #include <dev/mca/edvar.h> 83 #include <dev/mca/edcvar.h> 84 85 #include "locators.h" 86 87 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 88 #define EDC_MAX_CMD_RES_LEN 8 89 90 struct edc_mca_softc { 91 struct device sc_dev; 92 93 bus_space_tag_t sc_iot; 94 bus_space_handle_t sc_ioh; 95 96 /* DMA related stuff */ 97 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 98 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 99 100 void *sc_ih; /* interrupt handle */ 101 102 int sc_flags; 103 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 104 105 #define DASD_MAXDEVS 8 106 struct ed_softc *sc_ed[DASD_MAXDEVS]; 107 int sc_maxdevs; /* max number of disks attached to this 108 * controller */ 109 110 /* I/O results variables */ 111 volatile int sc_stat; 112 #define STAT_START 0 113 #define STAT_ERROR 1 114 #define STAT_DONE 2 115 volatile int sc_resblk; /* residual block count */ 116 117 /* CMD status block - only set & used in edc_intr() */ 118 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 119 }; 120 121 int edc_mca_probe __P((struct device *, struct cfdata *, void *)); 122 void edc_mca_attach __P((struct device *, struct device *, void *)); 123 124 CFATTACH_DECL(edc_mca, sizeof(struct edc_mca_softc), 125 edc_mca_probe, edc_mca_attach, NULL, NULL); 126 127 static int edc_intr __P((void *)); 128 static void edc_dump_status_block __P((struct edc_mca_softc *, 129 u_int16_t *, int)); 130 static int edc_do_attn __P((struct edc_mca_softc *, int, int, int)); 131 static void edc_cmd_wait __P((struct edc_mca_softc *, int, int)); 132 static void edcworker __P((void *)); 133 static void edc_spawn_worker __P((void *)); 134 135 int 136 edc_mca_probe(parent, match, aux) 137 struct device *parent; 138 struct cfdata *match; 139 void *aux; 140 { 141 struct mca_attach_args *ma = aux; 142 143 switch (ma->ma_id) { 144 case MCA_PRODUCT_IBM_ESDIC: 145 case MCA_PRODUCT_IBM_ESDIC_IG: 146 return (1); 147 default: 148 return (0); 149 } 150 } 151 152 static int 153 edcsubmatch(struct device *parent, struct cfdata *cf, 154 const locdesc_t *ldesc, void *aux) 155 { 156 157 if (cf->cf_loc[EDCCF_DRIVE] != EDCCF_DRIVE_DEFAULT && 158 cf->cf_loc[EDCCF_DRIVE] != ldesc->locs[EDCCF_DRIVE]) 159 return (0); 160 161 return (config_match(parent, cf, aux)); 162 } 163 164 void 165 edc_mca_attach(parent, self, aux) 166 struct device *parent, *self; 167 void *aux; 168 { 169 struct edc_mca_softc *sc = (void *) self; 170 struct mca_attach_args *ma = aux; 171 struct ed_attach_args eda; 172 int pos2, pos3, pos4; 173 int irq, drq, iobase; 174 const char *typestr; 175 int devno, error; 176 int help[2]; 177 locdesc_t *ldesc = (void *)help; /* XXX */ 178 179 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 180 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 181 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 182 183 /* 184 * POS register 2: (adf pos0) 185 * 186 * 7 6 5 4 3 2 1 0 187 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 188 * \ \ \___ Primary/Alternate Port Addresses: 189 * \ \ 0=0x3510-3517 1=0x3518-0x351f 190 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 191 * \ 0000=0 0001=1 0011=3 0100=4 192 * \_________ Fairness On/Off: 1=On 0=Off 193 * 194 * POS register 3: (adf pos1) 195 * 196 * 7 6 5 4 3 2 1 0 197 * 0 0 \_/ 198 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 199 * 01=16ms 00=Burst Disabled 200 * 201 * POS register 4: (adf pos2) 202 * 203 * 7 6 5 4 3 2 1 0 204 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 205 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 206 * 207 * IRQ is fixed to 14 (0x0e). 208 */ 209 210 switch (ma->ma_id) { 211 case MCA_PRODUCT_IBM_ESDIC: 212 typestr = "IBM ESDI Fixed Disk Controller"; 213 break; 214 case MCA_PRODUCT_IBM_ESDIC_IG: 215 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 216 break; 217 default: 218 typestr = NULL; 219 break; 220 } 221 222 irq = ESDIC_IRQ; 223 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 224 drq = (pos2 & DRQ_MASK) >> 2; 225 226 printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 227 irq, drq, typestr); 228 229 #ifdef DIAGNOSTIC 230 /* 231 * It's not strictly necessary to check this, machine configuration 232 * utility uses only valid addresses. 233 */ 234 if (drq == 2 || drq >= 8) { 235 printf("%s: invalid DMA Arbitration Level %d\n", 236 sc->sc_dev.dv_xname, drq); 237 return; 238 } 239 #endif 240 241 printf("%s: Fairness %s, Release %s, ", 242 sc->sc_dev.dv_xname, 243 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 244 (pos4 & RELEASE_1) ? "6ms" 245 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 246 ); 247 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 248 static const char * const pacint[] = 249 { "disabled", "16ms", "24ms", "31ms"}; 250 printf("DMA burst pacing interval %s\n", 251 pacint[(pos3 & PACING_INT_MASK) >> 4]); 252 } else 253 printf("DMA pacing control disabled\n"); 254 255 sc->sc_iot = ma->ma_iot; 256 257 if (bus_space_map(sc->sc_iot, iobase, 258 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 259 printf("%s: couldn't map registers\n", 260 sc->sc_dev.dv_xname); 261 return; 262 } 263 264 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 265 if (sc->sc_ih == NULL) { 266 printf("%s: couldn't establish interrupt handler\n", 267 sc->sc_dev.dv_xname); 268 return; 269 } 270 271 /* Create a MCA DMA map, used for data transfer */ 272 sc->sc_dmat = ma->ma_dmat; 273 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 274 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 275 &sc->sc_dmamap_xfer, drq)) != 0){ 276 printf("%s: couldn't create DMA map - error %d\n", 277 sc->sc_dev.dv_xname, error); 278 return; 279 } 280 281 /* 282 * Integrated ESDI controller supports only one disk, other 283 * controllers support two disks. 284 */ 285 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 286 sc->sc_maxdevs = 1; 287 else 288 sc->sc_maxdevs = 2; 289 290 /* 291 * Reset controller and attach individual disks. ed attach routine 292 * uses polling so that this works with interrupts disabled. 293 */ 294 295 /* Do a reset to ensure sane state after warm boot. */ 296 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 297 /* hard reset */ 298 printf("%s: controller busy, performing hardware reset ...\n", 299 sc->sc_dev.dv_xname); 300 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 301 BCR_INT_ENABLE|BCR_RESET); 302 } else { 303 /* "SOFT" reset */ 304 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 305 } 306 307 /* 308 * Since interrupts are disabled, it's necessary 309 * to detect the interrupt request and call edc_intr() 310 * explicitly. See also edc_run_cmd(). 311 */ 312 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 313 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 314 edc_intr(sc); 315 316 delay(100); 317 } 318 319 /* be quiet during probes */ 320 sc->sc_flags |= DASD_QUIET; 321 322 /* check for attached disks */ 323 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 324 eda.edc_drive = devno; 325 ldesc->len = 1; 326 ldesc->locs[EDCCF_DRIVE] = devno; 327 sc->sc_ed[devno] = 328 (void *) config_found_sm_loc(self, "edc", ldesc, &eda, 329 NULL, edcsubmatch); 330 331 /* If initialization did not succeed, NULL the pointer. */ 332 if (sc->sc_ed[devno] 333 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 334 sc->sc_ed[devno] = NULL; 335 } 336 337 /* enable full error dumps again */ 338 sc->sc_flags &= ~DASD_QUIET; 339 340 /* 341 * Check if there are any disks attached. If not, disestablish 342 * the interrupt. 343 */ 344 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 345 if (sc->sc_ed[devno]) 346 break; 347 } 348 349 if (devno == sc->sc_maxdevs) { 350 printf("%s: disabling controller (no drives attached)\n", 351 sc->sc_dev.dv_xname); 352 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 353 return; 354 } 355 356 /* 357 * Run the worker thread. 358 */ 359 config_pending_incr(); 360 kthread_create(edc_spawn_worker, (void *) sc); 361 } 362 363 void 364 edc_add_disk(sc, ed) 365 struct edc_mca_softc *sc; 366 struct ed_softc *ed; 367 { 368 sc->sc_ed[ed->sc_devno] = ed; 369 } 370 371 static int 372 edc_intr(arg) 373 void *arg; 374 { 375 struct edc_mca_softc *sc = arg; 376 u_int8_t isr, intr_id; 377 u_int16_t sifr; 378 int cmd=-1, devno; 379 380 /* 381 * Check if the interrupt was for us. 382 */ 383 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 384 return (0); 385 386 /* 387 * Read ISR to find out interrupt type. This also clears the interrupt 388 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 389 * and 4 are reserved and not used. 390 */ 391 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 392 intr_id = isr & ISR_INTR_ID_MASK; 393 394 #ifdef EDC_DEBUG 395 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 396 printf("%s: bogus interrupt id %d\n", sc->sc_dev.dv_xname, 397 (int) intr_id); 398 return (0); 399 } 400 #endif 401 402 /* Get number of device whose intr this was */ 403 devno = (isr & 0xe0) >> 5; 404 405 /* 406 * Get Status block. Higher byte always says how long the status 407 * block is, rest is device number and command code. 408 * Check the status block length against our supported maximum length 409 * and fetch the data. 410 */ 411 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 412 size_t len; 413 int i; 414 415 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 416 len = (sifr & 0xff00) >> 8; 417 #ifdef DEBUG 418 if (len > EDC_MAX_CMD_RES_LEN) 419 panic("%s: maximum Status Length exceeded: %d > %d", 420 sc->sc_dev.dv_xname, 421 len, EDC_MAX_CMD_RES_LEN); 422 #endif 423 424 /* Get command code */ 425 cmd = sifr & SIFR_CMD_MASK; 426 427 /* Read whole status block */ 428 sc->status_block[0] = sifr; 429 for(i=1; i < len; i++) { 430 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 431 & BSR_SIFR_FULL) == 0) 432 ; 433 434 sc->status_block[i] = le16toh( 435 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 436 } 437 /* zero out rest */ 438 if (i < EDC_MAX_CMD_RES_LEN) { 439 memset(&sc->status_block[i], 0, 440 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 441 } 442 } 443 444 switch (intr_id) { 445 case ISR_DATA_TRANSFER_RDY: 446 /* 447 * Ready to do DMA. The DMA controller has already been 448 * setup, now just kick disk controller to do the transfer. 449 */ 450 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 451 BCR_INT_ENABLE|BCR_DMA_ENABLE); 452 break; 453 454 case ISR_COMPLETED: 455 case ISR_COMPLETED_WITH_ECC: 456 case ISR_COMPLETED_RETRIES: 457 case ISR_COMPLETED_WARNING: 458 /* 459 * Copy device config data if appropriate. sc->sc_ed[] 460 * entry might be NULL during probe. 461 */ 462 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 463 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 464 sizeof(sc->sc_ed[devno]->sense_data)); 465 } 466 467 sc->sc_stat = STAT_DONE; 468 break; 469 470 case ISR_RESET_COMPLETED: 471 case ISR_ABORT_COMPLETED: 472 /* nothing to do */ 473 break; 474 475 case ISR_ATTN_ERROR: 476 /* 477 * Basically, this means driver bug or something seriously 478 * hosed. panic rather than extending the lossage. 479 * No status block available, so no further info. 480 */ 481 panic("%s: dev %d: attention error", 482 sc->sc_dev.dv_xname, 483 devno); 484 /* NOTREACHED */ 485 break; 486 487 default: 488 if ((sc->sc_flags & DASD_QUIET) == 0) 489 edc_dump_status_block(sc, sc->status_block, intr_id); 490 491 sc->sc_stat = STAT_ERROR; 492 break; 493 } 494 495 /* 496 * Unless the interrupt is for Data Transfer Ready or 497 * Attention Error, finish by assertion EOI. This makes 498 * attachment aware the interrupt is processed and system 499 * is ready to accept another one. 500 */ 501 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 502 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 503 504 /* If Read or Write Data, wakeup worker thread to finish it */ 505 if (intr_id != ISR_DATA_TRANSFER_RDY) { 506 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 507 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 508 wakeup_one(sc); 509 } 510 511 return (1); 512 } 513 514 /* 515 * This follows the exact order for Attention Request as 516 * written in DASD Storage Interface Specification MC (Rev 2.2). 517 */ 518 static int 519 edc_do_attn(sc, attn_type, devno, intr_id) 520 struct edc_mca_softc *sc; 521 int attn_type, devno, intr_id; 522 { 523 int tries; 524 525 /* 1. Disable interrupts in BCR. */ 526 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 527 528 /* 529 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 530 * a RESET COMPLETED interrupt. 531 */ 532 if (intr_id != ISR_RESET_COMPLETED) { 533 #ifdef EDC_DEBUG 534 if (attn_type == ATN_CMD_REQ 535 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 536 & BSR_INT_PENDING)) 537 panic("%s: edc int pending", sc->sc_dev.dv_xname); 538 #endif 539 540 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 541 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 542 & BSR_BUSY) == 0) 543 break; 544 } 545 546 if (tries == EDC_ATTN_MAXTRIES) { 547 printf("%s: edc_do_attn: timeout waiting for attachment to become available\n", 548 sc->sc_ed[devno]->sc_dev.dv_xname); 549 return (EIO); 550 } 551 } 552 553 /* 554 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 555 */ 556 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 557 558 /* 559 * 4. Enable interrupts via BCR. 560 */ 561 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 562 563 return (0); 564 } 565 566 /* 567 * Wait until command is processed, timeout after 'secs' seconds. 568 * We use mono_time, since we don't need actual RTC, just time 569 * interval. 570 */ 571 static void 572 edc_cmd_wait(sc, secs, poll) 573 struct edc_mca_softc *sc; 574 int secs, poll; 575 { 576 int val; 577 578 if (!poll) { 579 int s; 580 581 /* Not polling, can sleep. Sleep until we are awakened, 582 * but maximum secs seconds. 583 */ 584 s = splbio(); 585 if (sc->sc_stat != STAT_DONE) 586 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 587 splx(s); 588 } 589 590 /* Wait until the command is completely finished */ 591 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 592 & BSR_CMD_INPROGRESS) { 593 if (poll && (val & BSR_INTR)) 594 edc_intr(sc); 595 } 596 } 597 598 /* 599 * Command controller to execute specified command on a device. 600 */ 601 int 602 edc_run_cmd(sc, cmd, devno, cmd_args, cmd_len, poll) 603 struct edc_mca_softc *sc; 604 int cmd; 605 int devno; 606 u_int16_t cmd_args[]; 607 int cmd_len, poll; 608 { 609 int i, error, tries; 610 u_int16_t cmd0; 611 612 sc->sc_stat = STAT_START; 613 614 /* Do Attention Request for Command Request. */ 615 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 616 return (error); 617 618 /* 619 * Construct the command. The bits are like this: 620 * 621 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 622 * \_/ 0 0 1 0 \__/ \_____/ 623 * \ \__________/ \ \_ Command Code (see CMD_*) 624 * \ \ \__ Device: 0 common, 7 controller 625 * \ \__ Options: reserved, bit 10=cache bypass bit 626 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 627 * 628 * We always use device 0 or 1, so difference is made only by Command 629 * Code, Command Options and command length. 630 */ 631 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 632 | (devno << 5) 633 | (cmd_args[0] << 8) | cmd; 634 cmd_args[0] = cmd0; 635 636 /* 637 * Write word of CMD to the CIFR. This sets "Command 638 * Interface Register Full (CMD IN)" in BSR. Once the attachment 639 * detects it, it reads the word and clears CMD IN. This all should 640 * be quite fast, so don't sleep in !poll case neither. 641 */ 642 for(i=0; i < cmd_len; i++) { 643 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 644 htole16(cmd_args[i])); 645 646 /* Wait until CMD IN is cleared. */ 647 tries = 0; 648 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 649 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 650 delay(poll ? 1000 : 1); 651 ; 652 653 if (tries == 10000 654 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 655 & BSR_CIFR_FULL) { 656 printf("%s: device too slow to accept command %d\n", 657 sc->sc_dev.dv_xname, cmd); 658 return (EIO); 659 } 660 } 661 662 /* Wait for command to complete, but maximum 15 seconds. */ 663 edc_cmd_wait(sc, 15, poll); 664 665 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 666 } 667 668 #ifdef EDC_DEBUG 669 static const char * const edc_commands[] = { 670 "Invalid Command", 671 "Read Data", 672 "Write Data", 673 "Read Verify", 674 "Write with Verify", 675 "Seek", 676 "Park Head", 677 "Get Command Complete Status", 678 "Get Device Status", 679 "Get Device Configuration", 680 "Get POS Information", 681 "Translate RBA", 682 "Write Attachment Buffer", 683 "Read Attachment Buffer", 684 "Run Diagnostic Test", 685 "Get Diagnostic Status Block", 686 "Get MFG Header", 687 "Format Unit", 688 "Format Prepare", 689 "Set MAX RBA", 690 "Set Power Saving Mode", 691 "Power Conservation Command", 692 }; 693 694 static const char * const edc_cmd_status[256] = { 695 "Reserved", 696 "Command completed successfully", 697 "Reserved", 698 "Command completed successfully with ECC applied", 699 "Reserved", 700 "Command completed successfully with retries", 701 "Format Command partially completed", /* Status available */ 702 "Command completed successfully with ECC and retries", 703 "Command completed with Warning", /* Command Error is available */ 704 "Aborted", 705 "Reset completed", 706 "Data Transfer Ready", /* No Status Block available */ 707 "Command terminated with failure", /* Device Error is available */ 708 "DMA Error", /* Retry entire command as recovery */ 709 "Command Block Error", 710 "Attention Error (Illegal Attention Code)", 711 /* 0x14 - 0xff reserved */ 712 }; 713 714 static const char * const edc_cmd_error[256] = { 715 "No Error", 716 "Invalid parameter in the command block", 717 "Reserved", 718 "Command not supported", 719 "Command Aborted per request", 720 "Reserved", 721 "Command rejected", /* Attachment diagnostic failure */ 722 "Format Rejected", /* Prepare Format command is required */ 723 "Format Error (Primary Map is not readable)", 724 "Format Error (Secondary map is not readable)", 725 "Format Error (Diagnostic Failure)", 726 "Format Warning (Secondary Map Overflow)", 727 "Reserved" 728 "Format Error (Host Checksum Error)", 729 "Reserved", 730 "Format Warning (Push table overflow)", 731 "Format Warning (More pushes than allowed)", 732 "Reserved", 733 "Format Warning (Error during verifying)", 734 "Invalid device number for the command", 735 /* 0x14-0xff reserved */ 736 }; 737 738 static const char * const edc_dev_errors[] = { 739 "No Error", 740 "Seek Fault", /* Device report */ 741 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 742 "Block not found (ID not found)", 743 "Block not found (AM not found)", 744 "Data ECC Error (hard error)", 745 "ID CRC Error", 746 "RBA Out of Range", 747 "Reserved", 748 "Defective Block", 749 "Reserved", 750 "Selection Error", 751 "Reserved", 752 "Write Fault", 753 "No index or sector pulse", 754 "Device Not Ready", 755 "Seek Error", /* Attachment report */ 756 "Bad Format", 757 "Volume Overflow", 758 "No Data AM Found", 759 "Block not found (No ID AM or ID CRC error occurred)", 760 "Reserved", 761 "Reserved", 762 "No ID found on track (ID search)", 763 /* 0x19 - 0xff reserved */ 764 }; 765 #endif /* EDC_DEBUG */ 766 767 static void 768 edc_dump_status_block(sc, status_block, intr_id) 769 struct edc_mca_softc *sc; 770 u_int16_t *status_block; 771 int intr_id; 772 { 773 #ifdef EDC_DEBUG 774 printf("%s: Command: %s, Status: %s (intr %d)\n", 775 sc->sc_dev.dv_xname, 776 edc_commands[status_block[0] & 0x1f], 777 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 778 intr_id 779 ); 780 #else 781 printf("%s: Command: %d, Status: %d (intr %d)\n", 782 sc->sc_dev.dv_xname, 783 status_block[0] & 0x1f, 784 SB_GET_CMD_STATUS(status_block), 785 intr_id 786 ); 787 #endif 788 printf("%s: # left blocks: %u, last processed RBA: %u\n", 789 sc->sc_dev.dv_xname, 790 status_block[SB_RESBLKCNT_IDX], 791 (status_block[5] << 16) | status_block[4]); 792 793 if (intr_id == ISR_COMPLETED_WARNING) { 794 #ifdef EDC_DEBUG 795 printf("%s: Command Error Code: %s\n", 796 sc->sc_dev.dv_xname, 797 edc_cmd_error[status_block[1] & 0xff]); 798 #else 799 printf("%s: Command Error Code: %d\n", 800 sc->sc_dev.dv_xname, 801 status_block[1] & 0xff); 802 #endif 803 } 804 805 if (intr_id == ISR_CMD_FAILED) { 806 #ifdef EDC_DEBUG 807 char buf[100]; 808 809 printf("%s: Device Error Code: %s\n", 810 sc->sc_dev.dv_xname, 811 edc_dev_errors[status_block[2] & 0xff]); 812 bitmask_snprintf((status_block[2] & 0xff00) >> 8, 813 "\20" 814 "\01SeekOrCmdComplete" 815 "\02Track0Flag" 816 "\03WriteFault" 817 "\04Selected" 818 "\05Ready" 819 "\06Reserved0" 820 "\07STANDBY" 821 "\010Reserved0", 822 buf, sizeof(buf)); 823 printf("%s: Device Status: %s\n", 824 sc->sc_dev.dv_xname, buf); 825 #else 826 printf("%s: Device Error Code: %d, Device Status: %d\n", 827 sc->sc_dev.dv_xname, 828 status_block[2] & 0xff, 829 (status_block[2] & 0xff00) >> 8); 830 #endif 831 } 832 } 833 834 static void 835 edc_spawn_worker(arg) 836 void *arg; 837 { 838 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 839 int error; 840 struct proc *wrk; 841 842 /* Now, everything is ready, start a kthread */ 843 if ((error = kthread_create1(edcworker, sc, &wrk, 844 "%s", sc->sc_dev.dv_xname))) { 845 printf("%s: cannot spawn worker thread: errno=%d\n", 846 sc->sc_dev.dv_xname, error); 847 panic("edc_spawn_worker"); 848 } 849 } 850 851 /* 852 * Main worker thread function. 853 */ 854 void 855 edcworker(arg) 856 void *arg; 857 { 858 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 859 struct ed_softc *ed; 860 struct buf *bp; 861 int i, error; 862 863 config_pending_decr(); 864 865 for(;;) { 866 /* Wait until awakened */ 867 (void) tsleep(sc, PRIBIO, "edcidle", 0); 868 869 for(i=0; i<sc->sc_maxdevs; ) { 870 if ((ed = sc->sc_ed[i]) == NULL) { 871 i++; 872 continue; 873 } 874 875 /* Is there a buf for us ? */ 876 simple_lock(&ed->sc_q_lock); 877 if ((bp = BUFQ_GET(&ed->sc_q)) == NULL) { 878 simple_unlock(&ed->sc_q_lock); 879 i++; 880 continue; 881 } 882 simple_unlock(&ed->sc_q_lock); 883 884 /* Instrumentation. */ 885 disk_busy(&ed->sc_dk); 886 887 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 888 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 889 890 if (error) { 891 bp->b_error = error; 892 bp->b_flags |= B_ERROR; 893 } else { 894 /* Set resid, most commonly to zero. */ 895 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 896 } 897 898 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 899 (bp->b_flags & B_READ)); 900 #if NRND > 0 901 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 902 #endif 903 biodone(bp); 904 } 905 } 906 } 907 908 int 909 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 910 size_t bcount, daddr_t rawblkno, int isread, int poll) 911 { 912 u_int16_t cmd_args[4]; 913 int error=0, fl; 914 u_int16_t track; 915 u_int16_t cyl; 916 u_int8_t head; 917 u_int8_t sector; 918 919 mca_disk_busy(); 920 921 /* set WAIT and R/W flag appropriately for the DMA transfer */ 922 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 923 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 924 925 /* Load the buffer for DMA transfer. */ 926 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 927 bcount, NULL, BUS_DMA_STREAMING|fl))) { 928 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 929 ed->sc_dev.dv_xname, error); 930 goto out; 931 } 932 933 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 934 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 935 936 track = rawblkno / ed->sectors; 937 head = track % ed->heads; 938 cyl = track / ed->heads; 939 sector = rawblkno % ed->sectors; 940 941 /* Read or Write Data command */ 942 cmd_args[0] = 2; /* Options 0000010 */ 943 cmd_args[1] = bcount / DEV_BSIZE; 944 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 945 cmd_args[3] = ((cyl & 0x3E0) >> 5); 946 error = edc_run_cmd(sc, 947 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 948 ed->sc_devno, cmd_args, 4, poll); 949 950 /* Sync the DMA memory */ 951 if (!error) { 952 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 953 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 954 } 955 956 /* We are done, unload buffer from DMA map */ 957 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 958 959 out: 960 mca_disk_unbusy(); 961 962 return (error); 963 } 964