1 /* $NetBSD: edc_mca.c,v 1.34 2006/10/12 01:31:25 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jaromir Dolecek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 38 * spec. 39 * 40 * The driver was written with DASD Storage Interface Specification 41 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>. 42 * 43 * TODO: 44 * - improve error recovery 45 * Issue soft reset on error or timeout? 46 * - test with > 1 disk (this is supported by some controllers) 47 * - test with > 1 ESDI controller in machine; shared interrupts 48 * necessary for this to work should be supported - edc_intr() specifically 49 * checks if the interrupt is for this controller 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.34 2006/10/12 01:31:25 christos Exp $"); 54 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/buf.h> 60 #include <sys/bufq.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 #include <sys/malloc.h> 64 #include <sys/endian.h> 65 #include <sys/disklabel.h> 66 #include <sys/disk.h> 67 #include <sys/syslog.h> 68 #include <sys/proc.h> 69 #include <sys/vnode.h> 70 #include <sys/kernel.h> 71 #include <sys/kthread.h> 72 #if NRND > 0 73 #include <sys/rnd.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/mca/mcareg.h> 80 #include <dev/mca/mcavar.h> 81 #include <dev/mca/mcadevs.h> 82 83 #include <dev/mca/edcreg.h> 84 #include <dev/mca/edvar.h> 85 #include <dev/mca/edcvar.h> 86 87 #include "locators.h" 88 89 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 90 #define EDC_MAX_CMD_RES_LEN 8 91 92 struct edc_mca_softc { 93 struct device sc_dev; 94 95 bus_space_tag_t sc_iot; 96 bus_space_handle_t sc_ioh; 97 98 /* DMA related stuff */ 99 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 100 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 101 102 void *sc_ih; /* interrupt handle */ 103 104 int sc_flags; 105 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 106 107 #define DASD_MAXDEVS 8 108 struct ed_softc *sc_ed[DASD_MAXDEVS]; 109 int sc_maxdevs; /* max number of disks attached to this 110 * controller */ 111 112 /* I/O results variables */ 113 volatile int sc_stat; 114 #define STAT_START 0 115 #define STAT_ERROR 1 116 #define STAT_DONE 2 117 volatile int sc_resblk; /* residual block count */ 118 119 /* CMD status block - only set & used in edc_intr() */ 120 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 121 }; 122 123 int edc_mca_probe(struct device *, struct cfdata *, void *); 124 void edc_mca_attach(struct device *, struct device *, void *); 125 126 CFATTACH_DECL(edc_mca, sizeof(struct edc_mca_softc), 127 edc_mca_probe, edc_mca_attach, NULL, NULL); 128 129 static int edc_intr(void *); 130 static void edc_dump_status_block(struct edc_mca_softc *, 131 u_int16_t *, int); 132 static int edc_do_attn(struct edc_mca_softc *, int, int, int); 133 static void edc_cmd_wait(struct edc_mca_softc *, int, int); 134 static void edcworker(void *); 135 static void edc_spawn_worker(void *); 136 137 int 138 edc_mca_probe(struct device *parent __unused, struct cfdata *match __unused, 139 void *aux) 140 { 141 struct mca_attach_args *ma = aux; 142 143 switch (ma->ma_id) { 144 case MCA_PRODUCT_IBM_ESDIC: 145 case MCA_PRODUCT_IBM_ESDIC_IG: 146 return (1); 147 default: 148 return (0); 149 } 150 } 151 152 void 153 edc_mca_attach(struct device *parent __unused, struct device *self, void *aux) 154 { 155 struct edc_mca_softc *sc = device_private(self); 156 struct mca_attach_args *ma = aux; 157 struct ed_attach_args eda; 158 int pos2, pos3, pos4; 159 int irq, drq, iobase; 160 const char *typestr; 161 int devno, error; 162 int locs[EDCCF_NLOCS]; 163 164 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 165 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 166 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 167 168 /* 169 * POS register 2: (adf pos0) 170 * 171 * 7 6 5 4 3 2 1 0 172 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 173 * \ \ \___ Primary/Alternate Port Addresses: 174 * \ \ 0=0x3510-3517 1=0x3518-0x351f 175 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 176 * \ 0000=0 0001=1 0011=3 0100=4 177 * \_________ Fairness On/Off: 1=On 0=Off 178 * 179 * POS register 3: (adf pos1) 180 * 181 * 7 6 5 4 3 2 1 0 182 * 0 0 \_/ 183 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 184 * 01=16ms 00=Burst Disabled 185 * 186 * POS register 4: (adf pos2) 187 * 188 * 7 6 5 4 3 2 1 0 189 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 190 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 191 * 192 * IRQ is fixed to 14 (0x0e). 193 */ 194 195 switch (ma->ma_id) { 196 case MCA_PRODUCT_IBM_ESDIC: 197 typestr = "IBM ESDI Fixed Disk Controller"; 198 break; 199 case MCA_PRODUCT_IBM_ESDIC_IG: 200 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 201 break; 202 default: 203 typestr = NULL; 204 break; 205 } 206 207 irq = ESDIC_IRQ; 208 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 209 drq = (pos2 & DRQ_MASK) >> 2; 210 211 printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 212 irq, drq, typestr); 213 214 #ifdef DIAGNOSTIC 215 /* 216 * It's not strictly necessary to check this, machine configuration 217 * utility uses only valid addresses. 218 */ 219 if (drq == 2 || drq >= 8) { 220 printf("%s: invalid DMA Arbitration Level %d\n", 221 sc->sc_dev.dv_xname, drq); 222 return; 223 } 224 #endif 225 226 printf("%s: Fairness %s, Release %s, ", 227 sc->sc_dev.dv_xname, 228 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 229 (pos4 & RELEASE_1) ? "6ms" 230 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 231 ); 232 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 233 static const char * const pacint[] = 234 { "disabled", "16ms", "24ms", "31ms"}; 235 printf("DMA burst pacing interval %s\n", 236 pacint[(pos3 & PACING_INT_MASK) >> 4]); 237 } else 238 printf("DMA pacing control disabled\n"); 239 240 sc->sc_iot = ma->ma_iot; 241 242 if (bus_space_map(sc->sc_iot, iobase, 243 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 244 printf("%s: couldn't map registers\n", 245 sc->sc_dev.dv_xname); 246 return; 247 } 248 249 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 250 if (sc->sc_ih == NULL) { 251 printf("%s: couldn't establish interrupt handler\n", 252 sc->sc_dev.dv_xname); 253 return; 254 } 255 256 /* Create a MCA DMA map, used for data transfer */ 257 sc->sc_dmat = ma->ma_dmat; 258 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 259 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 260 &sc->sc_dmamap_xfer, drq)) != 0){ 261 printf("%s: couldn't create DMA map - error %d\n", 262 sc->sc_dev.dv_xname, error); 263 return; 264 } 265 266 /* 267 * Integrated ESDI controller supports only one disk, other 268 * controllers support two disks. 269 */ 270 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 271 sc->sc_maxdevs = 1; 272 else 273 sc->sc_maxdevs = 2; 274 275 /* 276 * Reset controller and attach individual disks. ed attach routine 277 * uses polling so that this works with interrupts disabled. 278 */ 279 280 /* Do a reset to ensure sane state after warm boot. */ 281 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 282 /* hard reset */ 283 printf("%s: controller busy, performing hardware reset ...\n", 284 sc->sc_dev.dv_xname); 285 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 286 BCR_INT_ENABLE|BCR_RESET); 287 } else { 288 /* "SOFT" reset */ 289 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 290 } 291 292 /* 293 * Since interrupts are disabled, it's necessary 294 * to detect the interrupt request and call edc_intr() 295 * explicitly. See also edc_run_cmd(). 296 */ 297 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 298 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 299 edc_intr(sc); 300 301 delay(100); 302 } 303 304 /* be quiet during probes */ 305 sc->sc_flags |= DASD_QUIET; 306 307 /* check for attached disks */ 308 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 309 eda.edc_drive = devno; 310 locs[EDCCF_DRIVE] = devno; 311 sc->sc_ed[devno] = 312 (void *) config_found_sm_loc(self, "edc", locs, &eda, 313 NULL, config_stdsubmatch); 314 315 /* If initialization did not succeed, NULL the pointer. */ 316 if (sc->sc_ed[devno] 317 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 318 sc->sc_ed[devno] = NULL; 319 } 320 321 /* enable full error dumps again */ 322 sc->sc_flags &= ~DASD_QUIET; 323 324 /* 325 * Check if there are any disks attached. If not, disestablish 326 * the interrupt. 327 */ 328 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 329 if (sc->sc_ed[devno]) 330 break; 331 } 332 333 if (devno == sc->sc_maxdevs) { 334 printf("%s: disabling controller (no drives attached)\n", 335 sc->sc_dev.dv_xname); 336 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 337 return; 338 } 339 340 /* 341 * Run the worker thread. 342 */ 343 config_pending_incr(); 344 kthread_create(edc_spawn_worker, (void *) sc); 345 } 346 347 void 348 edc_add_disk(struct edc_mca_softc *sc, struct ed_softc *ed) 349 { 350 sc->sc_ed[ed->sc_devno] = ed; 351 } 352 353 static int 354 edc_intr(void *arg) 355 { 356 struct edc_mca_softc *sc = arg; 357 u_int8_t isr, intr_id; 358 u_int16_t sifr; 359 int cmd=-1, devno; 360 361 /* 362 * Check if the interrupt was for us. 363 */ 364 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 365 return (0); 366 367 /* 368 * Read ISR to find out interrupt type. This also clears the interrupt 369 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 370 * and 4 are reserved and not used. 371 */ 372 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 373 intr_id = isr & ISR_INTR_ID_MASK; 374 375 #ifdef EDC_DEBUG 376 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 377 printf("%s: bogus interrupt id %d\n", sc->sc_dev.dv_xname, 378 (int) intr_id); 379 return (0); 380 } 381 #endif 382 383 /* Get number of device whose intr this was */ 384 devno = (isr & 0xe0) >> 5; 385 386 /* 387 * Get Status block. Higher byte always says how long the status 388 * block is, rest is device number and command code. 389 * Check the status block length against our supported maximum length 390 * and fetch the data. 391 */ 392 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 393 size_t len; 394 int i; 395 396 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 397 len = (sifr & 0xff00) >> 8; 398 #ifdef DEBUG 399 if (len > EDC_MAX_CMD_RES_LEN) 400 panic("%s: maximum Status Length exceeded: %d > %d", 401 sc->sc_dev.dv_xname, 402 len, EDC_MAX_CMD_RES_LEN); 403 #endif 404 405 /* Get command code */ 406 cmd = sifr & SIFR_CMD_MASK; 407 408 /* Read whole status block */ 409 sc->status_block[0] = sifr; 410 for(i=1; i < len; i++) { 411 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 412 & BSR_SIFR_FULL) == 0) 413 ; 414 415 sc->status_block[i] = le16toh( 416 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 417 } 418 /* zero out rest */ 419 if (i < EDC_MAX_CMD_RES_LEN) { 420 memset(&sc->status_block[i], 0, 421 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 422 } 423 } 424 425 switch (intr_id) { 426 case ISR_DATA_TRANSFER_RDY: 427 /* 428 * Ready to do DMA. The DMA controller has already been 429 * setup, now just kick disk controller to do the transfer. 430 */ 431 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 432 BCR_INT_ENABLE|BCR_DMA_ENABLE); 433 break; 434 435 case ISR_COMPLETED: 436 case ISR_COMPLETED_WITH_ECC: 437 case ISR_COMPLETED_RETRIES: 438 case ISR_COMPLETED_WARNING: 439 /* 440 * Copy device config data if appropriate. sc->sc_ed[] 441 * entry might be NULL during probe. 442 */ 443 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 444 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 445 sizeof(sc->sc_ed[devno]->sense_data)); 446 } 447 448 sc->sc_stat = STAT_DONE; 449 break; 450 451 case ISR_RESET_COMPLETED: 452 case ISR_ABORT_COMPLETED: 453 /* nothing to do */ 454 break; 455 456 case ISR_ATTN_ERROR: 457 /* 458 * Basically, this means driver bug or something seriously 459 * hosed. panic rather than extending the lossage. 460 * No status block available, so no further info. 461 */ 462 panic("%s: dev %d: attention error", 463 sc->sc_dev.dv_xname, 464 devno); 465 /* NOTREACHED */ 466 break; 467 468 default: 469 if ((sc->sc_flags & DASD_QUIET) == 0) 470 edc_dump_status_block(sc, sc->status_block, intr_id); 471 472 sc->sc_stat = STAT_ERROR; 473 break; 474 } 475 476 /* 477 * Unless the interrupt is for Data Transfer Ready or 478 * Attention Error, finish by assertion EOI. This makes 479 * attachment aware the interrupt is processed and system 480 * is ready to accept another one. 481 */ 482 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 483 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 484 485 /* If Read or Write Data, wakeup worker thread to finish it */ 486 if (intr_id != ISR_DATA_TRANSFER_RDY) { 487 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 488 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 489 wakeup_one(sc); 490 } 491 492 return (1); 493 } 494 495 /* 496 * This follows the exact order for Attention Request as 497 * written in DASD Storage Interface Specification MC (Rev 2.2). 498 */ 499 static int 500 edc_do_attn(struct edc_mca_softc *sc, int attn_type, int devno, int intr_id) 501 { 502 int tries; 503 504 /* 1. Disable interrupts in BCR. */ 505 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 506 507 /* 508 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 509 * a RESET COMPLETED interrupt. 510 */ 511 if (intr_id != ISR_RESET_COMPLETED) { 512 #ifdef EDC_DEBUG 513 if (attn_type == ATN_CMD_REQ 514 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 515 & BSR_INT_PENDING)) 516 panic("%s: edc int pending", sc->sc_dev.dv_xname); 517 #endif 518 519 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 520 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 521 & BSR_BUSY) == 0) 522 break; 523 } 524 525 if (tries == EDC_ATTN_MAXTRIES) { 526 printf("%s: edc_do_attn: timeout waiting for attachment to become available\n", 527 sc->sc_ed[devno]->sc_dev.dv_xname); 528 return (EIO); 529 } 530 } 531 532 /* 533 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 534 */ 535 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 536 537 /* 538 * 4. Enable interrupts via BCR. 539 */ 540 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 541 542 return (0); 543 } 544 545 /* 546 * Wait until command is processed, timeout after 'secs' seconds. 547 * We use mono_time, since we don't need actual RTC, just time 548 * interval. 549 */ 550 static void 551 edc_cmd_wait(struct edc_mca_softc *sc, int secs, int poll) 552 { 553 int val; 554 555 if (!poll) { 556 int s; 557 558 /* Not polling, can sleep. Sleep until we are awakened, 559 * but maximum secs seconds. 560 */ 561 s = splbio(); 562 if (sc->sc_stat != STAT_DONE) 563 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 564 splx(s); 565 } 566 567 /* Wait until the command is completely finished */ 568 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 569 & BSR_CMD_INPROGRESS) { 570 if (poll && (val & BSR_INTR)) 571 edc_intr(sc); 572 } 573 } 574 575 /* 576 * Command controller to execute specified command on a device. 577 */ 578 int 579 edc_run_cmd(struct edc_mca_softc *sc, int cmd, int devno, 580 u_int16_t cmd_args[], int cmd_len, int poll) 581 { 582 int i, error, tries; 583 u_int16_t cmd0; 584 585 sc->sc_stat = STAT_START; 586 587 /* Do Attention Request for Command Request. */ 588 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 589 return (error); 590 591 /* 592 * Construct the command. The bits are like this: 593 * 594 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 595 * \_/ 0 0 1 0 \__/ \_____/ 596 * \ \__________/ \ \_ Command Code (see CMD_*) 597 * \ \ \__ Device: 0 common, 7 controller 598 * \ \__ Options: reserved, bit 10=cache bypass bit 599 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 600 * 601 * We always use device 0 or 1, so difference is made only by Command 602 * Code, Command Options and command length. 603 */ 604 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 605 | (devno << 5) 606 | (cmd_args[0] << 8) | cmd; 607 cmd_args[0] = cmd0; 608 609 /* 610 * Write word of CMD to the CIFR. This sets "Command 611 * Interface Register Full (CMD IN)" in BSR. Once the attachment 612 * detects it, it reads the word and clears CMD IN. This all should 613 * be quite fast, so don't sleep in !poll case neither. 614 */ 615 for(i=0; i < cmd_len; i++) { 616 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 617 htole16(cmd_args[i])); 618 619 /* Wait until CMD IN is cleared. */ 620 tries = 0; 621 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 622 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 623 delay(poll ? 1000 : 1); 624 ; 625 626 if (tries == 10000 627 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 628 & BSR_CIFR_FULL) { 629 printf("%s: device too slow to accept command %d\n", 630 sc->sc_dev.dv_xname, cmd); 631 return (EIO); 632 } 633 } 634 635 /* Wait for command to complete, but maximum 15 seconds. */ 636 edc_cmd_wait(sc, 15, poll); 637 638 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 639 } 640 641 #ifdef EDC_DEBUG 642 static const char * const edc_commands[] = { 643 "Invalid Command", 644 "Read Data", 645 "Write Data", 646 "Read Verify", 647 "Write with Verify", 648 "Seek", 649 "Park Head", 650 "Get Command Complete Status", 651 "Get Device Status", 652 "Get Device Configuration", 653 "Get POS Information", 654 "Translate RBA", 655 "Write Attachment Buffer", 656 "Read Attachment Buffer", 657 "Run Diagnostic Test", 658 "Get Diagnostic Status Block", 659 "Get MFG Header", 660 "Format Unit", 661 "Format Prepare", 662 "Set MAX RBA", 663 "Set Power Saving Mode", 664 "Power Conservation Command", 665 }; 666 667 static const char * const edc_cmd_status[256] = { 668 "Reserved", 669 "Command completed successfully", 670 "Reserved", 671 "Command completed successfully with ECC applied", 672 "Reserved", 673 "Command completed successfully with retries", 674 "Format Command partially completed", /* Status available */ 675 "Command completed successfully with ECC and retries", 676 "Command completed with Warning", /* Command Error is available */ 677 "Aborted", 678 "Reset completed", 679 "Data Transfer Ready", /* No Status Block available */ 680 "Command terminated with failure", /* Device Error is available */ 681 "DMA Error", /* Retry entire command as recovery */ 682 "Command Block Error", 683 "Attention Error (Illegal Attention Code)", 684 /* 0x14 - 0xff reserved */ 685 }; 686 687 static const char * const edc_cmd_error[256] = { 688 "No Error", 689 "Invalid parameter in the command block", 690 "Reserved", 691 "Command not supported", 692 "Command Aborted per request", 693 "Reserved", 694 "Command rejected", /* Attachment diagnostic failure */ 695 "Format Rejected", /* Prepare Format command is required */ 696 "Format Error (Primary Map is not readable)", 697 "Format Error (Secondary map is not readable)", 698 "Format Error (Diagnostic Failure)", 699 "Format Warning (Secondary Map Overflow)", 700 "Reserved" 701 "Format Error (Host Checksum Error)", 702 "Reserved", 703 "Format Warning (Push table overflow)", 704 "Format Warning (More pushes than allowed)", 705 "Reserved", 706 "Format Warning (Error during verifying)", 707 "Invalid device number for the command", 708 /* 0x14-0xff reserved */ 709 }; 710 711 static const char * const edc_dev_errors[] = { 712 "No Error", 713 "Seek Fault", /* Device report */ 714 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 715 "Block not found (ID not found)", 716 "Block not found (AM not found)", 717 "Data ECC Error (hard error)", 718 "ID CRC Error", 719 "RBA Out of Range", 720 "Reserved", 721 "Defective Block", 722 "Reserved", 723 "Selection Error", 724 "Reserved", 725 "Write Fault", 726 "No index or sector pulse", 727 "Device Not Ready", 728 "Seek Error", /* Attachment report */ 729 "Bad Format", 730 "Volume Overflow", 731 "No Data AM Found", 732 "Block not found (No ID AM or ID CRC error occurred)", 733 "Reserved", 734 "Reserved", 735 "No ID found on track (ID search)", 736 /* 0x19 - 0xff reserved */ 737 }; 738 #endif /* EDC_DEBUG */ 739 740 static void 741 edc_dump_status_block(struct edc_mca_softc *sc, u_int16_t *status_block, 742 int intr_id) 743 { 744 #ifdef EDC_DEBUG 745 printf("%s: Command: %s, Status: %s (intr %d)\n", 746 sc->sc_dev.dv_xname, 747 edc_commands[status_block[0] & 0x1f], 748 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 749 intr_id 750 ); 751 #else 752 printf("%s: Command: %d, Status: %d (intr %d)\n", 753 sc->sc_dev.dv_xname, 754 status_block[0] & 0x1f, 755 SB_GET_CMD_STATUS(status_block), 756 intr_id 757 ); 758 #endif 759 printf("%s: # left blocks: %u, last processed RBA: %u\n", 760 sc->sc_dev.dv_xname, 761 status_block[SB_RESBLKCNT_IDX], 762 (status_block[5] << 16) | status_block[4]); 763 764 if (intr_id == ISR_COMPLETED_WARNING) { 765 #ifdef EDC_DEBUG 766 printf("%s: Command Error Code: %s\n", 767 sc->sc_dev.dv_xname, 768 edc_cmd_error[status_block[1] & 0xff]); 769 #else 770 printf("%s: Command Error Code: %d\n", 771 sc->sc_dev.dv_xname, 772 status_block[1] & 0xff); 773 #endif 774 } 775 776 if (intr_id == ISR_CMD_FAILED) { 777 #ifdef EDC_DEBUG 778 char buf[100]; 779 780 printf("%s: Device Error Code: %s\n", 781 sc->sc_dev.dv_xname, 782 edc_dev_errors[status_block[2] & 0xff]); 783 bitmask_snprintf((status_block[2] & 0xff00) >> 8, 784 "\20" 785 "\01SeekOrCmdComplete" 786 "\02Track0Flag" 787 "\03WriteFault" 788 "\04Selected" 789 "\05Ready" 790 "\06Reserved0" 791 "\07STANDBY" 792 "\010Reserved0", 793 buf, sizeof(buf)); 794 printf("%s: Device Status: %s\n", 795 sc->sc_dev.dv_xname, buf); 796 #else 797 printf("%s: Device Error Code: %d, Device Status: %d\n", 798 sc->sc_dev.dv_xname, 799 status_block[2] & 0xff, 800 (status_block[2] & 0xff00) >> 8); 801 #endif 802 } 803 } 804 805 static void 806 edc_spawn_worker(void *arg) 807 { 808 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 809 int error; 810 struct proc *wrk; 811 812 /* Now, everything is ready, start a kthread */ 813 if ((error = kthread_create1(edcworker, sc, &wrk, 814 "%s", sc->sc_dev.dv_xname))) { 815 printf("%s: cannot spawn worker thread: errno=%d\n", 816 sc->sc_dev.dv_xname, error); 817 panic("edc_spawn_worker"); 818 } 819 } 820 821 /* 822 * Main worker thread function. 823 */ 824 void 825 edcworker(void *arg) 826 { 827 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 828 struct ed_softc *ed; 829 struct buf *bp; 830 int i, error; 831 832 config_pending_decr(); 833 834 for(;;) { 835 /* Wait until awakened */ 836 (void) tsleep(sc, PRIBIO, "edcidle", 0); 837 838 for(i=0; i<sc->sc_maxdevs; ) { 839 if ((ed = sc->sc_ed[i]) == NULL) { 840 i++; 841 continue; 842 } 843 844 /* Is there a buf for us ? */ 845 simple_lock(&ed->sc_q_lock); 846 if ((bp = BUFQ_GET(ed->sc_q)) == NULL) { 847 simple_unlock(&ed->sc_q_lock); 848 i++; 849 continue; 850 } 851 simple_unlock(&ed->sc_q_lock); 852 853 /* Instrumentation. */ 854 disk_busy(&ed->sc_dk); 855 856 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 857 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 858 859 if (error) { 860 bp->b_error = error; 861 bp->b_flags |= B_ERROR; 862 } else { 863 /* Set resid, most commonly to zero. */ 864 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 865 } 866 867 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 868 (bp->b_flags & B_READ)); 869 #if NRND > 0 870 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 871 #endif 872 biodone(bp); 873 } 874 } 875 } 876 877 int 878 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 879 size_t bcount, daddr_t rawblkno, int isread, int poll) 880 { 881 u_int16_t cmd_args[4]; 882 int error=0, fl; 883 u_int16_t track; 884 u_int16_t cyl; 885 u_int8_t head; 886 u_int8_t sector; 887 888 mca_disk_busy(); 889 890 /* set WAIT and R/W flag appropriately for the DMA transfer */ 891 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 892 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 893 894 /* Load the buffer for DMA transfer. */ 895 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 896 bcount, NULL, BUS_DMA_STREAMING|fl))) { 897 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 898 ed->sc_dev.dv_xname, error); 899 goto out; 900 } 901 902 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 903 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 904 905 track = rawblkno / ed->sectors; 906 head = track % ed->heads; 907 cyl = track / ed->heads; 908 sector = rawblkno % ed->sectors; 909 910 /* Read or Write Data command */ 911 cmd_args[0] = 2; /* Options 0000010 */ 912 cmd_args[1] = bcount / DEV_BSIZE; 913 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 914 cmd_args[3] = ((cyl & 0x3E0) >> 5); 915 error = edc_run_cmd(sc, 916 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 917 ed->sc_devno, cmd_args, 4, poll); 918 919 /* Sync the DMA memory */ 920 if (!error) { 921 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 922 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 923 } 924 925 /* We are done, unload buffer from DMA map */ 926 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 927 928 out: 929 mca_disk_unbusy(); 930 931 return (error); 932 } 933