1 /* $NetBSD: edc_mca.c,v 1.50 2015/04/13 16:33:24 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jaromir Dolecek. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 34 * spec. 35 * 36 * The driver was written with DASD Storage Interface Specification 37 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>. 38 * 39 * TODO: 40 * - improve error recovery 41 * Issue soft reset on error or timeout? 42 * - test with > 1 disk (this is supported by some controllers) 43 * - test with > 1 ESDI controller in machine; shared interrupts 44 * necessary for this to work should be supported - edc_intr() specifically 45 * checks if the interrupt is for this controller 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.50 2015/04/13 16:33:24 riastradh Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/buf.h> 54 #include <sys/bufq.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/endian.h> 59 #include <sys/disklabel.h> 60 #include <sys/disk.h> 61 #include <sys/syslog.h> 62 #include <sys/proc.h> 63 #include <sys/vnode.h> 64 #include <sys/kernel.h> 65 #include <sys/kthread.h> 66 #include <sys/rndsource.h> 67 68 #include <sys/bus.h> 69 #include <sys/intr.h> 70 71 #include <dev/mca/mcareg.h> 72 #include <dev/mca/mcavar.h> 73 #include <dev/mca/mcadevs.h> 74 75 #include <dev/mca/edcreg.h> 76 #include <dev/mca/edvar.h> 77 #include <dev/mca/edcvar.h> 78 79 #include "locators.h" 80 81 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 82 #define EDC_MAX_CMD_RES_LEN 8 83 84 struct edc_mca_softc { 85 device_t sc_dev; 86 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 90 /* DMA related stuff */ 91 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 92 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 93 94 void *sc_ih; /* interrupt handle */ 95 96 int sc_flags; 97 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 98 99 #define DASD_MAXDEVS 8 100 struct ed_softc *sc_ed[DASD_MAXDEVS]; 101 int sc_maxdevs; /* max number of disks attached to this 102 * controller */ 103 104 /* I/O results variables */ 105 volatile int sc_stat; 106 #define STAT_START 0 107 #define STAT_ERROR 1 108 #define STAT_DONE 2 109 volatile int sc_resblk; /* residual block count */ 110 111 /* CMD status block - only set & used in edc_intr() */ 112 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 113 }; 114 115 int edc_mca_probe(device_t, cfdata_t, void *); 116 void edc_mca_attach(device_t, device_t, void *); 117 118 CFATTACH_DECL_NEW(edc_mca, sizeof(struct edc_mca_softc), 119 edc_mca_probe, edc_mca_attach, NULL, NULL); 120 121 static int edc_intr(void *); 122 static void edc_dump_status_block(struct edc_mca_softc *, 123 u_int16_t *, int); 124 static int edc_do_attn(struct edc_mca_softc *, int, int, int); 125 static void edc_cmd_wait(struct edc_mca_softc *, int, int); 126 static void edcworker(void *); 127 128 int 129 edc_mca_probe(device_t parent, cfdata_t match, void *aux) 130 { 131 struct mca_attach_args *ma = aux; 132 133 switch (ma->ma_id) { 134 case MCA_PRODUCT_IBM_ESDIC: 135 case MCA_PRODUCT_IBM_ESDIC_IG: 136 return (1); 137 default: 138 return (0); 139 } 140 } 141 142 void 143 edc_mca_attach(device_t parent, device_t self, void *aux) 144 { 145 struct edc_mca_softc *sc = device_private(self); 146 struct mca_attach_args *ma = aux; 147 struct ed_attach_args eda; 148 int pos2, pos3, pos4; 149 int irq, drq, iobase; 150 const char *typestr; 151 int devno, error; 152 int locs[EDCCF_NLOCS]; 153 154 sc->sc_dev = self; 155 156 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 157 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 158 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 159 160 /* 161 * POS register 2: (adf pos0) 162 * 163 * 7 6 5 4 3 2 1 0 164 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 165 * \ \ \___ Primary/Alternate Port Addresses: 166 * \ \ 0=0x3510-3517 1=0x3518-0x351f 167 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 168 * \ 0000=0 0001=1 0011=3 0100=4 169 * \_________ Fairness On/Off: 1=On 0=Off 170 * 171 * POS register 3: (adf pos1) 172 * 173 * 7 6 5 4 3 2 1 0 174 * 0 0 \_/ 175 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 176 * 01=16ms 00=Burst Disabled 177 * 178 * POS register 4: (adf pos2) 179 * 180 * 7 6 5 4 3 2 1 0 181 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 182 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 183 * 184 * IRQ is fixed to 14 (0x0e). 185 */ 186 187 switch (ma->ma_id) { 188 case MCA_PRODUCT_IBM_ESDIC: 189 typestr = "IBM ESDI Fixed Disk Controller"; 190 break; 191 case MCA_PRODUCT_IBM_ESDIC_IG: 192 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 193 break; 194 default: 195 typestr = NULL; 196 break; 197 } 198 199 irq = ESDIC_IRQ; 200 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 201 drq = (pos2 & DRQ_MASK) >> 2; 202 203 printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 204 irq, drq, typestr); 205 206 #ifdef DIAGNOSTIC 207 /* 208 * It's not strictly necessary to check this, machine configuration 209 * utility uses only valid addresses. 210 */ 211 if (drq == 2 || drq >= 8) { 212 aprint_error_dev(sc->sc_dev, "invalid DMA Arbitration Level %d\n", drq); 213 return; 214 } 215 #endif 216 217 printf("%s: Fairness %s, Release %s, ", 218 device_xname(sc->sc_dev), 219 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 220 (pos4 & RELEASE_1) ? "6ms" 221 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 222 ); 223 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 224 static const char * const pacint[] = 225 { "disabled", "16ms", "24ms", "31ms"}; 226 printf("DMA burst pacing interval %s\n", 227 pacint[(pos3 & PACING_INT_MASK) >> 4]); 228 } else 229 printf("DMA pacing control disabled\n"); 230 231 sc->sc_iot = ma->ma_iot; 232 233 if (bus_space_map(sc->sc_iot, iobase, 234 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 235 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 236 return; 237 } 238 239 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 240 if (sc->sc_ih == NULL) { 241 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt handler\n"); 242 return; 243 } 244 245 /* Create a MCA DMA map, used for data transfer */ 246 sc->sc_dmat = ma->ma_dmat; 247 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 248 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 249 &sc->sc_dmamap_xfer, drq)) != 0){ 250 aprint_error_dev(sc->sc_dev, "couldn't create DMA map - error %d\n", error); 251 return; 252 } 253 254 /* 255 * Integrated ESDI controller supports only one disk, other 256 * controllers support two disks. 257 */ 258 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 259 sc->sc_maxdevs = 1; 260 else 261 sc->sc_maxdevs = 2; 262 263 /* 264 * Reset controller and attach individual disks. ed attach routine 265 * uses polling so that this works with interrupts disabled. 266 */ 267 268 /* Do a reset to ensure sane state after warm boot. */ 269 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 270 /* hard reset */ 271 printf("%s: controller busy, performing hardware reset ...\n", 272 device_xname(sc->sc_dev)); 273 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 274 BCR_INT_ENABLE|BCR_RESET); 275 } else { 276 /* "SOFT" reset */ 277 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 278 } 279 280 /* 281 * Since interrupts are disabled, it's necessary 282 * to detect the interrupt request and call edc_intr() 283 * explicitly. See also edc_run_cmd(). 284 */ 285 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 286 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 287 edc_intr(sc); 288 289 delay(100); 290 } 291 292 /* be quiet during probes */ 293 sc->sc_flags |= DASD_QUIET; 294 295 /* check for attached disks */ 296 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 297 eda.edc_drive = devno; 298 locs[EDCCF_DRIVE] = devno; 299 300 sc->sc_ed[devno] = device_private( 301 config_found_sm_loc(self, "edc", locs, &eda, NULL, 302 config_stdsubmatch)); 303 304 /* If initialization did not succeed, NULL the pointer. */ 305 if (sc->sc_ed[devno] 306 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 307 sc->sc_ed[devno] = NULL; 308 } 309 310 /* enable full error dumps again */ 311 sc->sc_flags &= ~DASD_QUIET; 312 313 /* 314 * Check if there are any disks attached. If not, disestablish 315 * the interrupt. 316 */ 317 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 318 if (sc->sc_ed[devno]) 319 break; 320 } 321 322 if (devno == sc->sc_maxdevs) { 323 printf("%s: disabling controller (no drives attached)\n", 324 device_xname(sc->sc_dev)); 325 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 326 return; 327 } 328 329 /* 330 * Run the worker thread. 331 */ 332 config_pending_incr(self); 333 if ((error = kthread_create(PRI_NONE, 0, NULL, edcworker, sc, NULL, 334 "%s", device_xname(sc->sc_dev)))) { 335 aprint_error_dev(sc->sc_dev, "cannot spawn worker thread: errno=%d\n", error); 336 panic("edc_mca_attach"); 337 } 338 } 339 340 void 341 edc_add_disk(struct edc_mca_softc *sc, struct ed_softc *ed) 342 { 343 sc->sc_ed[ed->sc_devno] = ed; 344 } 345 346 static int 347 edc_intr(void *arg) 348 { 349 struct edc_mca_softc *sc = arg; 350 u_int8_t isr, intr_id; 351 u_int16_t sifr; 352 int cmd=-1, devno; 353 354 /* 355 * Check if the interrupt was for us. 356 */ 357 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 358 return (0); 359 360 /* 361 * Read ISR to find out interrupt type. This also clears the interrupt 362 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 363 * and 4 are reserved and not used. 364 */ 365 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 366 intr_id = isr & ISR_INTR_ID_MASK; 367 368 #ifdef EDC_DEBUG 369 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 370 aprint_error_dev(sc->sc_dev, "bogus interrupt id %d\n", 371 (int) intr_id); 372 return (0); 373 } 374 #endif 375 376 /* Get number of device whose intr this was */ 377 devno = (isr & 0xe0) >> 5; 378 379 /* 380 * Get Status block. Higher byte always says how long the status 381 * block is, rest is device number and command code. 382 * Check the status block length against our supported maximum length 383 * and fetch the data. 384 */ 385 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 386 size_t len; 387 int i; 388 389 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 390 len = (sifr & 0xff00) >> 8; 391 #ifdef DEBUG 392 if (len > EDC_MAX_CMD_RES_LEN) 393 panic("%s: maximum Status Length exceeded: %d > %d", 394 device_xname(sc->sc_dev), 395 len, EDC_MAX_CMD_RES_LEN); 396 #endif 397 398 /* Get command code */ 399 cmd = sifr & SIFR_CMD_MASK; 400 401 /* Read whole status block */ 402 sc->status_block[0] = sifr; 403 for(i=1; i < len; i++) { 404 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 405 & BSR_SIFR_FULL) == 0) 406 ; 407 408 sc->status_block[i] = le16toh( 409 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 410 } 411 /* zero out rest */ 412 if (i < EDC_MAX_CMD_RES_LEN) { 413 memset(&sc->status_block[i], 0, 414 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 415 } 416 } 417 418 switch (intr_id) { 419 case ISR_DATA_TRANSFER_RDY: 420 /* 421 * Ready to do DMA. The DMA controller has already been 422 * setup, now just kick disk controller to do the transfer. 423 */ 424 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 425 BCR_INT_ENABLE|BCR_DMA_ENABLE); 426 break; 427 428 case ISR_COMPLETED: 429 case ISR_COMPLETED_WITH_ECC: 430 case ISR_COMPLETED_RETRIES: 431 case ISR_COMPLETED_WARNING: 432 /* 433 * Copy device config data if appropriate. sc->sc_ed[] 434 * entry might be NULL during probe. 435 */ 436 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 437 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 438 sizeof(sc->sc_ed[devno]->sense_data)); 439 } 440 441 sc->sc_stat = STAT_DONE; 442 break; 443 444 case ISR_RESET_COMPLETED: 445 case ISR_ABORT_COMPLETED: 446 /* nothing to do */ 447 break; 448 449 case ISR_ATTN_ERROR: 450 /* 451 * Basically, this means driver bug or something seriously 452 * hosed. panic rather than extending the lossage. 453 * No status block available, so no further info. 454 */ 455 panic("%s: dev %d: attention error", 456 device_xname(sc->sc_dev), 457 devno); 458 /* NOTREACHED */ 459 break; 460 461 default: 462 if ((sc->sc_flags & DASD_QUIET) == 0) 463 edc_dump_status_block(sc, sc->status_block, intr_id); 464 465 sc->sc_stat = STAT_ERROR; 466 break; 467 } 468 469 /* 470 * Unless the interrupt is for Data Transfer Ready or 471 * Attention Error, finish by assertion EOI. This makes 472 * attachment aware the interrupt is processed and system 473 * is ready to accept another one. 474 */ 475 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 476 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 477 478 /* If Read or Write Data, wakeup worker thread to finish it */ 479 if (intr_id != ISR_DATA_TRANSFER_RDY) { 480 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 481 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 482 wakeup(sc); 483 } 484 485 return (1); 486 } 487 488 /* 489 * This follows the exact order for Attention Request as 490 * written in DASD Storage Interface Specification MC (Rev 2.2). 491 */ 492 static int 493 edc_do_attn(struct edc_mca_softc *sc, int attn_type, int devno, int intr_id) 494 { 495 int tries; 496 497 /* 1. Disable interrupts in BCR. */ 498 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 499 500 /* 501 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 502 * a RESET COMPLETED interrupt. 503 */ 504 if (intr_id != ISR_RESET_COMPLETED) { 505 #ifdef EDC_DEBUG 506 if (attn_type == ATN_CMD_REQ 507 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 508 & BSR_INT_PENDING)) 509 panic("%s: edc int pending", device_xname(sc->sc_dev)); 510 #endif 511 512 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 513 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 514 & BSR_BUSY) == 0) 515 break; 516 } 517 518 if (tries == EDC_ATTN_MAXTRIES) { 519 printf("%s: edc_do_attn: timeout waiting for attachment to become available\n", 520 device_xname(sc->sc_ed[devno]->sc_dev)); 521 return (EIO); 522 } 523 } 524 525 /* 526 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 527 */ 528 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 529 530 /* 531 * 4. Enable interrupts via BCR. 532 */ 533 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 534 535 return (0); 536 } 537 538 /* 539 * Wait until command is processed, timeout after 'secs' seconds. 540 * We use mono_time, since we don't need actual RTC, just time 541 * interval. 542 */ 543 static void 544 edc_cmd_wait(struct edc_mca_softc *sc, int secs, int poll) 545 { 546 int val; 547 548 if (!poll) { 549 int s; 550 551 /* Not polling, can sleep. Sleep until we are awakened, 552 * but maximum secs seconds. 553 */ 554 s = splbio(); 555 if (sc->sc_stat != STAT_DONE) 556 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 557 splx(s); 558 } 559 560 /* Wait until the command is completely finished */ 561 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 562 & BSR_CMD_INPROGRESS) { 563 if (poll && (val & BSR_INTR)) 564 edc_intr(sc); 565 } 566 } 567 568 /* 569 * Command controller to execute specified command on a device. 570 */ 571 int 572 edc_run_cmd(struct edc_mca_softc *sc, int cmd, int devno, 573 u_int16_t cmd_args[], int cmd_len, int poll) 574 { 575 int i, error, tries; 576 u_int16_t cmd0; 577 578 sc->sc_stat = STAT_START; 579 580 /* Do Attention Request for Command Request. */ 581 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 582 return (error); 583 584 /* 585 * Construct the command. The bits are like this: 586 * 587 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 588 * \_/ 0 0 1 0 \__/ \_____/ 589 * \ \__________/ \ \_ Command Code (see CMD_*) 590 * \ \ \__ Device: 0 common, 7 controller 591 * \ \__ Options: reserved, bit 10=cache bypass bit 592 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 593 * 594 * We always use device 0 or 1, so difference is made only by Command 595 * Code, Command Options and command length. 596 */ 597 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 598 | (devno << 5) 599 | (cmd_args[0] << 8) | cmd; 600 cmd_args[0] = cmd0; 601 602 /* 603 * Write word of CMD to the CIFR. This sets "Command 604 * Interface Register Full (CMD IN)" in BSR. Once the attachment 605 * detects it, it reads the word and clears CMD IN. This all should 606 * be quite fast, so don't sleep in !poll case neither. 607 */ 608 for(i=0; i < cmd_len; i++) { 609 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 610 htole16(cmd_args[i])); 611 612 /* Wait until CMD IN is cleared. */ 613 tries = 0; 614 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 615 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 616 delay(poll ? 1000 : 1); 617 ; 618 619 if (tries == 10000 620 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 621 & BSR_CIFR_FULL) { 622 aprint_error_dev(sc->sc_dev, "device too slow to accept command %d\n", cmd); 623 return (EIO); 624 } 625 } 626 627 /* Wait for command to complete, but maximum 15 seconds. */ 628 edc_cmd_wait(sc, 15, poll); 629 630 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 631 } 632 633 #ifdef EDC_DEBUG 634 static const char * const edc_commands[] = { 635 "Invalid Command", 636 "Read Data", 637 "Write Data", 638 "Read Verify", 639 "Write with Verify", 640 "Seek", 641 "Park Head", 642 "Get Command Complete Status", 643 "Get Device Status", 644 "Get Device Configuration", 645 "Get POS Information", 646 "Translate RBA", 647 "Write Attachment Buffer", 648 "Read Attachment Buffer", 649 "Run Diagnostic Test", 650 "Get Diagnostic Status Block", 651 "Get MFG Header", 652 "Format Unit", 653 "Format Prepare", 654 "Set MAX RBA", 655 "Set Power Saving Mode", 656 "Power Conservation Command", 657 }; 658 659 static const char * const edc_cmd_status[256] = { 660 "Reserved", 661 "Command completed successfully", 662 "Reserved", 663 "Command completed successfully with ECC applied", 664 "Reserved", 665 "Command completed successfully with retries", 666 "Format Command partially completed", /* Status available */ 667 "Command completed successfully with ECC and retries", 668 "Command completed with Warning", /* Command Error is available */ 669 "Aborted", 670 "Reset completed", 671 "Data Transfer Ready", /* No Status Block available */ 672 "Command terminated with failure", /* Device Error is available */ 673 "DMA Error", /* Retry entire command as recovery */ 674 "Command Block Error", 675 "Attention Error (Illegal Attention Code)", 676 /* 0x14 - 0xff reserved */ 677 }; 678 679 static const char * const edc_cmd_error[256] = { 680 "No Error", 681 "Invalid parameter in the command block", 682 "Reserved", 683 "Command not supported", 684 "Command Aborted per request", 685 "Reserved", 686 "Command rejected", /* Attachment diagnostic failure */ 687 "Format Rejected", /* Prepare Format command is required */ 688 "Format Error (Primary Map is not readable)", 689 "Format Error (Secondary map is not readable)", 690 "Format Error (Diagnostic Failure)", 691 "Format Warning (Secondary Map Overflow)", 692 "Reserved" 693 "Format Error (Host Checksum Error)", 694 "Reserved", 695 "Format Warning (Push table overflow)", 696 "Format Warning (More pushes than allowed)", 697 "Reserved", 698 "Format Warning (Error during verifying)", 699 "Invalid device number for the command", 700 /* 0x14-0xff reserved */ 701 }; 702 703 static const char * const edc_dev_errors[] = { 704 "No Error", 705 "Seek Fault", /* Device report */ 706 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 707 "Block not found (ID not found)", 708 "Block not found (AM not found)", 709 "Data ECC Error (hard error)", 710 "ID CRC Error", 711 "RBA Out of Range", 712 "Reserved", 713 "Defective Block", 714 "Reserved", 715 "Selection Error", 716 "Reserved", 717 "Write Fault", 718 "No index or sector pulse", 719 "Device Not Ready", 720 "Seek Error", /* Attachment report */ 721 "Bad Format", 722 "Volume Overflow", 723 "No Data AM Found", 724 "Block not found (No ID AM or ID CRC error occurred)", 725 "Reserved", 726 "Reserved", 727 "No ID found on track (ID search)", 728 /* 0x19 - 0xff reserved */ 729 }; 730 #endif /* EDC_DEBUG */ 731 732 static void 733 edc_dump_status_block(struct edc_mca_softc *sc, u_int16_t *status_block, 734 int intr_id) 735 { 736 #ifdef EDC_DEBUG 737 printf("%s: Command: %s, Status: %s (intr %d)\n", 738 device_xname(sc->sc_dev), 739 edc_commands[status_block[0] & 0x1f], 740 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 741 intr_id 742 ); 743 #else 744 printf("%s: Command: %d, Status: %d (intr %d)\n", 745 device_xname(sc->sc_dev), 746 status_block[0] & 0x1f, 747 SB_GET_CMD_STATUS(status_block), 748 intr_id 749 ); 750 #endif 751 printf("%s: # left blocks: %u, last processed RBA: %u\n", 752 device_xname(sc->sc_dev), 753 status_block[SB_RESBLKCNT_IDX], 754 (status_block[5] << 16) | status_block[4]); 755 756 if (intr_id == ISR_COMPLETED_WARNING) { 757 #ifdef EDC_DEBUG 758 aprint_error_dev(sc->sc_dev, "Command Error Code: %s\n", 759 edc_cmd_error[status_block[1] & 0xff]); 760 #else 761 aprint_error_dev(sc->sc_dev, "Command Error Code: %d\n", 762 status_block[1] & 0xff); 763 #endif 764 } 765 766 if (intr_id == ISR_CMD_FAILED) { 767 #ifdef EDC_DEBUG 768 char buf[100]; 769 770 printf("%s: Device Error Code: %s\n", 771 device_xname(sc->sc_dev), 772 edc_dev_errors[status_block[2] & 0xff]); 773 snprintb(buf, sizeof(buf), 774 "\20" 775 "\01SeekOrCmdComplete" 776 "\02Track0Flag" 777 "\03WriteFault" 778 "\04Selected" 779 "\05Ready" 780 "\06Reserved0" 781 "\07STANDBY" 782 "\010Reserved0", (status_block[2] & 0xff00) >> 8); 783 784 printf("%s: Device Status: %s\n", 785 device_xname(sc->sc_dev), buf); 786 #else 787 printf("%s: Device Error Code: %d, Device Status: %d\n", 788 device_xname(sc->sc_dev), 789 status_block[2] & 0xff, 790 (status_block[2] & 0xff00) >> 8); 791 #endif 792 } 793 } 794 /* 795 * Main worker thread function. 796 */ 797 void 798 edcworker(void *arg) 799 { 800 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 801 struct ed_softc *ed; 802 struct buf *bp; 803 int i, error; 804 805 config_pending_decr(sc->sc_dev); 806 807 for(;;) { 808 /* Wait until awakened */ 809 (void) tsleep(sc, PRIBIO, "edcidle", 0); 810 811 for(i=0; i<sc->sc_maxdevs; ) { 812 if ((ed = sc->sc_ed[i]) == NULL) { 813 i++; 814 continue; 815 } 816 817 /* Is there a buf for us ? */ 818 mutex_enter(&ed->sc_q_lock); 819 if ((bp = bufq_get(ed->sc_q)) == NULL) { 820 mutex_exit(&ed->sc_q_lock); 821 i++; 822 continue; 823 } 824 mutex_exit(&ed->sc_q_lock); 825 826 /* Instrumentation. */ 827 disk_busy(&ed->sc_dk); 828 829 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 830 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 831 832 if (error) { 833 bp->b_error = error; 834 } else { 835 /* Set resid, most commonly to zero. */ 836 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 837 } 838 839 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 840 (bp->b_flags & B_READ)); 841 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 842 biodone(bp); 843 } 844 } 845 } 846 847 int 848 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 849 size_t bcount, daddr_t rawblkno, int isread, int poll) 850 { 851 u_int16_t cmd_args[4]; 852 int error=0, fl; 853 u_int16_t track; 854 u_int16_t cyl; 855 u_int8_t head; 856 u_int8_t sector; 857 858 mca_disk_busy(); 859 860 /* set WAIT and R/W flag appropriately for the DMA transfer */ 861 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 862 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 863 864 /* Load the buffer for DMA transfer. */ 865 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 866 bcount, NULL, BUS_DMA_STREAMING|fl))) { 867 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 868 device_xname(ed->sc_dev), error); 869 goto out; 870 } 871 872 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 873 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 874 875 track = rawblkno / ed->sectors; 876 head = track % ed->heads; 877 cyl = track / ed->heads; 878 sector = rawblkno % ed->sectors; 879 880 /* Read or Write Data command */ 881 cmd_args[0] = 2; /* Options 0000010 */ 882 cmd_args[1] = bcount / DEV_BSIZE; 883 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 884 cmd_args[3] = ((cyl & 0x3E0) >> 5); 885 error = edc_run_cmd(sc, 886 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 887 ed->sc_devno, cmd_args, 4, poll); 888 889 /* Sync the DMA memory */ 890 if (!error) { 891 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 892 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 893 } 894 895 /* We are done, unload buffer from DMA map */ 896 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 897 898 out: 899 mca_disk_unbusy(); 900 901 return (error); 902 } 903