1 /* $NetBSD: edc_mca.c,v 1.39 2008/04/08 20:41:00 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jaromir Dolecek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 38 * spec. 39 * 40 * The driver was written with DASD Storage Interface Specification 41 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>. 42 * 43 * TODO: 44 * - improve error recovery 45 * Issue soft reset on error or timeout? 46 * - test with > 1 disk (this is supported by some controllers) 47 * - test with > 1 ESDI controller in machine; shared interrupts 48 * necessary for this to work should be supported - edc_intr() specifically 49 * checks if the interrupt is for this controller 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.39 2008/04/08 20:41:00 cegger Exp $"); 54 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/buf.h> 60 #include <sys/bufq.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 #include <sys/malloc.h> 64 #include <sys/endian.h> 65 #include <sys/disklabel.h> 66 #include <sys/disk.h> 67 #include <sys/syslog.h> 68 #include <sys/proc.h> 69 #include <sys/vnode.h> 70 #include <sys/kernel.h> 71 #include <sys/kthread.h> 72 #if NRND > 0 73 #include <sys/rnd.h> 74 #endif 75 76 #include <sys/bus.h> 77 #include <sys/intr.h> 78 79 #include <dev/mca/mcareg.h> 80 #include <dev/mca/mcavar.h> 81 #include <dev/mca/mcadevs.h> 82 83 #include <dev/mca/edcreg.h> 84 #include <dev/mca/edvar.h> 85 #include <dev/mca/edcvar.h> 86 87 #include "locators.h" 88 89 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 90 #define EDC_MAX_CMD_RES_LEN 8 91 92 struct edc_mca_softc { 93 struct device sc_dev; 94 95 bus_space_tag_t sc_iot; 96 bus_space_handle_t sc_ioh; 97 98 /* DMA related stuff */ 99 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 100 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 101 102 void *sc_ih; /* interrupt handle */ 103 104 int sc_flags; 105 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 106 107 #define DASD_MAXDEVS 8 108 struct ed_softc *sc_ed[DASD_MAXDEVS]; 109 int sc_maxdevs; /* max number of disks attached to this 110 * controller */ 111 112 /* I/O results variables */ 113 volatile int sc_stat; 114 #define STAT_START 0 115 #define STAT_ERROR 1 116 #define STAT_DONE 2 117 volatile int sc_resblk; /* residual block count */ 118 119 /* CMD status block - only set & used in edc_intr() */ 120 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 121 }; 122 123 int edc_mca_probe(struct device *, struct cfdata *, void *); 124 void edc_mca_attach(struct device *, struct device *, void *); 125 126 CFATTACH_DECL(edc_mca, sizeof(struct edc_mca_softc), 127 edc_mca_probe, edc_mca_attach, NULL, NULL); 128 129 static int edc_intr(void *); 130 static void edc_dump_status_block(struct edc_mca_softc *, 131 u_int16_t *, int); 132 static int edc_do_attn(struct edc_mca_softc *, int, int, int); 133 static void edc_cmd_wait(struct edc_mca_softc *, int, int); 134 static void edcworker(void *); 135 136 int 137 edc_mca_probe(struct device *parent, struct cfdata *match, 138 void *aux) 139 { 140 struct mca_attach_args *ma = aux; 141 142 switch (ma->ma_id) { 143 case MCA_PRODUCT_IBM_ESDIC: 144 case MCA_PRODUCT_IBM_ESDIC_IG: 145 return (1); 146 default: 147 return (0); 148 } 149 } 150 151 void 152 edc_mca_attach(struct device *parent, struct device *self, void *aux) 153 { 154 struct edc_mca_softc *sc = device_private(self); 155 struct mca_attach_args *ma = aux; 156 struct ed_attach_args eda; 157 int pos2, pos3, pos4; 158 int irq, drq, iobase; 159 const char *typestr; 160 int devno, error; 161 int locs[EDCCF_NLOCS]; 162 163 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 164 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 165 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 166 167 /* 168 * POS register 2: (adf pos0) 169 * 170 * 7 6 5 4 3 2 1 0 171 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 172 * \ \ \___ Primary/Alternate Port Addresses: 173 * \ \ 0=0x3510-3517 1=0x3518-0x351f 174 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 175 * \ 0000=0 0001=1 0011=3 0100=4 176 * \_________ Fairness On/Off: 1=On 0=Off 177 * 178 * POS register 3: (adf pos1) 179 * 180 * 7 6 5 4 3 2 1 0 181 * 0 0 \_/ 182 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 183 * 01=16ms 00=Burst Disabled 184 * 185 * POS register 4: (adf pos2) 186 * 187 * 7 6 5 4 3 2 1 0 188 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 189 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 190 * 191 * IRQ is fixed to 14 (0x0e). 192 */ 193 194 switch (ma->ma_id) { 195 case MCA_PRODUCT_IBM_ESDIC: 196 typestr = "IBM ESDI Fixed Disk Controller"; 197 break; 198 case MCA_PRODUCT_IBM_ESDIC_IG: 199 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 200 break; 201 default: 202 typestr = NULL; 203 break; 204 } 205 206 irq = ESDIC_IRQ; 207 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 208 drq = (pos2 & DRQ_MASK) >> 2; 209 210 printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 211 irq, drq, typestr); 212 213 #ifdef DIAGNOSTIC 214 /* 215 * It's not strictly necessary to check this, machine configuration 216 * utility uses only valid addresses. 217 */ 218 if (drq == 2 || drq >= 8) { 219 aprint_error_dev(&sc->sc_dev, "invalid DMA Arbitration Level %d\n", drq); 220 return; 221 } 222 #endif 223 224 printf("%s: Fairness %s, Release %s, ", 225 device_xname(&sc->sc_dev), 226 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 227 (pos4 & RELEASE_1) ? "6ms" 228 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 229 ); 230 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 231 static const char * const pacint[] = 232 { "disabled", "16ms", "24ms", "31ms"}; 233 printf("DMA burst pacing interval %s\n", 234 pacint[(pos3 & PACING_INT_MASK) >> 4]); 235 } else 236 printf("DMA pacing control disabled\n"); 237 238 sc->sc_iot = ma->ma_iot; 239 240 if (bus_space_map(sc->sc_iot, iobase, 241 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 242 aprint_error_dev(&sc->sc_dev, "couldn't map registers\n"); 243 return; 244 } 245 246 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 247 if (sc->sc_ih == NULL) { 248 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt handler\n"); 249 return; 250 } 251 252 /* Create a MCA DMA map, used for data transfer */ 253 sc->sc_dmat = ma->ma_dmat; 254 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 255 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 256 &sc->sc_dmamap_xfer, drq)) != 0){ 257 aprint_error_dev(&sc->sc_dev, "couldn't create DMA map - error %d\n", error); 258 return; 259 } 260 261 /* 262 * Integrated ESDI controller supports only one disk, other 263 * controllers support two disks. 264 */ 265 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 266 sc->sc_maxdevs = 1; 267 else 268 sc->sc_maxdevs = 2; 269 270 /* 271 * Reset controller and attach individual disks. ed attach routine 272 * uses polling so that this works with interrupts disabled. 273 */ 274 275 /* Do a reset to ensure sane state after warm boot. */ 276 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 277 /* hard reset */ 278 printf("%s: controller busy, performing hardware reset ...\n", 279 device_xname(&sc->sc_dev)); 280 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 281 BCR_INT_ENABLE|BCR_RESET); 282 } else { 283 /* "SOFT" reset */ 284 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 285 } 286 287 /* 288 * Since interrupts are disabled, it's necessary 289 * to detect the interrupt request and call edc_intr() 290 * explicitly. See also edc_run_cmd(). 291 */ 292 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 293 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 294 edc_intr(sc); 295 296 delay(100); 297 } 298 299 /* be quiet during probes */ 300 sc->sc_flags |= DASD_QUIET; 301 302 /* check for attached disks */ 303 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 304 eda.edc_drive = devno; 305 locs[EDCCF_DRIVE] = devno; 306 sc->sc_ed[devno] = 307 (void *) config_found_sm_loc(self, "edc", locs, &eda, 308 NULL, config_stdsubmatch); 309 310 /* If initialization did not succeed, NULL the pointer. */ 311 if (sc->sc_ed[devno] 312 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 313 sc->sc_ed[devno] = NULL; 314 } 315 316 /* enable full error dumps again */ 317 sc->sc_flags &= ~DASD_QUIET; 318 319 /* 320 * Check if there are any disks attached. If not, disestablish 321 * the interrupt. 322 */ 323 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 324 if (sc->sc_ed[devno]) 325 break; 326 } 327 328 if (devno == sc->sc_maxdevs) { 329 printf("%s: disabling controller (no drives attached)\n", 330 device_xname(&sc->sc_dev)); 331 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 332 return; 333 } 334 335 /* 336 * Run the worker thread. 337 */ 338 config_pending_incr(); 339 if ((error = kthread_create(PRI_NONE, 0, NULL, edcworker, sc, NULL, 340 "%s", device_xname(&sc->sc_dev)))) { 341 aprint_error_dev(&sc->sc_dev, "cannot spawn worker thread: errno=%d\n", error); 342 panic("edc_mca_attach"); 343 } 344 } 345 346 void 347 edc_add_disk(struct edc_mca_softc *sc, struct ed_softc *ed) 348 { 349 sc->sc_ed[ed->sc_devno] = ed; 350 } 351 352 static int 353 edc_intr(void *arg) 354 { 355 struct edc_mca_softc *sc = arg; 356 u_int8_t isr, intr_id; 357 u_int16_t sifr; 358 int cmd=-1, devno; 359 360 /* 361 * Check if the interrupt was for us. 362 */ 363 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 364 return (0); 365 366 /* 367 * Read ISR to find out interrupt type. This also clears the interrupt 368 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 369 * and 4 are reserved and not used. 370 */ 371 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 372 intr_id = isr & ISR_INTR_ID_MASK; 373 374 #ifdef EDC_DEBUG 375 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 376 aprint_error_dev(&sc->sc_dev, "bogus interrupt id %d\n", 377 (int) intr_id); 378 return (0); 379 } 380 #endif 381 382 /* Get number of device whose intr this was */ 383 devno = (isr & 0xe0) >> 5; 384 385 /* 386 * Get Status block. Higher byte always says how long the status 387 * block is, rest is device number and command code. 388 * Check the status block length against our supported maximum length 389 * and fetch the data. 390 */ 391 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 392 size_t len; 393 int i; 394 395 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 396 len = (sifr & 0xff00) >> 8; 397 #ifdef DEBUG 398 if (len > EDC_MAX_CMD_RES_LEN) 399 panic("%s: maximum Status Length exceeded: %d > %d", 400 device_xname(&sc->sc_dev), 401 len, EDC_MAX_CMD_RES_LEN); 402 #endif 403 404 /* Get command code */ 405 cmd = sifr & SIFR_CMD_MASK; 406 407 /* Read whole status block */ 408 sc->status_block[0] = sifr; 409 for(i=1; i < len; i++) { 410 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 411 & BSR_SIFR_FULL) == 0) 412 ; 413 414 sc->status_block[i] = le16toh( 415 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 416 } 417 /* zero out rest */ 418 if (i < EDC_MAX_CMD_RES_LEN) { 419 memset(&sc->status_block[i], 0, 420 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 421 } 422 } 423 424 switch (intr_id) { 425 case ISR_DATA_TRANSFER_RDY: 426 /* 427 * Ready to do DMA. The DMA controller has already been 428 * setup, now just kick disk controller to do the transfer. 429 */ 430 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 431 BCR_INT_ENABLE|BCR_DMA_ENABLE); 432 break; 433 434 case ISR_COMPLETED: 435 case ISR_COMPLETED_WITH_ECC: 436 case ISR_COMPLETED_RETRIES: 437 case ISR_COMPLETED_WARNING: 438 /* 439 * Copy device config data if appropriate. sc->sc_ed[] 440 * entry might be NULL during probe. 441 */ 442 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 443 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 444 sizeof(sc->sc_ed[devno]->sense_data)); 445 } 446 447 sc->sc_stat = STAT_DONE; 448 break; 449 450 case ISR_RESET_COMPLETED: 451 case ISR_ABORT_COMPLETED: 452 /* nothing to do */ 453 break; 454 455 case ISR_ATTN_ERROR: 456 /* 457 * Basically, this means driver bug or something seriously 458 * hosed. panic rather than extending the lossage. 459 * No status block available, so no further info. 460 */ 461 panic("%s: dev %d: attention error", 462 device_xname(&sc->sc_dev), 463 devno); 464 /* NOTREACHED */ 465 break; 466 467 default: 468 if ((sc->sc_flags & DASD_QUIET) == 0) 469 edc_dump_status_block(sc, sc->status_block, intr_id); 470 471 sc->sc_stat = STAT_ERROR; 472 break; 473 } 474 475 /* 476 * Unless the interrupt is for Data Transfer Ready or 477 * Attention Error, finish by assertion EOI. This makes 478 * attachment aware the interrupt is processed and system 479 * is ready to accept another one. 480 */ 481 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 482 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 483 484 /* If Read or Write Data, wakeup worker thread to finish it */ 485 if (intr_id != ISR_DATA_TRANSFER_RDY) { 486 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 487 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 488 wakeup_one(sc); 489 } 490 491 return (1); 492 } 493 494 /* 495 * This follows the exact order for Attention Request as 496 * written in DASD Storage Interface Specification MC (Rev 2.2). 497 */ 498 static int 499 edc_do_attn(struct edc_mca_softc *sc, int attn_type, int devno, int intr_id) 500 { 501 int tries; 502 503 /* 1. Disable interrupts in BCR. */ 504 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 505 506 /* 507 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 508 * a RESET COMPLETED interrupt. 509 */ 510 if (intr_id != ISR_RESET_COMPLETED) { 511 #ifdef EDC_DEBUG 512 if (attn_type == ATN_CMD_REQ 513 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 514 & BSR_INT_PENDING)) 515 panic("%s: edc int pending", device_xname(&sc->sc_dev)); 516 #endif 517 518 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 519 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 520 & BSR_BUSY) == 0) 521 break; 522 } 523 524 if (tries == EDC_ATTN_MAXTRIES) { 525 printf("%s: edc_do_attn: timeout waiting for attachment to become available\n", 526 device_xname(&sc->sc_ed[devno]->sc_dev)); 527 return (EIO); 528 } 529 } 530 531 /* 532 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 533 */ 534 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 535 536 /* 537 * 4. Enable interrupts via BCR. 538 */ 539 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 540 541 return (0); 542 } 543 544 /* 545 * Wait until command is processed, timeout after 'secs' seconds. 546 * We use mono_time, since we don't need actual RTC, just time 547 * interval. 548 */ 549 static void 550 edc_cmd_wait(struct edc_mca_softc *sc, int secs, int poll) 551 { 552 int val; 553 554 if (!poll) { 555 int s; 556 557 /* Not polling, can sleep. Sleep until we are awakened, 558 * but maximum secs seconds. 559 */ 560 s = splbio(); 561 if (sc->sc_stat != STAT_DONE) 562 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 563 splx(s); 564 } 565 566 /* Wait until the command is completely finished */ 567 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 568 & BSR_CMD_INPROGRESS) { 569 if (poll && (val & BSR_INTR)) 570 edc_intr(sc); 571 } 572 } 573 574 /* 575 * Command controller to execute specified command on a device. 576 */ 577 int 578 edc_run_cmd(struct edc_mca_softc *sc, int cmd, int devno, 579 u_int16_t cmd_args[], int cmd_len, int poll) 580 { 581 int i, error, tries; 582 u_int16_t cmd0; 583 584 sc->sc_stat = STAT_START; 585 586 /* Do Attention Request for Command Request. */ 587 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 588 return (error); 589 590 /* 591 * Construct the command. The bits are like this: 592 * 593 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 594 * \_/ 0 0 1 0 \__/ \_____/ 595 * \ \__________/ \ \_ Command Code (see CMD_*) 596 * \ \ \__ Device: 0 common, 7 controller 597 * \ \__ Options: reserved, bit 10=cache bypass bit 598 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 599 * 600 * We always use device 0 or 1, so difference is made only by Command 601 * Code, Command Options and command length. 602 */ 603 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 604 | (devno << 5) 605 | (cmd_args[0] << 8) | cmd; 606 cmd_args[0] = cmd0; 607 608 /* 609 * Write word of CMD to the CIFR. This sets "Command 610 * Interface Register Full (CMD IN)" in BSR. Once the attachment 611 * detects it, it reads the word and clears CMD IN. This all should 612 * be quite fast, so don't sleep in !poll case neither. 613 */ 614 for(i=0; i < cmd_len; i++) { 615 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 616 htole16(cmd_args[i])); 617 618 /* Wait until CMD IN is cleared. */ 619 tries = 0; 620 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 621 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 622 delay(poll ? 1000 : 1); 623 ; 624 625 if (tries == 10000 626 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 627 & BSR_CIFR_FULL) { 628 aprint_error_dev(&sc->sc_dev, "device too slow to accept command %d\n", cmd); 629 return (EIO); 630 } 631 } 632 633 /* Wait for command to complete, but maximum 15 seconds. */ 634 edc_cmd_wait(sc, 15, poll); 635 636 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 637 } 638 639 #ifdef EDC_DEBUG 640 static const char * const edc_commands[] = { 641 "Invalid Command", 642 "Read Data", 643 "Write Data", 644 "Read Verify", 645 "Write with Verify", 646 "Seek", 647 "Park Head", 648 "Get Command Complete Status", 649 "Get Device Status", 650 "Get Device Configuration", 651 "Get POS Information", 652 "Translate RBA", 653 "Write Attachment Buffer", 654 "Read Attachment Buffer", 655 "Run Diagnostic Test", 656 "Get Diagnostic Status Block", 657 "Get MFG Header", 658 "Format Unit", 659 "Format Prepare", 660 "Set MAX RBA", 661 "Set Power Saving Mode", 662 "Power Conservation Command", 663 }; 664 665 static const char * const edc_cmd_status[256] = { 666 "Reserved", 667 "Command completed successfully", 668 "Reserved", 669 "Command completed successfully with ECC applied", 670 "Reserved", 671 "Command completed successfully with retries", 672 "Format Command partially completed", /* Status available */ 673 "Command completed successfully with ECC and retries", 674 "Command completed with Warning", /* Command Error is available */ 675 "Aborted", 676 "Reset completed", 677 "Data Transfer Ready", /* No Status Block available */ 678 "Command terminated with failure", /* Device Error is available */ 679 "DMA Error", /* Retry entire command as recovery */ 680 "Command Block Error", 681 "Attention Error (Illegal Attention Code)", 682 /* 0x14 - 0xff reserved */ 683 }; 684 685 static const char * const edc_cmd_error[256] = { 686 "No Error", 687 "Invalid parameter in the command block", 688 "Reserved", 689 "Command not supported", 690 "Command Aborted per request", 691 "Reserved", 692 "Command rejected", /* Attachment diagnostic failure */ 693 "Format Rejected", /* Prepare Format command is required */ 694 "Format Error (Primary Map is not readable)", 695 "Format Error (Secondary map is not readable)", 696 "Format Error (Diagnostic Failure)", 697 "Format Warning (Secondary Map Overflow)", 698 "Reserved" 699 "Format Error (Host Checksum Error)", 700 "Reserved", 701 "Format Warning (Push table overflow)", 702 "Format Warning (More pushes than allowed)", 703 "Reserved", 704 "Format Warning (Error during verifying)", 705 "Invalid device number for the command", 706 /* 0x14-0xff reserved */ 707 }; 708 709 static const char * const edc_dev_errors[] = { 710 "No Error", 711 "Seek Fault", /* Device report */ 712 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 713 "Block not found (ID not found)", 714 "Block not found (AM not found)", 715 "Data ECC Error (hard error)", 716 "ID CRC Error", 717 "RBA Out of Range", 718 "Reserved", 719 "Defective Block", 720 "Reserved", 721 "Selection Error", 722 "Reserved", 723 "Write Fault", 724 "No index or sector pulse", 725 "Device Not Ready", 726 "Seek Error", /* Attachment report */ 727 "Bad Format", 728 "Volume Overflow", 729 "No Data AM Found", 730 "Block not found (No ID AM or ID CRC error occurred)", 731 "Reserved", 732 "Reserved", 733 "No ID found on track (ID search)", 734 /* 0x19 - 0xff reserved */ 735 }; 736 #endif /* EDC_DEBUG */ 737 738 static void 739 edc_dump_status_block(struct edc_mca_softc *sc, u_int16_t *status_block, 740 int intr_id) 741 { 742 #ifdef EDC_DEBUG 743 printf("%s: Command: %s, Status: %s (intr %d)\n", 744 device_xname(&sc->sc_dev), 745 edc_commands[status_block[0] & 0x1f], 746 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 747 intr_id 748 ); 749 #else 750 printf("%s: Command: %d, Status: %d (intr %d)\n", 751 device_xname(&sc->sc_dev), 752 status_block[0] & 0x1f, 753 SB_GET_CMD_STATUS(status_block), 754 intr_id 755 ); 756 #endif 757 printf("%s: # left blocks: %u, last processed RBA: %u\n", 758 device_xname(&sc->sc_dev), 759 status_block[SB_RESBLKCNT_IDX], 760 (status_block[5] << 16) | status_block[4]); 761 762 if (intr_id == ISR_COMPLETED_WARNING) { 763 #ifdef EDC_DEBUG 764 aprint_error_dev(&sc->sc_dev, "Command Error Code: %s\n", 765 edc_cmd_error[status_block[1] & 0xff]); 766 #else 767 aprint_error_dev(&sc->sc_dev, "Command Error Code: %d\n", 768 status_block[1] & 0xff); 769 #endif 770 } 771 772 if (intr_id == ISR_CMD_FAILED) { 773 #ifdef EDC_DEBUG 774 char buf[100]; 775 776 printf("%s: Device Error Code: %s\n", 777 device_xname(&sc->sc_dev), 778 edc_dev_errors[status_block[2] & 0xff]); 779 bitmask_snprintf((status_block[2] & 0xff00) >> 8, 780 "\20" 781 "\01SeekOrCmdComplete" 782 "\02Track0Flag" 783 "\03WriteFault" 784 "\04Selected" 785 "\05Ready" 786 "\06Reserved0" 787 "\07STANDBY" 788 "\010Reserved0", 789 buf, sizeof(buf)); 790 printf("%s: Device Status: %s\n", 791 device_xname(&sc->sc_dev), buf); 792 #else 793 printf("%s: Device Error Code: %d, Device Status: %d\n", 794 device_xname(&sc->sc_dev), 795 status_block[2] & 0xff, 796 (status_block[2] & 0xff00) >> 8); 797 #endif 798 } 799 } 800 /* 801 * Main worker thread function. 802 */ 803 void 804 edcworker(void *arg) 805 { 806 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 807 struct ed_softc *ed; 808 struct buf *bp; 809 int i, error; 810 811 config_pending_decr(); 812 813 for(;;) { 814 /* Wait until awakened */ 815 (void) tsleep(sc, PRIBIO, "edcidle", 0); 816 817 for(i=0; i<sc->sc_maxdevs; ) { 818 if ((ed = sc->sc_ed[i]) == NULL) { 819 i++; 820 continue; 821 } 822 823 /* Is there a buf for us ? */ 824 simple_lock(&ed->sc_q_lock); 825 if ((bp = BUFQ_GET(ed->sc_q)) == NULL) { 826 simple_unlock(&ed->sc_q_lock); 827 i++; 828 continue; 829 } 830 simple_unlock(&ed->sc_q_lock); 831 832 /* Instrumentation. */ 833 disk_busy(&ed->sc_dk); 834 835 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 836 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 837 838 if (error) { 839 bp->b_error = error; 840 } else { 841 /* Set resid, most commonly to zero. */ 842 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 843 } 844 845 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 846 (bp->b_flags & B_READ)); 847 #if NRND > 0 848 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 849 #endif 850 biodone(bp); 851 } 852 } 853 } 854 855 int 856 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 857 size_t bcount, daddr_t rawblkno, int isread, int poll) 858 { 859 u_int16_t cmd_args[4]; 860 int error=0, fl; 861 u_int16_t track; 862 u_int16_t cyl; 863 u_int8_t head; 864 u_int8_t sector; 865 866 mca_disk_busy(); 867 868 /* set WAIT and R/W flag appropriately for the DMA transfer */ 869 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 870 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 871 872 /* Load the buffer for DMA transfer. */ 873 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 874 bcount, NULL, BUS_DMA_STREAMING|fl))) { 875 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 876 device_xname(&ed->sc_dev), error); 877 goto out; 878 } 879 880 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 881 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 882 883 track = rawblkno / ed->sectors; 884 head = track % ed->heads; 885 cyl = track / ed->heads; 886 sector = rawblkno % ed->sectors; 887 888 /* Read or Write Data command */ 889 cmd_args[0] = 2; /* Options 0000010 */ 890 cmd_args[1] = bcount / DEV_BSIZE; 891 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 892 cmd_args[3] = ((cyl & 0x3E0) >> 5); 893 error = edc_run_cmd(sc, 894 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 895 ed->sc_devno, cmd_args, 4, poll); 896 897 /* Sync the DMA memory */ 898 if (!error) { 899 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 900 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 901 } 902 903 /* We are done, unload buffer from DMA map */ 904 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 905 906 out: 907 mca_disk_unbusy(); 908 909 return (error); 910 } 911