1 /* $NetBSD: edc_mca.c,v 1.53 2021/04/24 23:36:56 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jaromir Dolecek. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 34 * spec. 35 * 36 * The driver was written with DASD Storage Interface Specification 37 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>. 38 * 39 * TODO: 40 * - improve error recovery 41 * Issue soft reset on error or timeout? 42 * - test with > 1 disk (this is supported by some controllers) 43 * - test with > 1 ESDI controller in machine; shared interrupts 44 * necessary for this to work should be supported - edc_intr() specifically 45 * checks if the interrupt is for this controller 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.53 2021/04/24 23:36:56 thorpej Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/buf.h> 54 #include <sys/bufq.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/endian.h> 59 #include <sys/disklabel.h> 60 #include <sys/disk.h> 61 #include <sys/syslog.h> 62 #include <sys/proc.h> 63 #include <sys/vnode.h> 64 #include <sys/kernel.h> 65 #include <sys/kthread.h> 66 #include <sys/rndsource.h> 67 68 #include <sys/bus.h> 69 #include <sys/intr.h> 70 71 #include <dev/mca/mcareg.h> 72 #include <dev/mca/mcavar.h> 73 #include <dev/mca/mcadevs.h> 74 75 #include <dev/mca/edcreg.h> 76 #include <dev/mca/edvar.h> 77 #include <dev/mca/edcvar.h> 78 79 #include "locators.h" 80 81 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 82 #define EDC_MAX_CMD_RES_LEN 8 83 84 struct edc_mca_softc { 85 device_t sc_dev; 86 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 90 /* DMA related stuff */ 91 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 92 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 93 94 void *sc_ih; /* interrupt handle */ 95 96 int sc_flags; 97 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 98 99 #define DASD_MAXDEVS 8 100 struct ed_softc *sc_ed[DASD_MAXDEVS]; 101 int sc_maxdevs; /* max number of disks attached to this 102 * controller */ 103 104 /* I/O results variables */ 105 volatile int sc_stat; 106 #define STAT_START 0 107 #define STAT_ERROR 1 108 #define STAT_DONE 2 109 volatile int sc_resblk; /* residual block count */ 110 111 /* CMD status block - only set & used in edc_intr() */ 112 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 113 }; 114 115 int edc_mca_probe(device_t, cfdata_t, void *); 116 void edc_mca_attach(device_t, device_t, void *); 117 118 CFATTACH_DECL_NEW(edc_mca, sizeof(struct edc_mca_softc), 119 edc_mca_probe, edc_mca_attach, NULL, NULL); 120 121 static int edc_intr(void *); 122 static void edc_dump_status_block(struct edc_mca_softc *, 123 u_int16_t *, int); 124 static int edc_do_attn(struct edc_mca_softc *, int, int, int); 125 static void edc_cmd_wait(struct edc_mca_softc *, int, int); 126 static void edcworker(void *); 127 128 int 129 edc_mca_probe(device_t parent, cfdata_t match, void *aux) 130 { 131 struct mca_attach_args *ma = aux; 132 133 switch (ma->ma_id) { 134 case MCA_PRODUCT_IBM_ESDIC: 135 case MCA_PRODUCT_IBM_ESDIC_IG: 136 return (1); 137 default: 138 return (0); 139 } 140 } 141 142 void 143 edc_mca_attach(device_t parent, device_t self, void *aux) 144 { 145 struct edc_mca_softc *sc = device_private(self); 146 struct mca_attach_args *ma = aux; 147 struct ed_attach_args eda; 148 int pos2, pos3, pos4; 149 int irq, drq, iobase; 150 const char *typestr; 151 int devno, error; 152 int locs[EDCCF_NLOCS]; 153 154 sc->sc_dev = self; 155 156 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 157 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 158 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 159 160 /* 161 * POS register 2: (adf pos0) 162 * 163 * 7 6 5 4 3 2 1 0 164 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 165 * \ \ \___ Primary/Alternate Port Addresses: 166 * \ \ 0=0x3510-3517 1=0x3518-0x351f 167 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 168 * \ 0000=0 0001=1 0011=3 0100=4 169 * \_________ Fairness On/Off: 1=On 0=Off 170 * 171 * POS register 3: (adf pos1) 172 * 173 * 7 6 5 4 3 2 1 0 174 * 0 0 \_/ 175 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 176 * 01=16ms 00=Burst Disabled 177 * 178 * POS register 4: (adf pos2) 179 * 180 * 7 6 5 4 3 2 1 0 181 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 182 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 183 * 184 * IRQ is fixed to 14 (0x0e). 185 */ 186 187 switch (ma->ma_id) { 188 case MCA_PRODUCT_IBM_ESDIC: 189 typestr = "IBM ESDI Fixed Disk Controller"; 190 break; 191 case MCA_PRODUCT_IBM_ESDIC_IG: 192 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 193 break; 194 default: 195 typestr = NULL; 196 break; 197 } 198 199 irq = ESDIC_IRQ; 200 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 201 drq = (pos2 & DRQ_MASK) >> 2; 202 203 aprint_naive("\n"); 204 aprint_normal(": slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 205 irq, drq, typestr); 206 207 #ifdef DIAGNOSTIC 208 /* 209 * It's not strictly necessary to check this, machine configuration 210 * utility uses only valid addresses. 211 */ 212 if (drq == 2 || drq >= 8) { 213 aprint_error_dev(sc->sc_dev, 214 "invalid DMA Arbitration Level %d\n", drq); 215 return; 216 } 217 #endif 218 219 aprint_normal_dev(self, "Fairness %s, Release %s, ", 220 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 221 (pos4 & RELEASE_1) ? "6ms" 222 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 223 ); 224 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 225 static const char * const pacint[] = 226 { "disabled", "16ms", "24ms", "31ms"}; 227 aprint_normal("DMA burst pacing interval %s\n", 228 pacint[(pos3 & PACING_INT_MASK) >> 4]); 229 } else 230 aprint_normal("DMA pacing control disabled\n"); 231 232 sc->sc_iot = ma->ma_iot; 233 234 if (bus_space_map(sc->sc_iot, iobase, 235 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 236 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 237 return; 238 } 239 240 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 241 if (sc->sc_ih == NULL) { 242 aprint_error_dev(sc->sc_dev, 243 "couldn't establish interrupt handler\n"); 244 return; 245 } 246 247 /* Create a MCA DMA map, used for data transfer */ 248 sc->sc_dmat = ma->ma_dmat; 249 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 250 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 251 &sc->sc_dmamap_xfer, drq)) != 0){ 252 aprint_error_dev(sc->sc_dev, 253 "couldn't create DMA map - error %d\n", error); 254 return; 255 } 256 257 /* 258 * Integrated ESDI controller supports only one disk, other 259 * controllers support two disks. 260 */ 261 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 262 sc->sc_maxdevs = 1; 263 else 264 sc->sc_maxdevs = 2; 265 266 /* 267 * Reset controller and attach individual disks. ed attach routine 268 * uses polling so that this works with interrupts disabled. 269 */ 270 271 /* Do a reset to ensure sane state after warm boot. */ 272 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 273 /* hard reset */ 274 aprint_normal_dev(self, "controller busy, " 275 "performing hardware reset ...\n"); 276 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 277 BCR_INT_ENABLE|BCR_RESET); 278 } else { 279 /* "SOFT" reset */ 280 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 281 } 282 283 /* 284 * Since interrupts are disabled, it's necessary 285 * to detect the interrupt request and call edc_intr() 286 * explicitly. See also edc_run_cmd(). 287 */ 288 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 289 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 290 edc_intr(sc); 291 292 delay(100); 293 } 294 295 /* be quiet during probes */ 296 sc->sc_flags |= DASD_QUIET; 297 298 /* check for attached disks */ 299 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 300 eda.edc_drive = devno; 301 locs[EDCCF_DRIVE] = devno; 302 303 sc->sc_ed[devno] = device_private( 304 config_found(self, &eda, NULL, 305 CFARG_SUBMATCH, config_stdsubmatch, 306 CFARG_LOCATORS, locs, 307 CFARG_EOL)); 308 309 /* If initialization did not succeed, NULL the pointer. */ 310 if (sc->sc_ed[devno] 311 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 312 sc->sc_ed[devno] = NULL; 313 } 314 315 /* enable full error dumps again */ 316 sc->sc_flags &= ~DASD_QUIET; 317 318 /* 319 * Check if there are any disks attached. If not, disestablish 320 * the interrupt. 321 */ 322 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 323 if (sc->sc_ed[devno]) 324 break; 325 } 326 327 if (devno == sc->sc_maxdevs) { 328 aprint_error("%s: disabling controller (no drives attached)\n", 329 device_xname(sc->sc_dev)); 330 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 331 return; 332 } 333 334 /* 335 * Run the worker thread. 336 */ 337 config_pending_incr(self); 338 if ((error = kthread_create(PRI_NONE, 0, NULL, edcworker, sc, NULL, 339 "%s", device_xname(sc->sc_dev)))) { 340 aprint_error_dev(sc->sc_dev, 341 "cannot spawn worker thread: errno=%d\n", error); 342 panic("edc_mca_attach"); 343 } 344 } 345 346 void 347 edc_add_disk(struct edc_mca_softc *sc, struct ed_softc *ed) 348 { 349 sc->sc_ed[ed->sc_devno] = ed; 350 } 351 352 static int 353 edc_intr(void *arg) 354 { 355 struct edc_mca_softc *sc = arg; 356 u_int8_t isr, intr_id; 357 u_int16_t sifr; 358 int cmd = -1, devno; 359 360 /* 361 * Check if the interrupt was for us. 362 */ 363 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 364 return (0); 365 366 /* 367 * Read ISR to find out interrupt type. This also clears the interrupt 368 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 369 * and 4 are reserved and not used. 370 */ 371 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 372 intr_id = isr & ISR_INTR_ID_MASK; 373 374 #ifdef EDC_DEBUG 375 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 376 aprint_error_dev(sc->sc_dev, "bogus interrupt id %d\n", 377 (int) intr_id); 378 return (0); 379 } 380 #endif 381 382 /* Get number of device whose intr this was */ 383 devno = (isr & 0xe0) >> 5; 384 385 /* 386 * Get Status block. Higher byte always says how long the status 387 * block is, rest is device number and command code. 388 * Check the status block length against our supported maximum length 389 * and fetch the data. 390 */ 391 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 392 size_t len; 393 int i; 394 395 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 396 len = (sifr & 0xff00) >> 8; 397 #ifdef DEBUG 398 if (len > EDC_MAX_CMD_RES_LEN) 399 panic("%s: maximum Status Length exceeded: %d > %d", 400 device_xname(sc->sc_dev), 401 len, EDC_MAX_CMD_RES_LEN); 402 #endif 403 404 /* Get command code */ 405 cmd = sifr & SIFR_CMD_MASK; 406 407 /* Read whole status block */ 408 sc->status_block[0] = sifr; 409 for(i=1; i < len; i++) { 410 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 411 & BSR_SIFR_FULL) == 0) 412 ; 413 414 sc->status_block[i] = le16toh( 415 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 416 } 417 /* zero out rest */ 418 if (i < EDC_MAX_CMD_RES_LEN) { 419 memset(&sc->status_block[i], 0, 420 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 421 } 422 } 423 424 switch (intr_id) { 425 case ISR_DATA_TRANSFER_RDY: 426 /* 427 * Ready to do DMA. The DMA controller has already been 428 * setup, now just kick disk controller to do the transfer. 429 */ 430 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 431 BCR_INT_ENABLE|BCR_DMA_ENABLE); 432 break; 433 434 case ISR_COMPLETED: 435 case ISR_COMPLETED_WITH_ECC: 436 case ISR_COMPLETED_RETRIES: 437 case ISR_COMPLETED_WARNING: 438 /* 439 * Copy device config data if appropriate. sc->sc_ed[] 440 * entry might be NULL during probe. 441 */ 442 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 443 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 444 sizeof(sc->sc_ed[devno]->sense_data)); 445 } 446 447 sc->sc_stat = STAT_DONE; 448 break; 449 450 case ISR_RESET_COMPLETED: 451 case ISR_ABORT_COMPLETED: 452 /* nothing to do */ 453 break; 454 455 case ISR_ATTN_ERROR: 456 /* 457 * Basically, this means driver bug or something seriously 458 * hosed. panic rather than extending the lossage. 459 * No status block available, so no further info. 460 */ 461 panic("%s: dev %d: attention error", 462 device_xname(sc->sc_dev), 463 devno); 464 /* NOTREACHED */ 465 break; 466 467 default: 468 if ((sc->sc_flags & DASD_QUIET) == 0) 469 edc_dump_status_block(sc, sc->status_block, intr_id); 470 471 sc->sc_stat = STAT_ERROR; 472 break; 473 } 474 475 /* 476 * Unless the interrupt is for Data Transfer Ready or 477 * Attention Error, finish by assertion EOI. This makes 478 * attachment aware the interrupt is processed and system 479 * is ready to accept another one. 480 */ 481 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 482 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 483 484 /* If Read or Write Data, wakeup worker thread to finish it */ 485 if (intr_id != ISR_DATA_TRANSFER_RDY) { 486 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 487 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 488 wakeup(sc); 489 } 490 491 return (1); 492 } 493 494 /* 495 * This follows the exact order for Attention Request as 496 * written in DASD Storage Interface Specification MC (Rev 2.2). 497 */ 498 static int 499 edc_do_attn(struct edc_mca_softc *sc, int attn_type, int devno, int intr_id) 500 { 501 int tries; 502 503 /* 1. Disable interrupts in BCR. */ 504 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 505 506 /* 507 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 508 * a RESET COMPLETED interrupt. 509 */ 510 if (intr_id != ISR_RESET_COMPLETED) { 511 #ifdef EDC_DEBUG 512 if (attn_type == ATN_CMD_REQ 513 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 514 & BSR_INT_PENDING)) 515 panic("%s: edc int pending", device_xname(sc->sc_dev)); 516 #endif 517 518 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 519 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 520 & BSR_BUSY) == 0) 521 break; 522 } 523 524 if (tries == EDC_ATTN_MAXTRIES) { 525 printf("%s: edc_do_attn: timeout waiting for " 526 "attachment to become available\n", 527 device_xname(sc->sc_ed[devno]->sc_dev)); 528 return (EIO); 529 } 530 } 531 532 /* 533 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 534 */ 535 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 536 537 /* 538 * 4. Enable interrupts via BCR. 539 */ 540 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 541 542 return (0); 543 } 544 545 /* 546 * Wait until command is processed, timeout after 'secs' seconds. 547 * We use mono_time, since we don't need actual RTC, just time 548 * interval. 549 */ 550 static void 551 edc_cmd_wait(struct edc_mca_softc *sc, int secs, int poll) 552 { 553 int val; 554 555 if (!poll) { 556 int s; 557 558 /* Not polling, can sleep. Sleep until we are awakened, 559 * but maximum secs seconds. 560 */ 561 s = splbio(); 562 if (sc->sc_stat != STAT_DONE) 563 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 564 splx(s); 565 } 566 567 /* Wait until the command is completely finished */ 568 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 569 & BSR_CMD_INPROGRESS) { 570 if (poll && (val & BSR_INTR)) 571 edc_intr(sc); 572 } 573 } 574 575 /* 576 * Command controller to execute specified command on a device. 577 */ 578 int 579 edc_run_cmd(struct edc_mca_softc *sc, int cmd, int devno, 580 u_int16_t cmd_args[], int cmd_len, int poll) 581 { 582 int i, error, tries; 583 u_int16_t cmd0; 584 585 sc->sc_stat = STAT_START; 586 587 /* Do Attention Request for Command Request. */ 588 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 589 return (error); 590 591 /* 592 * Construct the command. The bits are like this: 593 * 594 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 595 * \_/ 0 0 1 0 \__/ \_____/ 596 * \ \__________/ \ \_ Command Code (see CMD_*) 597 * \ \ \__ Device: 0 common, 7 controller 598 * \ \__ Options: reserved, bit 10=cache bypass bit 599 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 600 * 601 * We always use device 0 or 1, so difference is made only by Command 602 * Code, Command Options and command length. 603 */ 604 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 605 | (devno << 5) 606 | (cmd_args[0] << 8) | cmd; 607 cmd_args[0] = cmd0; 608 609 /* 610 * Write word of CMD to the CIFR. This sets "Command 611 * Interface Register Full (CMD IN)" in BSR. Once the attachment 612 * detects it, it reads the word and clears CMD IN. This all should 613 * be quite fast, so don't sleep in !poll case neither. 614 */ 615 for(i=0; i < cmd_len; i++) { 616 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 617 htole16(cmd_args[i])); 618 619 /* Wait until CMD IN is cleared. */ 620 tries = 0; 621 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 622 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 623 delay(poll ? 1000 : 1); 624 ; 625 626 if (tries == 10000 627 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 628 & BSR_CIFR_FULL) { 629 aprint_error_dev(sc->sc_dev, 630 "device too slow to accept command %d\n", cmd); 631 return (EIO); 632 } 633 } 634 635 /* Wait for command to complete, but maximum 15 seconds. */ 636 edc_cmd_wait(sc, 15, poll); 637 638 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 639 } 640 641 #ifdef EDC_DEBUG 642 static const char * const edc_commands[] = { 643 "Invalid Command", 644 "Read Data", 645 "Write Data", 646 "Read Verify", 647 "Write with Verify", 648 "Seek", 649 "Park Head", 650 "Get Command Complete Status", 651 "Get Device Status", 652 "Get Device Configuration", 653 "Get POS Information", 654 "Translate RBA", 655 "Write Attachment Buffer", 656 "Read Attachment Buffer", 657 "Run Diagnostic Test", 658 "Get Diagnostic Status Block", 659 "Get MFG Header", 660 "Format Unit", 661 "Format Prepare", 662 "Set MAX RBA", 663 "Set Power Saving Mode", 664 "Power Conservation Command", 665 }; 666 667 static const char * const edc_cmd_status[256] = { 668 "Reserved", 669 "Command completed successfully", 670 "Reserved", 671 "Command completed successfully with ECC applied", 672 "Reserved", 673 "Command completed successfully with retries", 674 "Format Command partially completed", /* Status available */ 675 "Command completed successfully with ECC and retries", 676 "Command completed with Warning", /* Command Error is available */ 677 "Aborted", 678 "Reset completed", 679 "Data Transfer Ready", /* No Status Block available */ 680 "Command terminated with failure", /* Device Error is available */ 681 "DMA Error", /* Retry entire command as recovery */ 682 "Command Block Error", 683 "Attention Error (Illegal Attention Code)", 684 /* 0x14 - 0xff reserved */ 685 }; 686 687 static const char * const edc_cmd_error[256] = { 688 "No Error", 689 "Invalid parameter in the command block", 690 "Reserved", 691 "Command not supported", 692 "Command Aborted per request", 693 "Reserved", 694 "Command rejected", /* Attachment diagnostic failure */ 695 "Format Rejected", /* Prepare Format command is required */ 696 "Format Error (Primary Map is not readable)", 697 "Format Error (Secondary map is not readable)", 698 "Format Error (Diagnostic Failure)", 699 "Format Warning (Secondary Map Overflow)", 700 "Reserved" 701 "Format Error (Host Checksum Error)", 702 "Reserved", 703 "Format Warning (Push table overflow)", 704 "Format Warning (More pushes than allowed)", 705 "Reserved", 706 "Format Warning (Error during verifying)", 707 "Invalid device number for the command", 708 /* 0x14-0xff reserved */ 709 }; 710 711 static const char * const edc_dev_errors[] = { 712 "No Error", 713 "Seek Fault", /* Device report */ 714 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 715 "Block not found (ID not found)", 716 "Block not found (AM not found)", 717 "Data ECC Error (hard error)", 718 "ID CRC Error", 719 "RBA Out of Range", 720 "Reserved", 721 "Defective Block", 722 "Reserved", 723 "Selection Error", 724 "Reserved", 725 "Write Fault", 726 "No index or sector pulse", 727 "Device Not Ready", 728 "Seek Error", /* Attachment report */ 729 "Bad Format", 730 "Volume Overflow", 731 "No Data AM Found", 732 "Block not found (No ID AM or ID CRC error occurred)", 733 "Reserved", 734 "Reserved", 735 "No ID found on track (ID search)", 736 /* 0x19 - 0xff reserved */ 737 }; 738 #endif /* EDC_DEBUG */ 739 740 static void 741 edc_dump_status_block(struct edc_mca_softc *sc, u_int16_t *status_block, 742 int intr_id) 743 { 744 #ifdef EDC_DEBUG 745 printf("%s: Command: %s, Status: %s (intr %d)\n", 746 device_xname(sc->sc_dev), 747 edc_commands[status_block[0] & 0x1f], 748 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 749 intr_id 750 ); 751 #else 752 printf("%s: Command: %d, Status: %d (intr %d)\n", 753 device_xname(sc->sc_dev), 754 status_block[0] & 0x1f, 755 SB_GET_CMD_STATUS(status_block), 756 intr_id 757 ); 758 #endif 759 printf("%s: # left blocks: %u, last processed RBA: %u\n", 760 device_xname(sc->sc_dev), 761 status_block[SB_RESBLKCNT_IDX], 762 (status_block[5] << 16) | status_block[4]); 763 764 if (intr_id == ISR_COMPLETED_WARNING) { 765 #ifdef EDC_DEBUG 766 aprint_error_dev(sc->sc_dev, "Command Error Code: %s\n", 767 edc_cmd_error[status_block[1] & 0xff]); 768 #else 769 aprint_error_dev(sc->sc_dev, "Command Error Code: %d\n", 770 status_block[1] & 0xff); 771 #endif 772 } 773 774 if (intr_id == ISR_CMD_FAILED) { 775 #ifdef EDC_DEBUG 776 char buf[100]; 777 778 printf("%s: Device Error Code: %s\n", 779 device_xname(sc->sc_dev), 780 edc_dev_errors[status_block[2] & 0xff]); 781 snprintb(buf, sizeof(buf), 782 "\20" 783 "\01SeekOrCmdComplete" 784 "\02Track0Flag" 785 "\03WriteFault" 786 "\04Selected" 787 "\05Ready" 788 "\06Reserved0" 789 "\07STANDBY" 790 "\010Reserved0", (status_block[2] & 0xff00) >> 8); 791 792 printf("%s: Device Status: %s\n", 793 device_xname(sc->sc_dev), buf); 794 #else 795 printf("%s: Device Error Code: %d, Device Status: %d\n", 796 device_xname(sc->sc_dev), 797 status_block[2] & 0xff, 798 (status_block[2] & 0xff00) >> 8); 799 #endif 800 } 801 } 802 /* 803 * Main worker thread function. 804 */ 805 void 806 edcworker(void *arg) 807 { 808 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 809 struct ed_softc *ed; 810 struct buf *bp; 811 int i, error; 812 813 config_pending_decr(sc->sc_dev); 814 815 for(;;) { 816 /* Wait until awakened */ 817 (void) tsleep(sc, PRIBIO, "edcidle", 0); 818 819 for(i=0; i<sc->sc_maxdevs; ) { 820 if ((ed = sc->sc_ed[i]) == NULL) { 821 i++; 822 continue; 823 } 824 825 /* Is there a buf for us ? */ 826 mutex_enter(&ed->sc_q_lock); 827 if ((bp = bufq_get(ed->sc_q)) == NULL) { 828 mutex_exit(&ed->sc_q_lock); 829 i++; 830 continue; 831 } 832 mutex_exit(&ed->sc_q_lock); 833 834 /* Instrumentation. */ 835 disk_busy(&ed->sc_dk); 836 837 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 838 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 839 840 if (error) { 841 bp->b_error = error; 842 } else { 843 /* Set resid, most commonly to zero. */ 844 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 845 } 846 847 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 848 (bp->b_flags & B_READ)); 849 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 850 biodone(bp); 851 } 852 } 853 } 854 855 int 856 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 857 size_t bcount, daddr_t rawblkno, int isread, int poll) 858 { 859 u_int16_t cmd_args[4]; 860 int error=0, fl; 861 u_int16_t track; 862 u_int16_t cyl; 863 u_int8_t head; 864 u_int8_t sector; 865 866 mca_disk_busy(); 867 868 /* set WAIT and R/W flag appropriately for the DMA transfer */ 869 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 870 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 871 872 /* Load the buffer for DMA transfer. */ 873 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 874 bcount, NULL, BUS_DMA_STREAMING|fl))) { 875 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 876 device_xname(ed->sc_dev), error); 877 goto out; 878 } 879 880 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 881 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 882 883 track = rawblkno / ed->sectors; 884 head = track % ed->heads; 885 cyl = track / ed->heads; 886 sector = rawblkno % ed->sectors; 887 888 /* Read or Write Data command */ 889 cmd_args[0] = 2; /* Options 0000010 */ 890 cmd_args[1] = bcount / DEV_BSIZE; 891 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 892 cmd_args[3] = ((cyl & 0x3E0) >> 5); 893 error = edc_run_cmd(sc, 894 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 895 ed->sc_devno, cmd_args, 4, poll); 896 897 /* Sync the DMA memory */ 898 if (!error) { 899 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 900 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 901 } 902 903 /* We are done, unload buffer from DMA map */ 904 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 905 906 out: 907 mca_disk_unbusy(); 908 909 return (error); 910 } 911