1 /* $NetBSD: edc_mca.c,v 1.15 2001/12/31 22:09:27 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jaromir Dolecek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 38 * spec. 39 * 40 * The driver was written with DASD Storage Interface Specification 41 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>. 42 * 43 * TODO: 44 * - improve error recovery 45 * Issue soft reset on error or timeout? 46 * - test with > 1 disk (this is supported by some controllers) 47 * - test with > 1 ESDI controller in machine; shared interrupts 48 * necessary for this to work should be supported - edc_intr() specifically 49 * checks if the interrupt is for this controller 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.15 2001/12/31 22:09:27 thorpej Exp $"); 54 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/errno.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/endian.h> 63 #include <sys/disklabel.h> 64 #include <sys/disk.h> 65 #include <sys/syslog.h> 66 #include <sys/proc.h> 67 #include <sys/vnode.h> 68 #include <sys/kernel.h> 69 #include <sys/kthread.h> 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <machine/bus.h> 75 #include <machine/intr.h> 76 77 #include <dev/mca/mcareg.h> 78 #include <dev/mca/mcavar.h> 79 #include <dev/mca/mcadevs.h> 80 81 #include <dev/mca/edcreg.h> 82 #include <dev/mca/edvar.h> 83 #include <dev/mca/edcvar.h> 84 85 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 86 #define EDC_MAX_CMD_RES_LEN 8 87 88 struct edc_mca_softc { 89 struct device sc_dev; 90 91 bus_space_tag_t sc_iot; 92 bus_space_handle_t sc_ioh; 93 94 /* DMA related stuff */ 95 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 96 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 97 98 void *sc_ih; /* interrupt handle */ 99 100 int sc_flags; 101 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 102 103 #define DASD_MAXDEVS 8 104 struct ed_softc *sc_ed[DASD_MAXDEVS]; 105 int sc_maxdevs; /* max number of disks attached to this 106 * controller */ 107 108 /* I/O results variables */ 109 volatile int sc_error; 110 volatile int sc_resblk; /* residual block count */ 111 }; 112 113 int edc_mca_probe __P((struct device *, struct cfdata *, void *)); 114 void edc_mca_attach __P((struct device *, struct device *, void *)); 115 116 struct cfattach edc_mca_ca = { 117 sizeof(struct edc_mca_softc), edc_mca_probe, edc_mca_attach 118 }; 119 120 static int edc_intr __P((void *)); 121 static void edc_dump_status_block __P((struct edc_mca_softc *, 122 u_int16_t *, int)); 123 static int edc_do_attn __P((struct edc_mca_softc *, int, int, int)); 124 static int edc_cmd_wait __P((struct edc_mca_softc *, int, int)); 125 static void edcworker __P((void *)); 126 static void edc_spawn_worker __P((void *)); 127 128 int 129 edc_mca_probe(parent, match, aux) 130 struct device *parent; 131 struct cfdata *match; 132 void *aux; 133 { 134 struct mca_attach_args *ma = aux; 135 136 switch (ma->ma_id) { 137 case MCA_PRODUCT_IBM_ESDIC: 138 case MCA_PRODUCT_IBM_ESDIC_IG: 139 return (1); 140 default: 141 return (0); 142 } 143 } 144 145 void 146 edc_mca_attach(parent, self, aux) 147 struct device *parent, *self; 148 void *aux; 149 { 150 struct edc_mca_softc *sc = (void *) self; 151 struct mca_attach_args *ma = aux; 152 struct ed_attach_args eda; 153 int pos2, pos3, pos4; 154 int irq, drq, iobase; 155 const char *typestr; 156 int devno, error; 157 158 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 159 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 160 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 161 162 /* 163 * POS register 2: (adf pos0) 164 * 165 * 7 6 5 4 3 2 1 0 166 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 167 * \ \ \___ Primary/Alternate Port Adresses: 168 * \ \ 0=0x3510-3517 1=0x3518-0x351f 169 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 170 * \ 0000=0 0001=1 0011=3 0100=4 171 * \_________ Fairness On/Off: 1=On 0=Off 172 * 173 * POS register 3: (adf pos1) 174 * 175 * 7 6 5 4 3 2 1 0 176 * 0 0 \_/ 177 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 178 * 01=16ms 00=Burst Disabled 179 * 180 * POS register 4: (adf pos2) 181 * 182 * 7 6 5 4 3 2 1 0 183 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 184 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 185 * 186 * IRQ is fixed to 14 (0x0e). 187 */ 188 189 switch (ma->ma_id) { 190 case MCA_PRODUCT_IBM_ESDIC: 191 typestr = "IBM ESDI Fixed Disk Controller"; 192 break; 193 case MCA_PRODUCT_IBM_ESDIC_IG: 194 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 195 break; 196 default: 197 /* never reached */ ; 198 } 199 200 irq = ESDIC_IRQ; 201 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 202 drq = (pos2 & DRQ_MASK) >> 2; 203 204 printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 205 irq, drq, typestr); 206 207 #ifdef DIAGNOSTIC 208 /* 209 * It's not strictly necessary to check this, machine configuration 210 * utility uses only valid adresses. 211 */ 212 if (drq == 2 || drq >= 8) { 213 printf("%s: invalid DMA Arbitration Level %d\n", 214 sc->sc_dev.dv_xname, drq); 215 return; 216 } 217 #endif 218 219 printf("%s: Fairness %s, Release %s, ", 220 sc->sc_dev.dv_xname, 221 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 222 (pos4 & RELEASE_1) ? "6ms" 223 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 224 ); 225 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 226 static const char * const pacint[] = 227 { "disabled", "16ms", "24ms", "31ms"}; 228 printf("DMA burst pacing interval %s\n", 229 pacint[(pos3 & PACING_INT_MASK) >> 4]); 230 } else 231 printf("DMA pacing control disabled\n"); 232 233 sc->sc_iot = ma->ma_iot; 234 235 if (bus_space_map(sc->sc_iot, iobase, 236 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 237 printf("%s: couldn't map registers\n", 238 sc->sc_dev.dv_xname); 239 return; 240 } 241 242 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 243 if (sc->sc_ih == NULL) { 244 printf("%s: couldn't establish interrupt handler\n", 245 sc->sc_dev.dv_xname); 246 return; 247 } 248 249 /* Create a MCA DMA map, used for data transfer */ 250 sc->sc_dmat = ma->ma_dmat; 251 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 252 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 253 &sc->sc_dmamap_xfer, drq)) != 0){ 254 printf("%s: couldn't create DMA map - error %d\n", 255 sc->sc_dev.dv_xname, error); 256 return; 257 } 258 259 /* 260 * Integrated ESDI controller supports only one disk, other 261 * controllers support two disks. 262 */ 263 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 264 sc->sc_maxdevs = 1; 265 else 266 sc->sc_maxdevs = 2; 267 268 /* 269 * Reset controller and attach individual disks. ed attach routine 270 * uses polling so that this works with interrupts disabled. 271 */ 272 273 /* Do a reset to ensure sane state after warm boot. */ 274 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 275 /* hard reset */ 276 printf("%s: controller busy, performing hardware reset ...\n", 277 sc->sc_dev.dv_xname); 278 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 279 BCR_INT_ENABLE|BCR_RESET); 280 } else { 281 /* "SOFT" reset */ 282 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 283 } 284 285 /* 286 * Since interrupts are disabled ATM, it's necessary 287 * to detect the interrupt request and call edc_intr() 288 * explicitly. See also edc_run_cmd(). 289 */ 290 while(bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 291 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 292 edc_intr(sc); 293 294 delay(100); 295 } 296 297 /* be quiet during probes */ 298 sc->sc_flags |= DASD_QUIET; 299 300 /* check for attached disks */ 301 for(devno=0; devno < sc->sc_maxdevs; devno++) { 302 eda.edc_drive = devno; 303 sc->sc_ed[devno] = 304 (void *) config_found_sm(self, &eda, NULL, NULL); 305 306 /* If initialization did not succeed, NULL the pointer. */ 307 if (sc->sc_ed[devno] 308 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 309 sc->sc_ed[devno] = NULL; 310 } 311 312 /* enable full error dumps again */ 313 sc->sc_flags &= ~DASD_QUIET; 314 315 /* 316 * Check if there are any disks attached. If not, disestablish 317 * the interrupt. 318 */ 319 for(devno=0; devno < sc->sc_maxdevs; devno++) { 320 if (sc->sc_ed[devno]) 321 break; 322 } 323 324 if (devno == sc->sc_maxdevs) { 325 printf("%s: disabling controller (no drives attached)\n", 326 sc->sc_dev.dv_xname); 327 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 328 return; 329 } 330 331 /* 332 * Run the worker thread. 333 */ 334 config_pending_incr(); 335 kthread_create(edc_spawn_worker, (void *) sc); 336 } 337 338 void 339 edc_add_disk(sc, ed) 340 struct edc_mca_softc *sc; 341 struct ed_softc *ed; 342 { 343 sc->sc_ed[ed->sc_devno] = ed; 344 } 345 346 static int 347 edc_intr(arg) 348 void *arg; 349 { 350 struct edc_mca_softc *sc = arg; 351 u_int8_t isr, intr_id; 352 u_int16_t sifr; 353 int cmd=-1, devno, error=0; 354 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; /* CMD status block */ 355 356 /* 357 * Check if the interrupt was for us. 358 */ 359 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 360 return (0); 361 362 /* 363 * Read ISR to find out interrupt type. This also clears the interrupt 364 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 365 * and 4 are reserved and not used. 366 */ 367 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 368 intr_id = isr & ISR_INTR_ID_MASK; 369 370 #ifdef DEBUG 371 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 372 printf("%s: bogus interrupt id %d\n", sc->sc_dev.dv_xname, 373 (int) intr_id); 374 return (0); 375 } 376 #endif 377 378 /* Get number of device whose intr this was */ 379 devno = (isr & 0xe0) >> 5; 380 381 /* 382 * Get Status block. Higher byte always says how long the status 383 * block is, rest is device number and command code. 384 * Check the status block length against our supported maximum length 385 * and fetch the data. 386 */ 387 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 388 size_t len; 389 int i; 390 391 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 392 len = (sifr & 0xff00) >> 8; 393 #ifdef DEBUG 394 if (len > EDC_MAX_CMD_RES_LEN) 395 panic("%s: maximum Status Length exceeded: %d > %d", 396 sc->sc_dev.dv_xname, 397 len, EDC_MAX_CMD_RES_LEN); 398 #endif 399 400 /* Get command code */ 401 cmd = sifr & SIFR_CMD_MASK; 402 403 /* Read whole status block */ 404 memset(status_block, 0, sizeof(status_block)); /* zero first */ 405 status_block[0] = sifr; 406 for(i=1; i < len; i++) { 407 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 408 & BSR_SIFR_FULL) == 0) 409 delay(1); 410 411 status_block[i] = le16toh( 412 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 413 } 414 } 415 416 switch (intr_id) { 417 case ISR_DATA_TRANSFER_RDY: 418 /* 419 * Ready to do DMA. The DMA controller has already been 420 * setup, now just kick disk controller to do the transfer. 421 */ 422 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 423 BCR_INT_ENABLE|BCR_DMA_ENABLE); 424 break; 425 case ISR_COMPLETED: 426 case ISR_COMPLETED_WITH_ECC: 427 case ISR_COMPLETED_RETRIES: 428 case ISR_COMPLETED_WARNING: 429 error = 0; 430 431 /* 432 * Copy device config data if appropriate. sc->sc_ed[] 433 * entry might be NULL during probe. 434 */ 435 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 436 memcpy(sc->sc_ed[devno]->sense_data, status_block, 437 sizeof(sc->sc_ed[devno]->sense_data)); 438 } 439 440 break; 441 case ISR_RESET_COMPLETED: 442 case ISR_ABORT_COMPLETED: 443 /* nothing to do */ 444 break; 445 default: 446 if ((sc->sc_flags & DASD_QUIET) == 0) 447 edc_dump_status_block(sc, status_block, intr_id); 448 449 error = EIO; 450 break; 451 } 452 453 /* 454 * Unless the interrupt is for Data Transfer Ready or 455 * Attention Error, finish by assertion EOI. This makes 456 * attachment aware the interrupt is processed and system 457 * is ready to accept another one. 458 */ 459 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 460 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 461 462 /* If Read or Write Data, wakeup worker thread to finish it */ 463 if (intr_id != ISR_DATA_TRANSFER_RDY 464 && (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA)) { 465 if ((sc->sc_error = error) == 0) 466 sc->sc_resblk = status_block[SB_RESBLKCNT_IDX]; 467 wakeup_one(sc); 468 } 469 470 return (1); 471 } 472 473 /* 474 * This follows the exact order for Attention Request as 475 * written in DASD Storage Interface Specification MC (Rev 2.2). 476 */ 477 static int 478 edc_do_attn(sc, attn_type, devno, intr_id) 479 struct edc_mca_softc *sc; 480 int attn_type, devno, intr_id; 481 { 482 int tries; 483 484 /* 1. Disable interrupts in BCR. */ 485 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 486 487 /* 488 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 489 * a RESET COMPLETED interrupt. 490 */ 491 if (intr_id != ISR_RESET_COMPLETED) { 492 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 493 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 494 & BSR_BUSY) == 0) { 495 #ifdef DEBUG 496 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, 497 BSR) & BSR_INT_PENDING) && intr_id) 498 panic("foobar"); 499 #endif 500 break; 501 } 502 } 503 504 if (tries == EDC_ATTN_MAXTRIES) { 505 printf("%s: edc_do_attn: timeout waiting for attachment to become available\n", 506 sc->sc_ed[devno]->sc_dev.dv_xname); 507 return (EAGAIN); 508 } 509 } 510 511 /* 512 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 513 */ 514 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, 515 attn_type | (devno << 5)); 516 517 /* 518 * 4. Enable interrupts via BCR. 519 */ 520 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 521 522 return (0); 523 } 524 525 /* 526 * Wait until command is processed, timeout after 'secs' seconds. 527 * We use mono_time, since we don't need actual RTC, just time 528 * interval. 529 */ 530 static int 531 edc_cmd_wait(sc, secs, poll) 532 struct edc_mca_softc *sc; 533 int secs, poll; 534 { 535 int val, delayed; 536 537 if (!poll) { 538 int error; 539 540 /* Not polling, can sleep. Sleep until we are awakened, 541 * but maximum secs seconds. 542 */ 543 error = tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 544 if (error) 545 goto err; 546 return (0); 547 } 548 549 /* Poll the controller until command finishes */ 550 delayed = 0; 551 do { 552 val = bus_space_read_1(sc->sc_iot,sc->sc_ioh, BSR); 553 if ((val & BSR_CMD_INPROGRESS) == 0) 554 break; 555 556 if (val & BSR_INTR) 557 break; 558 559 delay(1); 560 561 /* 562 * This is not as accurate as checking mono_time, but 563 * it works with hardclock interrupts disabled too. 564 */ 565 delayed++; 566 if (delayed == 1000000) { 567 delayed = 0; 568 secs--; 569 } 570 } while(secs > 0); 571 572 if (secs == 0 && 573 bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_CMD_INPROGRESS){ 574 err: 575 printf("%s: timed out waiting for cmd to finish\n", 576 sc->sc_dev.dv_xname); 577 return (EAGAIN); 578 } 579 580 return (0); 581 } 582 583 int 584 edc_run_cmd(sc, cmd, devno, cmd_args, cmd_len, poll) 585 struct edc_mca_softc *sc; 586 int cmd; 587 int devno; 588 u_int16_t cmd_args[]; 589 int cmd_len, poll; 590 { 591 int i, error, tries; 592 u_int16_t cmd0; 593 594 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 595 printf("%s: device busy?\n", sc->sc_dev.dv_xname); 596 return (EAGAIN); 597 } 598 599 /* Do Attention Request for Command Request. */ 600 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 601 return (error); 602 603 /* 604 * Construct the command. The bits are like this: 605 * 606 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 607 * \_/ 0 0 1 0 \__/ \_____/ 608 * \ \__________/ \ \_ Command Code (see CMD_*) 609 * \ \ \__ Device: 0 common, 7 controller 610 * \ \__ Options: reserved, bit 10=cache bypass bit 611 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 612 * 613 * We always use device 0 or 1, so difference is made only by Command 614 * Code, Command Options and command length. 615 */ 616 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 617 | (devno << 5) 618 | (cmd_args[0] << 8) | cmd; 619 cmd_args[0] = cmd0; 620 621 /* 622 * Write word of CMD to the CIFR. This sets "Command 623 * Interface Register Full (CMD IN)" in BSR. Once the attachment 624 * detects it, it reads the word and clears CMD IN. This all should 625 * be quite fast, so don't bother with sleeps for !poll case. 626 */ 627 for(i=0; i < cmd_len; i++) { 628 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 629 htole16(cmd_args[i])); 630 631 /* 632 * Wait until CMD IN is cleared. The 1ms delay for polling 633 * case is necessary, otherwise e.g. system dump gets stuck 634 * soon. Quirky hw ? 635 */ 636 tries = 0; 637 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 638 & BSR_CIFR_FULL) && tries < 1000 ; tries++) 639 delay(poll ? 1000 : 1); 640 641 if (tries == 10000) { 642 printf("%s: device too slow to accept command %d\n", 643 sc->sc_dev.dv_xname, cmd); 644 return (EAGAIN); 645 } 646 } 647 648 /* Wait for command to complete, but maximum 15 seconds. */ 649 if ((error = edc_cmd_wait(sc, 15, poll))) 650 return (error); 651 652 /* If polling, call edc_intr() explicitly */ 653 if (poll) { 654 edc_intr(sc); 655 656 /* 657 * If got attention id DATA TRANSFER READY, wait for 658 * the transfer to finish. 659 */ 660 if ((cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 661 && sc->sc_error == 0) { 662 if ((error = edc_cmd_wait(sc, 15, poll))) 663 return (error); 664 edc_intr(sc); 665 } 666 667 if ((error = edc_cmd_wait(sc, 15, poll))) 668 return (error); 669 } 670 671 return (sc->sc_error); 672 } 673 674 #ifdef EDC_DEBUG 675 static const char * const edc_commands[] = { 676 "Invalid Command", 677 "Read Data", 678 "Write Data", 679 "Read Verify", 680 "Write with Verify", 681 "Seek", 682 "Park Head", 683 "Get Command Complete Status", 684 "Get Device Status", 685 "Get Device Configuration", 686 "Get POS Information", 687 "Translate RBA", 688 "Write Attachment Buffer", 689 "Read Attachment Buffer", 690 "Run Diagnostic Test", 691 "Get Diagnostic Status Block", 692 "Get MFG Header", 693 "Format Unit", 694 "Format Prepare", 695 "Set MAX RBA", 696 "Set Power Saving Mode", 697 "Power Conservation Command", 698 }; 699 700 static const char * const edc_cmd_status[256] = { 701 "Reserved", 702 "Command completed successfully", 703 "Reserved", 704 "Command completed successfully with ECC applied", 705 "Reserved", 706 "Command completed successfully with retries", 707 "Format Command partially completed", /* Status available */ 708 "Command completed successfully with ECC and retries", 709 "Command completed with Warning", /* Command Error is available */ 710 "Aborted", 711 "Reset completed", 712 "Data Transfer Ready", /* No Status Block available */ 713 "Command terminated with failure", /* Device Error is available */ 714 "DMA Error", /* Retry entire command as recovery */ 715 "Command Block Error", 716 "Attention Error (Illegal Attention Code)", 717 /* 0x14 - 0xff reserved */ 718 }; 719 720 static const char * const edc_cmd_error[256] = { 721 "No Error", 722 "Invalid parameter in the command block", 723 "Reserved", 724 "Command not supported", 725 "Command Aborted per request", 726 "Reserved", 727 "Command rejected", /* Attachment diagnostic failure */ 728 "Format Rejected", /* Prepare Format command is required */ 729 "Format Error (Primary Map is not readable)", 730 "Format Error (Secondary map is not readable)", 731 "Format Error (Diagnostic Failure)", 732 "Format Warning (Secondary Map Overflow)", 733 "Reserved" 734 "Format Error (Host Checksum Error)", 735 "Reserved", 736 "Format Warning (Push table overflow)", 737 "Format Warning (More pushes than allowed)", 738 "Reserved", 739 "Format Warning (Error during verifying)", 740 "Invalid device number for the command", 741 /* 0x14-0xff reserved */ 742 }; 743 744 static const char * const edc_dev_errors[] = { 745 "No Error", 746 "Seek Fault", /* Device report */ 747 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 748 "Block not found (ID not found)", 749 "Block not found (AM not found)", 750 "Data ECC Error (hard error)", 751 "ID CRC Error", 752 "RBA Out of Range", 753 "Reserved", 754 "Defective Block", 755 "Reserved", 756 "Selection Error", 757 "Reserved", 758 "Write Fault", 759 "No index or sector pulse", 760 "Device Not Ready", 761 "Seek Error", /* Attachment report */ 762 "Bad Format", 763 "Volume Overflow", 764 "No Data AM Found", 765 "Block not found (No ID AM or ID CRC error occurred)", 766 "Reserved", 767 "Reserved", 768 "No ID found on track (ID search)", 769 /* 0x19 - 0xff reserved */ 770 }; 771 #endif /* EDC_DEBUG */ 772 773 static void 774 edc_dump_status_block(sc, status_block, intr_id) 775 struct edc_mca_softc *sc; 776 u_int16_t *status_block; 777 int intr_id; 778 { 779 #ifdef EDC_DEBUG 780 printf("%s: Command: %s, Status: %s\n", 781 sc->sc_dev.dv_xname, 782 edc_commands[status_block[0] & 0x1f], 783 edc_cmd_status[SB_GET_CMD_STATUS(status_block)] 784 ); 785 #else 786 printf("%s: Command: %d, Status: %d\n", 787 sc->sc_dev.dv_xname, 788 status_block[0] & 0x1f, 789 SB_GET_CMD_STATUS(status_block)); 790 #endif 791 printf("%s: # left blocks: %u, last processed RBA: %u\n", 792 sc->sc_dev.dv_xname, 793 status_block[SB_RESBLKCNT_IDX], 794 (status_block[5] << 16) | status_block[4]); 795 796 if (intr_id == ISR_COMPLETED_WARNING) { 797 #ifdef EDC_DEBUG 798 printf("%s: Command Error Code: %s\n", 799 sc->sc_dev.dv_xname, 800 edc_cmd_error[status_block[1] & 0xff]); 801 #else 802 printf("%s: Command Error Code: %d\n", 803 sc->sc_dev.dv_xname, 804 status_block[1] & 0xff); 805 #endif 806 } 807 808 if (intr_id == ISR_CMD_FAILED) { 809 #ifdef EDC_DEBUG 810 char buf[100]; 811 812 printf("%s: Device Error Code: %s\n", 813 sc->sc_dev.dv_xname, 814 edc_dev_errors[status_block[2] & 0xff]); 815 bitmask_snprintf((status_block[2] & 0xff00) >> 8, 816 "\20" 817 "\01SeekOrCmdComplete" 818 "\02Track0Flag" 819 "\03WriteFault" 820 "\04Selected" 821 "\05Ready" 822 "\06Reserved0" 823 "\07STANDBY" 824 "\010Reserved0", 825 buf, sizeof(buf)); 826 printf("%s: Device Status: %s\n", 827 sc->sc_dev.dv_xname, buf); 828 #else 829 printf("%s: Device Error Code: %d, Device Status: %d\n", 830 sc->sc_dev.dv_xname, 831 status_block[2] & 0xff, 832 (status_block[2] & 0xff00) >> 8); 833 #endif 834 } 835 } 836 837 static void 838 edc_spawn_worker(arg) 839 void *arg; 840 { 841 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 842 int error; 843 struct proc *wrk; 844 845 /* Now, everything is ready, start a kthread */ 846 if ((error = kthread_create1(edcworker, sc, &wrk, 847 "%s", sc->sc_dev.dv_xname))) { 848 printf("%s: cannot spawn worker thread: errno=%d\n", 849 sc->sc_dev.dv_xname, error); 850 panic("edc_spawn_worker"); 851 } 852 } 853 854 /* 855 * Main worker thread function. 856 */ 857 void 858 edcworker(arg) 859 void *arg; 860 { 861 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 862 struct ed_softc *ed; 863 struct buf *bp; 864 int s, i, error; 865 866 config_pending_decr(); 867 868 s = splbio(); 869 870 for(;;) { 871 /* Wait until awakened */ 872 (void) tsleep(sc, PRIBIO, "edcidle", 0); 873 874 for(i=0; i<sc->sc_maxdevs; ) { 875 if ((ed = sc->sc_ed[i]) == NULL) { 876 i++; 877 continue; 878 } 879 880 /* Is there a buf for us ? */ 881 simple_lock(&ed->sc_q_lock); 882 if ((bp = BUFQ_FIRST(&ed->sc_q)) == NULL) { 883 simple_unlock(&ed->sc_q_lock); 884 i++; 885 continue; 886 } 887 BUFQ_REMOVE(&ed->sc_q, bp); 888 simple_unlock(&ed->sc_q_lock); 889 890 /* Instrumentation. */ 891 disk_busy(&ed->sc_dk); 892 893 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 894 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 895 896 if (error) { 897 bp->b_error = error; 898 bp->b_flags |= B_ERROR; 899 } else { 900 /* Set resid, most commonly to zero. */ 901 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 902 } 903 904 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid)); 905 #if NRND > 0 906 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 907 #endif 908 biodone(bp); 909 } 910 } 911 912 splx(s); 913 } 914 915 int 916 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 917 size_t bcount, daddr_t rawblkno, int isread, int poll) 918 { 919 u_int16_t cmd_args[4]; 920 int error=0, fl; 921 u_int16_t track; 922 u_int16_t cyl; 923 u_int8_t head; 924 u_int8_t sector; 925 926 mca_disk_busy(); 927 928 /* set WAIT and R/W flag appropriately for the DMA transfer */ 929 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 930 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 931 932 /* Load the buffer for DMA transfer. */ 933 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 934 bcount, NULL, BUS_DMA_STREAMING|fl))) { 935 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 936 ed->sc_dev.dv_xname, error); 937 goto out; 938 } 939 940 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 941 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 942 943 track = rawblkno / ed->sectors; 944 head = track % ed->heads; 945 cyl = track / ed->heads; 946 sector = rawblkno % ed->sectors; 947 948 /* Read or Write Data command */ 949 cmd_args[0] = 2; /* Options 0000010 */ 950 cmd_args[1] = bcount / DEV_BSIZE; 951 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 952 cmd_args[3] = ((cyl & 0x3E0) >> 5); 953 error = edc_run_cmd(sc, 954 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 955 ed->sc_devno, cmd_args, 4, poll); 956 957 /* Sync the DMA memory */ 958 if (!error) { 959 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 960 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 961 } 962 963 /* We are done, unload buffer from DMA map */ 964 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 965 966 out: 967 mca_disk_unbusy(); 968 969 return (error); 970 } 971