1 /* $NetBSD: mvgbereg.h,v 1.3 2011/02/01 23:40:12 jakllsch Exp $ */ 2 /* 3 * Copyright (c) 2007 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _MVGBEREG_H_ 28 #define _MVGBEREG_H_ 29 30 #define MVGBE_SIZE 0x4000 31 32 #define MVGBE_NWINDOW 6 33 #define MVGBE_NREMAP 4 34 35 #define MVGBE_PHY_TIMEOUT 10000 /* msec */ 36 37 #define MVGBE_RX_CSUM_MIN_BYTE 72 38 39 40 /* 41 * Ethernet Unit Registers 42 */ 43 /* Ethernet Unit Global Registers */ 44 #define MVGBE_PHYADDR 0x2000 45 #if defined(MV88W8660) 46 #define MVGBE_SMI 0x8010 47 #else 48 #define MVGBE_SMI 0x2004 49 #endif 50 #define MVGBE_EUDA 0x2008 /* Ethernet Unit Default Address */ 51 #define MVGBE_EUDID 0x200c /* Ethernet Unit Default ID */ 52 #define MVGBE_EU 0x2014 /* Ethernet Unit Reserved */ 53 #define MVGBE_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */ 54 #define MVGBE_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */ 55 #define MVGBE_EUEA 0x2094 /* Ethernet Unit Error Address */ 56 #define MVGBE_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */ 57 #define MVGBE_EUPCR 0x20a0 /* EthernetUnit Port Pads Calibration */ 58 #define MVGBE_EUC 0x20b0 /* Ethernet Unit Control */ 59 60 #define MVGBE_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */ 61 #define MVGBE_S(n) (0x2204 + ((n) << 3)) /* Size */ 62 #define MVGBE_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */ 63 #define MVGBE_BARE 0x2290 /* Base Address Enable */ 64 #define MVGBE_EPAP 0x2294 /* Ethernet Port Access Protect */ 65 66 /* Ethernet Unit Port Registers */ 67 #define MVGBE_PORTR_BASE 0x2400 68 #define MVGBE_PORTR_SIZE 0x400 69 70 #define MVGBE_PXC 0x000 /* Port Configuration */ 71 #define MVGBE_PXCX 0x004 /* Port Configuration Extend */ 72 #define MVGBE_MIISP 0x008 /* MII Serial Parameters */ 73 #define MVGBE_GMIISP 0x00c /* GMII Serial Params */ 74 #define MVGBE_EVLANE 0x010 /* VLAN EtherType */ 75 #define MVGBE_MACAL 0x014 /* MAC Address Low */ 76 #define MVGBE_MACAH 0x018 /* MAC Address High */ 77 #define MVGBE_SDC 0x01c /* SDMA Configuration */ 78 #define MVGBE_DSCP(n) (0x020 + ((n) << 2)) 79 #define MVGBE_PSC 0x03c /* Port Serial Control0 */ 80 #define MVGBE_VPT2P 0x040 /* VLAN Priority Tag to Priority */ 81 #define MVGBE_PS 0x044 /* Ethernet Port Status */ 82 #define MVGBE_TQC 0x048 /* Transmit Queue Command */ 83 #define MVGBE_PSC1 0x04c /* Port Serial Control1 */ 84 #define MVGBE_MTU 0x058 /* Max Transmit Unit */ 85 #define MVGBE_IC 0x060 /* Port Interrupt Cause */ 86 #define MVGBE_ICE 0x064 /* Port Interrupt Cause Extend */ 87 #define MVGBE_PIM 0x068 /* Port Interrupt Mask */ 88 #define MVGBE_PEIM 0x06c /* Port Extend Interrupt Mask */ 89 #define MVGBE_PRFUT 0x070 /* Port Rx FIFO Urgent Threshold */ 90 #define MVGBE_PTFUT 0x074 /* Port Tx FIFO Urgent Threshold */ 91 #define MVGBE_PMFS 0x07c /* Port Rx Minimal Frame Size */ 92 #define MVGBE_PXDFC 0x084 /* Port Rx Discard Frame Counter */ 93 #define MVGBE_POFC 0x088 /* Port Overrun Frame Counter */ 94 #define MVGBE_PIAE 0x094 /* Port Internal Address Error */ 95 #define MVGBE_TQFPC 0x0dc /* Transmit Queue Fixed Priority Cfg */ 96 #define MVGBE_CRDP(n) (0x20c + ((n) << 4)) 97 /* Ethernet Current Receive Descriptor Pointers */ 98 #define MVGBE_RQC 0x280 /* Receive Queue Command */ 99 #define MVGBE_TCSDP 0x284 /* Tx Current Served Desc Pointer */ 100 #define MVGBE_TCQDP 0x2c0 /* Tx Current Queue Desc Pointer */ 101 #define MVGBE_TQTBCOUNT(q) (0x300 + ((q) << 4)) 102 /* Transmit Queue Token-Bucket Counter */ 103 #define MVGBE_TQTBCONFIG(q) (0x304 + ((q) << 4)) 104 /* Transmit Queue Token-Bucket Configuration */ 105 #define MVGBE_TQAC(q) (0x308 + ((q) << 4)) 106 /* Transmit Queue Arbiter Configuration */ 107 108 #define MVGBE_PORTDAFR_BASE 0x3400 109 #define MVGBE_PORTDAFR_SIZE 0x400 110 111 #define MVGBE_NDFSMT 0x40 112 #define MVGBE_DFSMT 0x000 113 /* Destination Address Filter Special Multicast Table */ 114 #define MVGBE_NDFOMT 0x40 115 #define MVGBE_DFOMT 0x100 116 /* Destination Address Filter Other Multicast Table */ 117 #define MVGBE_NDFUT 0x4 118 #define MVGBE_DFUT 0x200 119 /* Destination Address Filter Unicast Table */ 120 121 122 /* MAC MIB Counters 0x3000 - 0x307c */ 123 124 125 126 /* PHY Address (MVGBE_PHYADDR) */ 127 #define MVGBE_PHYADDR_PHYAD_MASK 0x1f 128 #define MVGBE_PHYADDR_PHYAD(port, phy) ((phy) << ((port) * 5)) 129 130 /* SMI register fields (MVGBE_SMI) */ 131 #define MVGBE_SMI_DATA_MASK 0x0000ffff 132 #define MVGBE_SMI_PHYAD(phy) (((phy) & 0x1f) << 16) 133 #define MVGBE_SMI_REGAD(reg) (((reg) & 0x1f) << 21) 134 #define MVGBE_SMI_OPCODE_WRITE (0 << 26) 135 #define MVGBE_SMI_OPCODE_READ (1 << 26) 136 #define MVGBE_SMI_READVALID (1 << 27) 137 #define MVGBE_SMI_BUSY (1 << 28) 138 139 /* Ethernet Unit Default ID (MVGBE_EUDID) */ 140 #define MVGBE_EUDID_DIDR_MASK 0x0000000f 141 #define MVGBE_EUDID_DATTR_MASK 0x00000ff0 142 143 /* Ethernet Unit Reserved (MVGBE_EU) */ 144 #define MVGBE_EU_FASTMDC (1 << 0) 145 #define MVGBE_EU_ACCS (1 << 1) 146 147 /* Ethernet Unit Interrupt Cause (MVGBE_EUIC) */ 148 #define MVGBE_EUIC_ETHERINTSUM (1 << 0) 149 #define MVGBE_EUIC_PARITY (1 << 1) 150 #define MVGBE_EUIC_ADDRVIOL (1 << 2) 151 #define MVGBE_EUIC_ADDRVNOMATCH (1 << 3) 152 #define MVGBE_EUIC_SMIDONE (1 << 4) 153 #define MVGBE_EUIC_COUNTWA (1 << 5) 154 #define MVGBE_EUIC_INTADDRERR (1 << 7) 155 #define MVGBE_EUIC_PORT0DPERR (1 << 9) 156 #define MVGBE_EUIC_TOPDPERR (1 << 12) 157 158 /* Ethernet Unit Internal Addr Error (MVGBE_EUIAE) */ 159 #define MVGBE_EUIAE_INTADDR_MASK 0x000001ff 160 161 /* Ethernet Unit Port Pads Calibration (MVGBE_EUPCR) */ 162 #define MVGBE_EUPCR_DRVN_MASK 0x0000001f 163 #define MVGBE_EUPCR_TUNEEN (1 << 16) 164 #define MVGBE_EUPCR_LOCKN_MASK 0x003e0000 165 #define MVGBE_EUPCR_OFFSET_MASK 0x1f000000 /* Reserved */ 166 #define MVGBE_EUPCR_WREN (1 << 31) 167 168 /* Ethernet Unit Control (MVGBE_EUC) */ 169 #define MVGBE_EUC_PORT0DPPAR (1 << 0) 170 #define MVGBE_EUC_TOPDPPAR (1 << 3) 171 #define MVGBE_EUC_PORT0PW (1 << 16) 172 173 /* Base Address (MVGBE_BASEADDR) */ 174 #define MVGBE_BASEADDR_TARGET(target) ((target) & 0xf) 175 #define MVGBE_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8) 176 #define MVGBE_BASEADDR_BASE(base) ((base) & 0xffff0000) 177 178 /* Size (MVGBE_S) */ 179 #define MVGBE_S_SIZE(size) (((size) - 1) & 0xffff0000) 180 181 /* Base Address Enable (MVGBE_BARE) */ 182 #define MVGBE_BARE_EN_MASK ((1 << MVGBE_NWINDOW) - 1) 183 #define MVGBE_BARE_EN(win) ((1 << (win)) & MVGBE_BARE_EN_MASK) 184 185 /* Ethernet Port Access Protect (MVGBE_EPAP) */ 186 #define MVGBE_EPAP_AC_NAC 0x0 /* No access allowed */ 187 #define MVGBE_EPAP_AC_RO 0x1 /* Read Only */ 188 #define MVGBE_EPAP_AC_FA 0x3 /* Full access (r/w) */ 189 #define MVGBE_EPAP_EPAR(win, ac) ((ac) << ((win) * 2)) 190 191 /* Port Configuration (MVGBE_PXC) */ 192 #define MVGBE_PXC_UPM (1 << 0) /* Uni Promisc mode */ 193 #define MVGBE_PXC_RXQ(q) ((q) << 1) 194 #define MVGBE_PXC_RXQ_MASK MVGBE_PXC_RXQ(7) 195 #define MVGBE_PXC_RXQARP(q) ((q) << 4) 196 #define MVGBE_PXC_RXQARP_MASK MVGBE_PXC_RXQARP(7) 197 #define MVGBE_PXC_RB (1 << 7) /* Rej mode of MAC */ 198 #define MVGBE_PXC_RBIP (1 << 8) 199 #define MVGBE_PXC_RBARP (1 << 9) 200 #define MVGBE_PXC_AMNOTXES (1 << 12) 201 #define MVGBE_PXC_TCPCAPEN (1 << 14) 202 #define MVGBE_PXC_UDPCAPEN (1 << 15) 203 #define MVGBE_PXC_TCPQ(q) ((q) << 16) 204 #define MVGBE_PXC_TCPQ_MASK MVGBE_PXC_TCPQ(7) 205 #define MVGBE_PXC_UDPQ(q) ((q) << 19) 206 #define MVGBE_PXC_UDPQ_MASK MVGBE_PXC_UDPQ(7) 207 #define MVGBE_PXC_BPDUQ(q) ((q) << 22) 208 #define MVGBE_PXC_BPDUQ_MASK MVGBE_PXC_BPDUQ(7) 209 #define MVGBE_PXC_RXCS (1 << 25) 210 211 /* Port Configuration Extend (MVGBE_PXCX) */ 212 #define MVGBE_PXCX_SPAN (1 << 1) 213 214 /* MII Serial Parameters (MVGBE_MIISP) */ 215 #define MVGBE_MIISP_JAMLENGTH_12KBIT 0x00000000 216 #define MVGBE_MIISP_JAMLENGTH_24KBIT 0x00000001 217 #define MVGBE_MIISP_JAMLENGTH_32KBIT 0x00000002 218 #define MVGBE_MIISP_JAMLENGTH_48KBIT 0x00000003 219 #define MVGBE_MIISP_JAMIPG(x) (((x) & 0x7c) << 0) 220 #define MVGBE_MIISP_IPGJAMTODATA(x) (((x) & 0x7c) << 5) 221 #define MVGBE_MIISP_IPGDATA(x) (((x) & 0x7c) << 10) 222 #define MVGBE_MIISP_DATABLIND(x) (((x) & 0x1f) << 17) 223 224 /* GMII Serial Parameters (MVGBE_GMIISP) */ 225 #define MVGBE_GMIISP_IPGDATA(x) (((x) >> 4) & 0x7) 226 227 /* SDMA Configuration (MVGBE_SDC) */ 228 #define MVGBE_SDC_RIFB (1 << 0) 229 #define MVGBE_SDC_RXBSZ(x) ((x) << 1) 230 #define MVGBE_SDC_RXBSZ_MASK MVGBE_SDC_RXBSZ(7) 231 #define MVGBE_SDC_RXBSZ_1_64BITWORDS MVGBE_SDC_RXBSZ(0) 232 #define MVGBE_SDC_RXBSZ_2_64BITWORDS MVGBE_SDC_RXBSZ(1) 233 #define MVGBE_SDC_RXBSZ_4_64BITWORDS MVGBE_SDC_RXBSZ(2) 234 #define MVGBE_SDC_RXBSZ_8_64BITWORDS MVGBE_SDC_RXBSZ(3) 235 #define MVGBE_SDC_RXBSZ_16_64BITWORDS MVGBE_SDC_RXBSZ(4) 236 #define MVGBE_SDC_BLMR (1 << 4) 237 #define MVGBE_SDC_BLMT (1 << 5) 238 #define MVGBE_SDC_SWAPMODE (1 << 6) 239 #define MVGBE_SDC_IPGINTRX_MASK __BITS(21, 8) 240 #define MVGBE_SDC_IPGINTRX(x) __SHIFTIN(x, MVGBE_SDC_IPGINTRX_MASK) 241 #define MVGBE_SDC_TXBSZ(x) ((x) << 22) 242 #define MVGBE_SDC_TXBSZ_MASK MVGBE_SDC_TXBSZ(7) 243 #define MVGBE_SDC_TXBSZ_1_64BITWORDS MVGBE_SDC_TXBSZ(0) 244 #define MVGBE_SDC_TXBSZ_2_64BITWORDS MVGBE_SDC_TXBSZ(1) 245 #define MVGBE_SDC_TXBSZ_4_64BITWORDS MVGBE_SDC_TXBSZ(2) 246 #define MVGBE_SDC_TXBSZ_8_64BITWORDS MVGBE_SDC_TXBSZ(3) 247 #define MVGBE_SDC_TXBSZ_16_64BITWORDS MVGBE_SDC_TXBSZ(4) 248 249 /* Port Serial Control (MVGBE_PSC) */ 250 #define MVGBE_PSC_PORTEN (1 << 0) 251 #define MVGBE_PSC_FLP (1 << 1) /* Force_Link_Pass */ 252 #define MVGBE_PSC_ANDUPLEX (1 << 2) /* auto nego */ 253 #define MVGBE_PSC_ANFC (1 << 3) 254 #define MVGBE_PSC_PAUSEADV (1 << 4) 255 #define MVGBE_PSC_FFCMODE (1 << 5) /* Force FC */ 256 #define MVGBE_PSC_FBPMODE (1 << 7) /* Back pressure */ 257 #define MVGBE_PSC_RESERVED (1 << 9) /* Must be set to 1 */ 258 #define MVGBE_PSC_FLFAIL (1 << 10) /* Force Link Fail */ 259 #define MVGBE_PSC_ANSPEED (1 << 13) 260 #define MVGBE_PSC_DTEADVERT (1 << 14) 261 #define MVGBE_PSC_MRU(x) ((x) << 17) 262 #define MVGBE_PSC_MRU_MASK MVGBE_PSC_MRU(7) 263 #define MVGBE_PSC_MRU_1518 0 264 #define MVGBE_PSC_MRU_1522 1 265 #define MVGBE_PSC_MRU_1552 2 266 #define MVGBE_PSC_MRU_9022 3 267 #define MVGBE_PSC_MRU_9192 4 268 #define MVGBE_PSC_MRU_9700 5 269 #define MVGBE_PSC_SETFULLDX (1 << 21) 270 #define MVGBE_PSC_SETFCEN (1 << 22) 271 #define MVGBE_PSC_SETGMIISPEED (1 << 23) 272 #define MVGBE_PSC_SETMIISPEED (1 << 24) 273 274 /* Ethernet Port Status (MVGBE_PS) */ 275 #define MVGBE_PS_LINKUP (1 << 1) 276 #define MVGBE_PS_FULLDX (1 << 2) 277 #define MVGBE_PS_ENFC (1 << 3) 278 #define MVGBE_PS_GMIISPEED (1 << 4) 279 #define MVGBE_PS_MIISPEED (1 << 5) 280 #define MVGBE_PS_TXINPROG (1 << 7) 281 #define MVGBE_PS_TXFIFOEMP (1 << 10) /* FIFO Empty */ 282 283 /* Transmit Queue Command (MVGBE_TQC) */ 284 #define MVGBE_TQC_ENQ (1 << 0) /* Enable Q */ 285 #define MVGBE_TQC_DISQ (1 << 8) /* Disable Q */ 286 287 /* Port Serial Control 1 (MVGBE_PSC1) */ 288 #define MVGBE_PSC1_PCSLB (1 << 1) 289 #define MVGBE_PSC1_RGMIIEN (1 << 3) /* RGMII */ 290 #define MVGBE_PSC1_PRST (1 << 4) /* Port Reset */ 291 292 /* Port Interrupt Cause (MVGBE_IC) */ 293 #define MVGBE_IC_RXBUF (1 << 0) 294 #define MVGBE_IC_EXTEND (1 << 1) 295 #define MVGBE_IC_RXBUFQ_MASK (0xff << 2) 296 #define MVGBE_IC_RXBUFQ(q) (1 << ((q) + 2)) 297 #define MVGBE_IC_RXERROR (1 << 10) 298 #define MVGBE_IC_RXERRQ_MASK (0xff << 11) 299 #define MVGBE_IC_RXERRQ(q) (1 << ((q) + 11)) 300 #define MVGBE_IC_TXEND (1 << 19) 301 #define MVGBE_IC_ETHERINTSUM (1 << 31) 302 303 /* Port Interrupt Cause Extend (MVGBE_ICE) */ 304 #define MVGBE_ICE_TXBUF (1 << 0) 305 #define MVGBE_ICE_TXERR (1 << 8) 306 #define MVGBE_ICE_PHYSTC (1 << 16) 307 #define MVGBE_ICE_RXOVR (1 << 18) 308 #define MVGBE_ICE_TXUDR (1 << 19) 309 #define MVGBE_ICE_LINKCHG (1 << 20) 310 #define MVGBE_ICE_INTADDRERR (1 << 23) 311 #define MVGBE_ICE_ETHERINTSUM (1 << 31) 312 313 /* Port Tx FIFO Urgent Threshold (MVGBE_PTFUT) */ 314 #define MVGBE_PTFUT_IPGINTTX_MASK __BITS(17, 4) 315 #define MVGBE_PTFUT_IPGINTTX(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_MASK) 316 317 /* Port Rx Minimal Frame Size (MVGBE_PMFS) */ 318 #define MVGBE_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c) 319 /* RxMFS = 40,44,48,52,56,60,64 bytes */ 320 321 /* Transmit Queue Fixed Priority Configuration */ 322 #define MVGBE_TQFPC_EN(q) (1 << (q)) 323 324 /* Receive Queue Command (MVGBE_RQC) */ 325 #define MVGBE_RQC_ENQ_MASK (0xff << 0) /* Enable Q */ 326 #define MVGBE_RQC_ENQ(n) (1 << (0 + (n))) 327 #define MVGBE_RQC_DISQ_MASK (0xff << 8) /* Disable Q */ 328 #define MVGBE_RQC_DISQ(n) (1 << (8 + (n))) 329 #define MVGBE_RQC_DISQ_DISABLE(q) ((q) << 8) 330 331 /* Destination Address Filter Registers (MVGBE_DF{SM,OM,U}T) */ 332 #define MVGBE_DF(n, x) ((x) << (8 * (n))) 333 #define MVGBE_DF_PASS (1 << 0) 334 #define MVGBE_DF_QUEUE(q) ((q) << 1) 335 #define MVGBE_DF_QUEUE_MASK ((7) << 1) 336 337 338 /* 339 * Set the chip's packet size limit to 9022. 340 * (ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) 341 */ 342 #define MVGBE_MRU 9022 343 344 #define MVGBE_RXBUF_ALIGN 8 345 #define MVGBE_RXBUF_MASK (MVGBE_RXBUF_ALIGN - 1) 346 #define MVGBE_HWHEADER_SIZE 2 347 348 349 /* 350 * DMA descriptors 351 * Despite the documentation saying these descriptors only need to be 352 * aligned to 16-byte bondaries, 32-byte alignment seems to be required 353 * by the hardware. We'll just pad them out to that to make it easier. 354 */ 355 struct mvgbe_tx_desc { 356 #if BYTE_ORDER == BIG_ENDIAN 357 uint16_t bytecnt; /* Descriptor buffer byte count */ 358 uint16_t l4ichk; /* CPU provided TCP Checksum */ 359 uint32_t cmdsts; /* Descriptor command status */ 360 uint32_t nextdescptr; /* Next descriptor pointer */ 361 uint32_t bufptr; /* Descriptor buffer pointer */ 362 #else /* LITTLE_ENDIAN */ 363 uint32_t cmdsts; /* Descriptor command status */ 364 uint16_t l4ichk; /* CPU provided TCP Checksum */ 365 uint16_t bytecnt; /* Descriptor buffer byte count */ 366 uint32_t bufptr; /* Descriptor buffer pointer */ 367 uint32_t nextdescptr; /* Next descriptor pointer */ 368 #endif 369 uint32_t _padding[4]; 370 } __packed; 371 372 struct mvgbe_rx_desc { 373 #if BYTE_ORDER == BIG_ENDIAN 374 uint16_t bytecnt; /* Descriptor buffer byte count */ 375 uint16_t bufsize; /* Buffer size */ 376 uint32_t cmdsts; /* Descriptor command status */ 377 uint32_t nextdescptr; /* Next descriptor pointer */ 378 uint32_t bufptr; /* Descriptor buffer pointer */ 379 #else /* LITTLE_ENDIAN */ 380 uint32_t cmdsts; /* Descriptor command status */ 381 uint16_t bufsize; /* Buffer size */ 382 uint16_t bytecnt; /* Descriptor buffer byte count */ 383 uint32_t bufptr; /* Descriptor buffer pointer */ 384 uint32_t nextdescptr; /* Next descriptor pointer */ 385 #endif 386 uint32_t _padding[4]; 387 } __packed; 388 389 #define MVGBE_ERROR_SUMMARY (1 << 0) 390 #define MVGBE_BUFFER_OWNED_MASK (1 << 31) 391 #define MVGBE_BUFFER_OWNED_BY_HOST (0 << 31) 392 #define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31) 393 394 #define MVGBE_TX_ERROR_CODE_MASK (3 << 1) 395 #define MVGBE_TX_LATE_COLLISION_ERROR (0 << 1) 396 #define MVGBE_TX_UNDERRUN_ERROR (1 << 1) 397 #define MVGBE_TX_EXCESSIVE_COLLISION_ERRO (2 << 1) 398 #define MVGBE_TX_LLC_SNAP_FORMAT (1 << 9) 399 #define MVGBE_TX_IP_NO_FRAG (1 << 10) 400 #define MVGBE_TX_IP_HEADER_LEN(len) ((len) << 11) 401 #define MVGBE_TX_VLAN_TAGGED_FRAME (1 << 15) 402 #define MVGBE_TX_L4_TYPE_TCP (0 << 16) 403 #define MVGBE_TX_L4_TYPE_UDP (1 << 16) 404 #define MVGBE_TX_GENERATE_L4_CHKSUM (1 << 17) 405 #define MVGBE_TX_GENERATE_IP_CHKSUM (1 << 18) 406 #define MVGBE_TX_ZERO_PADDING (1 << 19) 407 #define MVGBE_TX_LAST_DESC (1 << 20) 408 #define MVGBE_TX_FIRST_DESC (1 << 21) 409 #define MVGBE_TX_GENERATE_CRC (1 << 22) 410 #define MVGBE_TX_ENABLE_INTERRUPT (1 << 23) 411 #define MVGBE_TX_AUTO_MODE (1 << 30) 412 413 #define MVGBE_RX_ERROR_CODE_MASK (3 << 1) 414 #define MVGBE_RX_CRC_ERROR (0 << 1) 415 #define MVGBE_RX_OVERRUN_ERROR (1 << 1) 416 #define MVGBE_RX_MAX_FRAME_LEN_ERROR (2 << 1) 417 #define MVGBE_RX_RESOURCE_ERROR (3 << 1) 418 #define MVGBE_RX_L4_CHECKSUM_MASK (0xffff << 3) 419 #define MVGBE_RX_VLAN_TAGGED_FRAME (1 << 19) 420 #define MVGBE_RX_BPDU_FRAME (1 << 20) 421 #define MVGBE_RX_L4_TYPE_MASK (3 << 21) 422 #define MVGBE_RX_L4_TYPE_TCP (0 << 21) 423 #define MVGBE_RX_L4_TYPE_UDP (1 << 21) 424 #define MVGBE_RX_L4_TYPE_OTHER (2 << 21) 425 #define MVGBE_RX_NOT_LLC_SNAP_FORMAT (1 << 23) 426 #define MVGBE_RX_IP_FRAME_TYPE (1 << 24) 427 #define MVGBE_RX_IP_HEADER_OK (1 << 25) 428 #define MVGBE_RX_LAST_DESC (1 << 26) 429 #define MVGBE_RX_FIRST_DESC (1 << 27) 430 #define MVGBE_RX_UNKNOWN_DA (1 << 28) 431 #define MVGBE_RX_ENABLE_INTERRUPT (1 << 29) 432 #define MVGBE_RX_L4_CHECKSUM (1 << 30) 433 434 #endif /* _MVGEREG_H_ */ 435