1 /* $NetBSD: if_mvgbe.c,v 1.50 2018/06/26 06:48:01 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.50 2018/06/26 06:48:01 msaitoh Exp $"); 29 30 #include "opt_multiprocessor.h" 31 32 #if defined MULTIPROCESSOR 33 #warning Queue Management Method 'Counters' not support. Please use mvxpe instead of this. 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/callout.h> 39 #include <sys/device.h> 40 #include <sys/endian.h> 41 #include <sys/errno.h> 42 #include <sys/evcnt.h> 43 #include <sys/kernel.h> 44 #include <sys/kmem.h> 45 #include <sys/mutex.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/marvell/mvgbereg.h> 52 53 #include <net/if.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 61 #include <net/bpf.h> 62 #include <sys/rndsource.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include "locators.h" 68 69 /* #define MVGBE_DEBUG 3 */ 70 #ifdef MVGBE_DEBUG 71 #define DPRINTF(x) if (mvgbe_debug) printf x 72 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 73 int mvgbe_debug = MVGBE_DEBUG; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 80 #define MVGBE_READ(sc, reg) \ 81 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 82 #define MVGBE_WRITE(sc, reg, val) \ 83 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 84 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 85 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 86 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 87 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 88 89 #define MVGBE_LINKUP_READ(sc) \ 90 bus_space_read_4((sc)->sc_iot, (sc)->sc_linkup.ioh, 0) 91 #define MVGBE_IS_LINKUP(sc) (MVGBE_LINKUP_READ(sc) & (sc)->sc_linkup.bit) 92 93 #define MVGBE_TX_RING_CNT 256 94 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 95 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 96 #define MVGBE_RX_RING_CNT 256 97 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 98 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 99 100 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 101 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 102 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 103 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 104 105 #define MVGBE_JSLOTS 384 /* XXXX */ 106 #define MVGBE_JLEN \ 107 ((MVGBE_MRU + MVGBE_HWHEADER_SIZE + MVGBE_RXBUF_ALIGN - 1) & \ 108 ~MVGBE_RXBUF_MASK) 109 #define MVGBE_NTXSEG 30 110 #define MVGBE_JPAGESZ PAGE_SIZE 111 #define MVGBE_RESID \ 112 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 113 #define MVGBE_JMEM \ 114 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 115 116 #define MVGBE_TX_RING_ADDR(sc, i) \ 117 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 118 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 119 120 #define MVGBE_RX_RING_ADDR(sc, i) \ 121 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 122 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 123 124 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 125 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 126 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 127 128 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 129 do { \ 130 int __x, __n; \ 131 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 132 \ 133 __x = (x); \ 134 __n = (n); \ 135 \ 136 /* If it will wrap around, sync to the end of the ring. */ \ 137 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 138 bus_dmamap_sync((sc)->sc_dmat, \ 139 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 140 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 141 __n -= (MVGBE_TX_RING_CNT - __x); \ 142 __x = 0; \ 143 } \ 144 \ 145 /* Now sync whatever is left. */ \ 146 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 147 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 148 } while (0 /*CONSTCOND*/) 149 150 #define MVGBE_CDRXSYNC(sc, x, ops) \ 151 do { \ 152 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 153 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 154 } while (/*CONSTCOND*/0) 155 156 #define MVGBE_IPGINTTX_DEFAULT 768 157 #define MVGBE_IPGINTRX_DEFAULT 768 158 159 #ifdef MVGBE_EVENT_COUNTERS 160 #define MVGBE_EVCNT_INCR(ev) (ev)->ev_count++ 161 #define MVGBE_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 162 #else 163 #define MVGBE_EVCNT_INCR(ev) /* nothing */ 164 #define MVGBE_EVCNT_ADD(ev, val) /* nothing */ 165 #endif 166 167 struct mvgbe_jpool_entry { 168 int slot; 169 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 170 }; 171 172 struct mvgbe_chain { 173 void *mvgbe_desc; 174 struct mbuf *mvgbe_mbuf; 175 struct mvgbe_chain *mvgbe_next; 176 }; 177 178 struct mvgbe_txmap_entry { 179 bus_dmamap_t dmamap; 180 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 181 }; 182 183 struct mvgbe_chain_data { 184 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 185 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 186 int mvgbe_tx_prod; 187 int mvgbe_tx_cons; 188 int mvgbe_tx_cnt; 189 190 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 191 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 192 bus_dmamap_t mvgbe_rx_jumbo_map; 193 int mvgbe_rx_prod; 194 int mvgbe_rx_cons; 195 int mvgbe_rx_cnt; 196 197 /* Stick the jumbo mem management stuff here too. */ 198 void *mvgbe_jslots[MVGBE_JSLOTS]; 199 void *mvgbe_jumbo_buf; 200 }; 201 202 struct mvgbe_ring_data { 203 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 204 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 205 }; 206 207 struct mvgbec_softc { 208 device_t sc_dev; 209 210 bus_space_tag_t sc_iot; 211 bus_space_handle_t sc_ioh; 212 213 kmutex_t sc_mtx; 214 215 int sc_flags; 216 }; 217 218 struct mvgbe_softc { 219 device_t sc_dev; 220 int sc_port; 221 uint32_t sc_version; 222 223 bus_space_tag_t sc_iot; 224 bus_space_handle_t sc_ioh; 225 bus_space_handle_t sc_dafh; /* dest address filter handle */ 226 bus_dma_tag_t sc_dmat; 227 228 struct ethercom sc_ethercom; 229 struct mii_data sc_mii; 230 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 231 232 callout_t sc_tick_ch; /* tick callout */ 233 234 struct mvgbe_chain_data sc_cdata; 235 struct mvgbe_ring_data *sc_rdata; 236 bus_dmamap_t sc_ring_map; 237 int sc_if_flags; 238 unsigned int sc_ipginttx; 239 unsigned int sc_ipgintrx; 240 int sc_wdogsoft; 241 242 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 243 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 244 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 245 246 struct { 247 bus_space_handle_t ioh; 248 uint32_t bit; 249 } sc_linkup; 250 uint32_t sc_cmdsts_opts; 251 252 krndsource_t sc_rnd_source; 253 struct sysctllog *mvgbe_clog; 254 #ifdef MVGBE_EVENT_COUNTERS 255 struct evcnt sc_ev_rxoverrun; 256 struct evcnt sc_ev_wdogsoft; 257 #endif 258 }; 259 260 261 /* Gigabit Ethernet Unit Global part functions */ 262 263 static int mvgbec_match(device_t, struct cfdata *, void *); 264 static void mvgbec_attach(device_t, device_t, void *); 265 266 static int mvgbec_print(void *, const char *); 267 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 268 269 /* MII funcstions */ 270 static int mvgbec_miibus_readreg(device_t, int, int); 271 static void mvgbec_miibus_writereg(device_t, int, int, int); 272 static void mvgbec_miibus_statchg(struct ifnet *); 273 274 static void mvgbec_wininit(struct mvgbec_softc *, enum marvell_tags *); 275 276 /* Gigabit Ethernet Port part functions */ 277 278 static int mvgbe_match(device_t, struct cfdata *, void *); 279 static void mvgbe_attach(device_t, device_t, void *); 280 281 static void mvgbe_tick(void *); 282 static int mvgbe_intr(void *); 283 284 static void mvgbe_start(struct ifnet *); 285 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 286 static int mvgbe_init(struct ifnet *); 287 static void mvgbe_stop(struct ifnet *, int); 288 static void mvgbe_watchdog(struct ifnet *); 289 290 static int mvgbe_ifflags_cb(struct ethercom *); 291 292 static int mvgbe_mediachange(struct ifnet *); 293 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 294 295 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 296 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 297 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 298 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 299 static void *mvgbe_jalloc(struct mvgbe_softc *); 300 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 301 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 302 static void mvgbe_rxeof(struct mvgbe_softc *); 303 static void mvgbe_txeof(struct mvgbe_softc *); 304 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 305 static void mvgbe_filter_setup(struct mvgbe_softc *); 306 #ifdef MVGBE_DEBUG 307 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 308 #endif 309 static int mvgbe_ipginttx(struct mvgbec_softc *, struct mvgbe_softc *, 310 unsigned int); 311 static int mvgbe_ipgintrx(struct mvgbec_softc *, struct mvgbe_softc *, 312 unsigned int); 313 static void sysctl_mvgbe_init(struct mvgbe_softc *); 314 static int mvgbe_sysctl_ipginttx(SYSCTLFN_PROTO); 315 static int mvgbe_sysctl_ipgintrx(SYSCTLFN_PROTO); 316 317 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 318 mvgbec_match, mvgbec_attach, NULL, NULL); 319 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 320 mvgbec_match, mvgbec_attach, NULL, NULL); 321 322 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 323 mvgbe_match, mvgbe_attach, NULL, NULL); 324 325 device_t mvgbec0 = NULL; 326 static int mvgbe_root_num; 327 328 struct mvgbe_port { 329 int model; 330 int unit; 331 int ports; 332 int irqs[3]; 333 int flags; 334 #define FLAGS_FIX_TQTB (1 << 0) 335 #define FLAGS_FIX_MTU (1 << 1) 336 #define FLAGS_IPG1 (1 << 2) 337 #define FLAGS_IPG2 (1 << 3) 338 #define FLAGS_HAS_PV (1 << 4) /* Has Port Version Register */ 339 } mvgbe_ports[] = { 340 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 341 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 342 #if 0 343 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 344 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 345 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 346 #endif 347 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 348 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU }, 349 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 350 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 351 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 352 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 353 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU }, 354 355 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 356 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 357 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 358 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 359 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 360 { MARVELL_KIRKWOOD_88F6282, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 361 { MARVELL_KIRKWOOD_88F6282, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 362 363 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 364 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 365 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 366 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 367 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 368 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 369 370 { MARVELL_DOVE_88AP510, 0, 1, { 29 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 371 372 { MARVELL_ARMADAXP_MV78130, 0, 1, { 66 }, FLAGS_HAS_PV }, 373 { MARVELL_ARMADAXP_MV78130, 1, 1, { 70 }, FLAGS_HAS_PV }, 374 { MARVELL_ARMADAXP_MV78130, 2, 1, { 74 }, FLAGS_HAS_PV }, 375 { MARVELL_ARMADAXP_MV78160, 0, 1, { 66 }, FLAGS_HAS_PV }, 376 { MARVELL_ARMADAXP_MV78160, 1, 1, { 70 }, FLAGS_HAS_PV }, 377 { MARVELL_ARMADAXP_MV78160, 2, 1, { 74 }, FLAGS_HAS_PV }, 378 { MARVELL_ARMADAXP_MV78160, 3, 1, { 78 }, FLAGS_HAS_PV }, 379 { MARVELL_ARMADAXP_MV78230, 0, 1, { 66 }, FLAGS_HAS_PV }, 380 { MARVELL_ARMADAXP_MV78230, 1, 1, { 70 }, FLAGS_HAS_PV }, 381 { MARVELL_ARMADAXP_MV78230, 2, 1, { 74 }, FLAGS_HAS_PV }, 382 { MARVELL_ARMADAXP_MV78260, 0, 1, { 66 }, FLAGS_HAS_PV }, 383 { MARVELL_ARMADAXP_MV78260, 1, 1, { 70 }, FLAGS_HAS_PV }, 384 { MARVELL_ARMADAXP_MV78260, 2, 1, { 74 }, FLAGS_HAS_PV }, 385 { MARVELL_ARMADAXP_MV78260, 3, 1, { 78 }, FLAGS_HAS_PV }, 386 { MARVELL_ARMADAXP_MV78460, 0, 1, { 66 }, FLAGS_HAS_PV }, 387 { MARVELL_ARMADAXP_MV78460, 1, 1, { 70 }, FLAGS_HAS_PV }, 388 { MARVELL_ARMADAXP_MV78460, 2, 1, { 74 }, FLAGS_HAS_PV }, 389 { MARVELL_ARMADAXP_MV78460, 3, 1, { 78 }, FLAGS_HAS_PV }, 390 391 { MARVELL_ARMADA370_MV6707, 0, 1, { 66 }, FLAGS_HAS_PV }, 392 { MARVELL_ARMADA370_MV6707, 1, 1, { 70 }, FLAGS_HAS_PV }, 393 { MARVELL_ARMADA370_MV6710, 0, 1, { 66 }, FLAGS_HAS_PV }, 394 { MARVELL_ARMADA370_MV6710, 1, 1, { 70 }, FLAGS_HAS_PV }, 395 { MARVELL_ARMADA370_MV6W11, 0, 1, { 66 }, FLAGS_HAS_PV }, 396 { MARVELL_ARMADA370_MV6W11, 1, 1, { 70 }, FLAGS_HAS_PV }, 397 }; 398 399 400 /* ARGSUSED */ 401 static int 402 mvgbec_match(device_t parent, cfdata_t match, void *aux) 403 { 404 struct marvell_attach_args *mva = aux; 405 int i; 406 407 if (strcmp(mva->mva_name, match->cf_name) != 0) 408 return 0; 409 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 410 return 0; 411 412 for (i = 0; i < __arraycount(mvgbe_ports); i++) 413 if (mva->mva_model == mvgbe_ports[i].model) { 414 mva->mva_size = MVGBE_SIZE; 415 return 1; 416 } 417 return 0; 418 } 419 420 /* ARGSUSED */ 421 static void 422 mvgbec_attach(device_t parent, device_t self, void *aux) 423 { 424 struct mvgbec_softc *csc = device_private(self); 425 struct marvell_attach_args *mva = aux, gbea; 426 struct mvgbe_softc *port; 427 struct mii_softc *mii; 428 device_t child; 429 uint32_t phyaddr; 430 int i, j; 431 432 aprint_naive("\n"); 433 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 434 435 csc->sc_dev = self; 436 csc->sc_iot = mva->mva_iot; 437 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 438 mva->mva_size, &csc->sc_ioh)) { 439 aprint_error_dev(self, "Cannot map registers\n"); 440 return; 441 } 442 443 if (mvgbec0 == NULL) 444 mvgbec0 = self; 445 446 phyaddr = 0; 447 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 448 449 mutex_init(&csc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 450 451 /* Disable and clear Gigabit Ethernet Unit interrupts */ 452 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 453 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 454 455 mvgbec_wininit(csc, mva->mva_tags); 456 457 memset(&gbea, 0, sizeof(gbea)); 458 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 459 if (mvgbe_ports[i].model != mva->mva_model || 460 mvgbe_ports[i].unit != mva->mva_unit) 461 continue; 462 463 csc->sc_flags = mvgbe_ports[i].flags; 464 465 for (j = 0; j < mvgbe_ports[i].ports; j++) { 466 gbea.mva_name = "mvgbe"; 467 gbea.mva_model = mva->mva_model; 468 gbea.mva_iot = csc->sc_iot; 469 gbea.mva_ioh = csc->sc_ioh; 470 gbea.mva_unit = j; 471 gbea.mva_dmat = mva->mva_dmat; 472 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 473 child = config_found_sm_loc(csc->sc_dev, "mvgbec", NULL, 474 &gbea, mvgbec_print, mvgbec_search); 475 if (child) { 476 port = device_private(child); 477 mii = LIST_FIRST(&port->sc_mii.mii_phys); 478 if (mii != NULL) 479 phyaddr |= MVGBE_PHYADDR_PHYAD(j, 480 mii->mii_phy); 481 } 482 } 483 break; 484 } 485 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 486 } 487 488 static int 489 mvgbec_print(void *aux, const char *pnp) 490 { 491 struct marvell_attach_args *gbea = aux; 492 493 if (pnp) 494 aprint_normal("%s at %s port %d", 495 gbea->mva_name, pnp, gbea->mva_unit); 496 else { 497 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 498 aprint_normal(" port %d", gbea->mva_unit); 499 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 500 aprint_normal(" irq %d", gbea->mva_irq); 501 } 502 return UNCONF; 503 } 504 505 /* ARGSUSED */ 506 static int 507 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 508 { 509 struct marvell_attach_args *gbea = aux; 510 511 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 512 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 513 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 514 515 return config_match(parent, cf, aux); 516 } 517 518 static int 519 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 520 { 521 struct mvgbe_softc *sc = device_private(dev); 522 struct mvgbec_softc *csc; 523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 524 uint32_t smi, val; 525 int i; 526 527 if (mvgbec0 == NULL) { 528 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 529 return -1; 530 } 531 csc = device_private(mvgbec0); 532 533 mutex_enter(&csc->sc_mtx); 534 535 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 536 DELAY(1); 537 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 538 break; 539 } 540 if (i == MVGBE_PHY_TIMEOUT) { 541 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 542 mutex_exit(&csc->sc_mtx); 543 return -1; 544 } 545 546 smi = 547 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 548 MVGBE_WRITE(csc, MVGBE_SMI, smi); 549 550 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 551 DELAY(1); 552 smi = MVGBE_READ(csc, MVGBE_SMI); 553 if (smi & MVGBE_SMI_READVALID) 554 break; 555 } 556 557 mutex_exit(&csc->sc_mtx); 558 559 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 560 i, MVGBE_PHY_TIMEOUT)); 561 562 val = smi & MVGBE_SMI_DATA_MASK; 563 564 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 565 phy, reg, val)); 566 567 return val; 568 } 569 570 static void 571 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 572 { 573 struct mvgbe_softc *sc = device_private(dev); 574 struct mvgbec_softc *csc; 575 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 576 uint32_t smi; 577 int i; 578 579 if (mvgbec0 == NULL) { 580 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 581 return; 582 } 583 csc = device_private(mvgbec0); 584 585 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 586 phy, reg, val)); 587 588 mutex_enter(&csc->sc_mtx); 589 590 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 591 DELAY(1); 592 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 593 break; 594 } 595 if (i == MVGBE_PHY_TIMEOUT) { 596 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 597 mutex_exit(&csc->sc_mtx); 598 return; 599 } 600 601 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 602 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 603 MVGBE_WRITE(csc, MVGBE_SMI, smi); 604 605 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 606 DELAY(1); 607 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 608 break; 609 } 610 611 mutex_exit(&csc->sc_mtx); 612 613 if (i == MVGBE_PHY_TIMEOUT) 614 aprint_error_ifnet(ifp, "phy write timed out\n"); 615 } 616 617 static void 618 mvgbec_miibus_statchg(struct ifnet *ifp) 619 { 620 621 /* nothing to do */ 622 } 623 624 625 static void 626 mvgbec_wininit(struct mvgbec_softc *sc, enum marvell_tags *tags) 627 { 628 device_t pdev = device_parent(sc->sc_dev); 629 uint64_t base; 630 uint32_t en, ac, size; 631 int window, target, attr, rv, i; 632 633 /* First disable all address decode windows */ 634 en = MVGBE_BARE_EN_MASK; 635 MVGBE_WRITE(sc, MVGBE_BARE, en); 636 637 ac = 0; 638 for (window = 0, i = 0; 639 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 640 rv = marvell_winparams_by_tag(pdev, tags[i], 641 &target, &attr, &base, &size); 642 if (rv != 0 || size == 0) 643 continue; 644 645 if (base > 0xffffffffULL) { 646 if (window >= MVGBE_NREMAP) { 647 aprint_error_dev(sc->sc_dev, 648 "can't remap window %d\n", window); 649 continue; 650 } 651 MVGBE_WRITE(sc, MVGBE_HA(window), 652 (base >> 32) & 0xffffffff); 653 } 654 655 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 656 MVGBE_BASEADDR_TARGET(target) | 657 MVGBE_BASEADDR_ATTR(attr) | 658 MVGBE_BASEADDR_BASE(base)); 659 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 660 661 en &= ~(1 << window); 662 /* set full access (r/w) */ 663 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 664 window++; 665 } 666 /* allow to access decode window */ 667 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 668 669 MVGBE_WRITE(sc, MVGBE_BARE, en); 670 } 671 672 673 /* ARGSUSED */ 674 static int 675 mvgbe_match(device_t parent, cfdata_t match, void *aux) 676 { 677 struct marvell_attach_args *mva = aux; 678 uint32_t pbase, maddrh, maddrl; 679 prop_dictionary_t dict; 680 681 dict = device_properties(parent); 682 if (dict) { 683 if (prop_dictionary_get(dict, "mac-address")) 684 return 1; 685 } 686 687 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 688 maddrh = 689 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 690 maddrl = 691 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 692 if ((maddrh | maddrl) == 0) 693 return 0; 694 695 return 1; 696 } 697 698 /* ARGSUSED */ 699 static void 700 mvgbe_attach(device_t parent, device_t self, void *aux) 701 { 702 struct mvgbec_softc *csc = device_private(parent); 703 struct mvgbe_softc *sc = device_private(self); 704 struct marvell_attach_args *mva = aux; 705 struct mvgbe_txmap_entry *entry; 706 prop_dictionary_t dict; 707 prop_data_t enaddrp; 708 struct ifnet *ifp; 709 bus_dma_segment_t seg; 710 bus_dmamap_t dmamap; 711 int rseg, i; 712 uint32_t maddrh, maddrl; 713 uint8_t enaddr[ETHER_ADDR_LEN]; 714 void *kva; 715 716 aprint_naive("\n"); 717 aprint_normal("\n"); 718 719 dict = device_properties(parent); 720 if (dict) 721 enaddrp = prop_dictionary_get(dict, "mac-address"); 722 else 723 enaddrp = NULL; 724 725 sc->sc_dev = self; 726 sc->sc_port = mva->mva_unit; 727 sc->sc_iot = mva->mva_iot; 728 callout_init(&sc->sc_tick_ch, 0); 729 callout_setfunc(&sc->sc_tick_ch, mvgbe_tick, sc); 730 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 731 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 732 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 733 aprint_error_dev(self, "Cannot map registers\n"); 734 return; 735 } 736 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 737 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 738 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 739 aprint_error_dev(self, 740 "Cannot map destination address filter registers\n"); 741 return; 742 } 743 sc->sc_dmat = mva->mva_dmat; 744 745 if (csc->sc_flags & FLAGS_HAS_PV) { 746 /* GbE port has Port Version register. */ 747 sc->sc_version = MVGBE_READ(sc, MVGBE_PV); 748 aprint_normal_dev(self, "Port Version 0x%x\n", sc->sc_version); 749 } 750 751 if (sc->sc_version >= 0x10) { 752 /* 753 * Armada XP 754 */ 755 756 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 757 MVGBE_PS0, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 758 aprint_error_dev(self, "Cannot map linkup register\n"); 759 return; 760 } 761 sc->sc_linkup.bit = MVGBE_PS0_LINKUP; 762 csc->sc_flags |= FLAGS_IPG2; 763 } else { 764 if (bus_space_subregion(mva->mva_iot, sc->sc_ioh, 765 MVGBE_PS, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 766 aprint_error_dev(self, "Cannot map linkup register\n"); 767 return; 768 } 769 sc->sc_linkup.bit = MVGBE_PS_LINKUP; 770 } 771 772 if (enaddrp) { 773 memcpy(enaddr, prop_data_data_nocopy(enaddrp), ETHER_ADDR_LEN); 774 maddrh = enaddr[0] << 24; 775 maddrh |= enaddr[1] << 16; 776 maddrh |= enaddr[2] << 8; 777 maddrh |= enaddr[3]; 778 maddrl = enaddr[4] << 8; 779 maddrl |= enaddr[5]; 780 MVGBE_WRITE(sc, MVGBE_MACAH, maddrh); 781 MVGBE_WRITE(sc, MVGBE_MACAL, maddrl); 782 } 783 784 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 785 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 786 sc->sc_enaddr[0] = maddrh >> 24; 787 sc->sc_enaddr[1] = maddrh >> 16; 788 sc->sc_enaddr[2] = maddrh >> 8; 789 sc->sc_enaddr[3] = maddrh >> 0; 790 sc->sc_enaddr[4] = maddrl >> 8; 791 sc->sc_enaddr[5] = maddrl >> 0; 792 aprint_normal_dev(self, "Ethernet address %s\n", 793 ether_sprintf(sc->sc_enaddr)); 794 795 /* clear all ethernet port interrupts */ 796 MVGBE_WRITE(sc, MVGBE_IC, 0); 797 MVGBE_WRITE(sc, MVGBE_ICE, 0); 798 799 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 800 801 /* Allocate the descriptor queues. */ 802 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 803 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 804 aprint_error_dev(self, "can't alloc rx buffers\n"); 805 return; 806 } 807 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 808 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 809 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 810 (u_long)sizeof(struct mvgbe_ring_data)); 811 goto fail1; 812 } 813 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 814 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 815 &sc->sc_ring_map)) { 816 aprint_error_dev(self, "can't create dma map\n"); 817 goto fail2; 818 } 819 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 820 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 821 aprint_error_dev(self, "can't load dma map\n"); 822 goto fail3; 823 } 824 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 825 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 826 827 SIMPLEQ_INIT(&sc->sc_txmap_head); 828 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 829 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 830 831 if (bus_dmamap_create(sc->sc_dmat, 832 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 833 BUS_DMA_NOWAIT, &dmamap)) { 834 aprint_error_dev(self, "Can't create TX dmamap\n"); 835 goto fail4; 836 } 837 838 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 839 entry->dmamap = dmamap; 840 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 841 } 842 843 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 844 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 845 846 /* 847 * We can support 802.1Q VLAN-sized frames and jumbo 848 * Ethernet frames. 849 */ 850 sc->sc_ethercom.ec_capabilities |= 851 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 852 853 /* Try to allocate memory for jumbo buffers. */ 854 if (mvgbe_alloc_jumbo_mem(sc)) { 855 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 856 goto fail4; 857 } 858 859 ifp = &sc->sc_ethercom.ec_if; 860 ifp->if_softc = sc; 861 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 862 ifp->if_start = mvgbe_start; 863 ifp->if_ioctl = mvgbe_ioctl; 864 ifp->if_init = mvgbe_init; 865 ifp->if_stop = mvgbe_stop; 866 ifp->if_watchdog = mvgbe_watchdog; 867 /* 868 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 869 */ 870 sc->sc_ethercom.ec_if.if_capabilities |= 871 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 872 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 873 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 874 /* 875 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 876 */ 877 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 878 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 879 IFQ_SET_READY(&ifp->if_snd); 880 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 881 882 mvgbe_stop(ifp, 0); 883 884 /* 885 * Do MII setup. 886 */ 887 sc->sc_mii.mii_ifp = ifp; 888 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 889 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 890 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 891 892 sc->sc_ethercom.ec_mii = &sc->sc_mii; 893 ifmedia_init(&sc->sc_mii.mii_media, 0, 894 mvgbe_mediachange, mvgbe_mediastatus); 895 mii_attach(self, &sc->sc_mii, 0xffffffff, 896 MII_PHY_ANY, parent == mvgbec0 ? 0 : 1, 0); 897 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 898 aprint_error_dev(self, "no PHY found!\n"); 899 ifmedia_add(&sc->sc_mii.mii_media, 900 IFM_ETHER|IFM_MANUAL, 0, NULL); 901 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 902 } else 903 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 904 905 /* 906 * Call MI attach routines. 907 */ 908 if_attach(ifp); 909 if_deferred_start_init(ifp, NULL); 910 911 ether_ifattach(ifp, sc->sc_enaddr); 912 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 913 914 sysctl_mvgbe_init(sc); 915 #ifdef MVGBE_EVENT_COUNTERS 916 /* Attach event counters. */ 917 evcnt_attach_dynamic(&sc->sc_ev_rxoverrun, EVCNT_TYPE_MISC, 918 NULL, device_xname(sc->sc_dev), "rxoverrrun"); 919 evcnt_attach_dynamic(&sc->sc_ev_wdogsoft, EVCNT_TYPE_MISC, 920 NULL, device_xname(sc->sc_dev), "wdogsoft"); 921 #endif 922 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 923 RND_TYPE_NET, RND_FLAG_DEFAULT); 924 925 return; 926 927 fail4: 928 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 929 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 930 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 931 } 932 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 933 fail3: 934 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 935 fail2: 936 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 937 fail1: 938 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 939 return; 940 } 941 942 static int 943 mvgbe_ipginttx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 944 unsigned int ipginttx) 945 { 946 uint32_t reg; 947 reg = MVGBE_READ(sc, MVGBE_PTFUT); 948 949 if (csc->sc_flags & FLAGS_IPG2) { 950 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V2_MAX) 951 return -1; 952 reg &= ~MVGBE_PTFUT_IPGINTTX_V2_MASK; 953 reg |= MVGBE_PTFUT_IPGINTTX_V2(ipginttx); 954 } else if (csc->sc_flags & FLAGS_IPG1) { 955 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V1_MAX) 956 return -1; 957 reg &= ~MVGBE_PTFUT_IPGINTTX_V1_MASK; 958 reg |= MVGBE_PTFUT_IPGINTTX_V1(ipginttx); 959 } 960 MVGBE_WRITE(sc, MVGBE_PTFUT, reg); 961 962 return 0; 963 } 964 965 static int 966 mvgbe_ipgintrx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 967 unsigned int ipgintrx) 968 { 969 uint32_t reg; 970 reg = MVGBE_READ(sc, MVGBE_SDC); 971 972 if (csc->sc_flags & FLAGS_IPG2) { 973 if (ipgintrx > MVGBE_SDC_IPGINTRX_V2_MAX) 974 return -1; 975 reg &= ~MVGBE_SDC_IPGINTRX_V2_MASK; 976 reg |= MVGBE_SDC_IPGINTRX_V2(ipgintrx); 977 } else if (csc->sc_flags & FLAGS_IPG1) { 978 if (ipgintrx > MVGBE_SDC_IPGINTRX_V1_MAX) 979 return -1; 980 reg &= ~MVGBE_SDC_IPGINTRX_V1_MASK; 981 reg |= MVGBE_SDC_IPGINTRX_V1(ipgintrx); 982 } 983 MVGBE_WRITE(sc, MVGBE_SDC, reg); 984 985 return 0; 986 } 987 988 static void 989 mvgbe_tick(void *arg) 990 { 991 struct mvgbe_softc *sc = arg; 992 struct mii_data *mii = &sc->sc_mii; 993 int s; 994 995 s = splnet(); 996 mii_tick(mii); 997 /* Need more work */ 998 MVGBE_EVCNT_ADD(&sc->sc_ev_rxoverrun, MVGBE_READ(sc, MVGBE_POFC)); 999 splx(s); 1000 1001 callout_schedule(&sc->sc_tick_ch, hz); 1002 } 1003 1004 static int 1005 mvgbe_intr(void *arg) 1006 { 1007 struct mvgbe_softc *sc = arg; 1008 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1009 uint32_t ic, ice, datum = 0; 1010 int claimed = 0; 1011 1012 for (;;) { 1013 ice = MVGBE_READ(sc, MVGBE_ICE); 1014 ic = MVGBE_READ(sc, MVGBE_IC); 1015 1016 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 1017 if (ic == 0 && ice == 0) 1018 break; 1019 1020 datum = datum ^ ic ^ ice; 1021 1022 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 1023 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 1024 1025 claimed = 1; 1026 1027 if (!(ifp->if_flags & IFF_RUNNING)) 1028 break; 1029 1030 if (ice & MVGBE_ICE_LINKCHG) { 1031 if (MVGBE_IS_LINKUP(sc)) { 1032 /* Enable port RX and TX. */ 1033 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1034 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1035 } else { 1036 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 1037 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1038 } 1039 1040 /* Notify link change event to mii layer */ 1041 mii_pollstat(&sc->sc_mii); 1042 } 1043 1044 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 1045 mvgbe_rxeof(sc); 1046 1047 if (ice & (MVGBE_ICE_TXBUF_MASK | MVGBE_ICE_TXERR_MASK)) 1048 mvgbe_txeof(sc); 1049 } 1050 1051 if_schedule_deferred_start(ifp); 1052 1053 rnd_add_uint32(&sc->sc_rnd_source, datum); 1054 1055 return claimed; 1056 } 1057 1058 static void 1059 mvgbe_start(struct ifnet *ifp) 1060 { 1061 struct mvgbe_softc *sc = ifp->if_softc; 1062 struct mbuf *m_head = NULL; 1063 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 1064 int pkts = 0; 1065 1066 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 1067 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 1068 1069 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1070 return; 1071 /* If Link is DOWN, can't start TX */ 1072 if (!MVGBE_IS_LINKUP(sc)) 1073 return; 1074 1075 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 1076 IFQ_POLL(&ifp->if_snd, m_head); 1077 if (m_head == NULL) 1078 break; 1079 1080 /* 1081 * Pack the data into the transmit ring. If we 1082 * don't have room, set the OACTIVE flag and wait 1083 * for the NIC to drain the ring. 1084 */ 1085 if (mvgbe_encap(sc, m_head, &idx)) { 1086 if (sc->sc_cdata.mvgbe_tx_cnt > 0) 1087 ifp->if_flags |= IFF_OACTIVE; 1088 break; 1089 } 1090 1091 /* now we are committed to transmit the packet */ 1092 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1093 pkts++; 1094 1095 /* 1096 * If there's a BPF listener, bounce a copy of this frame 1097 * to him. 1098 */ 1099 bpf_mtap(ifp, m_head, BPF_D_OUT); 1100 } 1101 if (pkts == 0) 1102 return; 1103 1104 /* Transmit at Queue 0 */ 1105 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 1106 sc->sc_cdata.mvgbe_tx_prod = idx; 1107 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1108 1109 /* 1110 * Set a timeout in case the chip goes out to lunch. 1111 */ 1112 ifp->if_timer = 1; 1113 sc->sc_wdogsoft = 1; 1114 } 1115 } 1116 1117 static int 1118 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1119 { 1120 struct mvgbe_softc *sc = ifp->if_softc; 1121 struct ifreq *ifr = data; 1122 int s, error = 0; 1123 1124 s = splnet(); 1125 1126 switch (cmd) { 1127 case SIOCGIFMEDIA: 1128 case SIOCSIFMEDIA: 1129 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 1130 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1131 break; 1132 default: 1133 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 1134 error = ether_ioctl(ifp, cmd, data); 1135 if (error == ENETRESET) { 1136 if (ifp->if_flags & IFF_RUNNING) { 1137 mvgbe_filter_setup(sc); 1138 } 1139 error = 0; 1140 } 1141 break; 1142 } 1143 1144 splx(s); 1145 1146 return error; 1147 } 1148 1149 static int 1150 mvgbe_init(struct ifnet *ifp) 1151 { 1152 struct mvgbe_softc *sc = ifp->if_softc; 1153 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1154 struct mii_data *mii = &sc->sc_mii; 1155 uint32_t reg; 1156 int i; 1157 1158 DPRINTFN(2, ("mvgbe_init\n")); 1159 1160 /* Cancel pending I/O and free all RX/TX buffers. */ 1161 mvgbe_stop(ifp, 0); 1162 1163 /* clear all ethernet port interrupts */ 1164 MVGBE_WRITE(sc, MVGBE_IC, 0); 1165 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1166 1167 /* Init TX/RX descriptors */ 1168 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 1169 aprint_error_ifnet(ifp, 1170 "initialization failed: no memory for tx buffers\n"); 1171 return ENOBUFS; 1172 } 1173 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 1174 aprint_error_ifnet(ifp, 1175 "initialization failed: no memory for rx buffers\n"); 1176 return ENOBUFS; 1177 } 1178 1179 if ((csc->sc_flags & FLAGS_IPG1) || (csc->sc_flags & FLAGS_IPG2)) { 1180 sc->sc_ipginttx = MVGBE_IPGINTTX_DEFAULT; 1181 sc->sc_ipgintrx = MVGBE_IPGINTRX_DEFAULT; 1182 } 1183 if (csc->sc_flags & FLAGS_FIX_MTU) 1184 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */ 1185 if (sc->sc_version >= 0x10) { 1186 MVGBE_WRITE(csc, MVGBE_PANC, 1187 MVGBE_PANC_FORCELINKPASS | 1188 MVGBE_PANC_INBANDANBYPASSEN | 1189 MVGBE_PANC_SETMIISPEED | 1190 MVGBE_PANC_SETGMIISPEED | 1191 MVGBE_PANC_ANSPEEDEN | 1192 MVGBE_PANC_SETFCEN | 1193 MVGBE_PANC_PAUSEADV | 1194 MVGBE_PANC_SETFULLDX | 1195 MVGBE_PANC_ANDUPLEXEN | 1196 MVGBE_PANC_RESERVED); 1197 MVGBE_WRITE(csc, MVGBE_PMACC0, 1198 MVGBE_PMACC0_RESERVED | 1199 MVGBE_PMACC0_FRAMESIZELIMIT(1600)); 1200 reg = MVGBE_READ(csc, MVGBE_PMACC2); 1201 reg &= MVGBE_PMACC2_PCSEN; /* keep PCSEN bit */ 1202 MVGBE_WRITE(csc, MVGBE_PMACC2, 1203 reg | MVGBE_PMACC2_RESERVED | MVGBE_PMACC2_RGMIIEN); 1204 1205 MVGBE_WRITE(sc, MVGBE_PXCX, 1206 MVGBE_READ(sc, MVGBE_PXCX) & ~MVGBE_PXCX_TXCRCDIS); 1207 1208 #ifndef MULTIPROCESSOR 1209 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_BM); 1210 #else 1211 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM); 1212 #endif 1213 } else { 1214 MVGBE_WRITE(sc, MVGBE_PSC, 1215 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 1216 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 1217 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 1218 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 1219 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 1220 /* XXXX: mvgbe(4) always use RGMII. */ 1221 MVGBE_WRITE(sc, MVGBE_PSC1, 1222 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 1223 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 1224 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 1225 1226 sc->sc_cmdsts_opts = MVGBE_TX_GENERATE_CRC; 1227 } 1228 1229 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 1230 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 1231 1232 if (csc->sc_flags & FLAGS_FIX_TQTB) { 1233 /* 1234 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1235 * And offset 0x72704 must be programmed to 0x03ffffff. 1236 * Queue 1 through 7 must be programmed to 0x0. 1237 */ 1238 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1239 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1240 for (i = 1; i < 8; i++) { 1241 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1242 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1243 } 1244 } else if (sc->sc_version < 0x10) 1245 for (i = 1; i < 8; i++) { 1246 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1247 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1248 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1249 } 1250 1251 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1252 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1253 1254 /* Set SDC register except IPGINT bits */ 1255 MVGBE_WRITE(sc, MVGBE_SDC, 1256 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1257 #if BYTE_ORDER == LITTLE_ENDIAN 1258 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1259 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1260 #endif 1261 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1262 /* And then set IPGINT bits */ 1263 mvgbe_ipgintrx(csc, sc, sc->sc_ipgintrx); 1264 1265 /* Tx side */ 1266 MVGBE_WRITE(sc, MVGBE_PTFUT, 0); 1267 mvgbe_ipginttx(csc, sc, sc->sc_ipginttx); 1268 1269 mvgbe_filter_setup(sc); 1270 1271 mii_mediachg(mii); 1272 1273 /* Enable port */ 1274 if (sc->sc_version >= 0x10) { 1275 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1276 MVGBE_WRITE(csc, MVGBE_PMACC0, reg | MVGBE_PMACC0_PORTEN); 1277 } else { 1278 reg = MVGBE_READ(sc, MVGBE_PSC); 1279 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1280 } 1281 1282 /* If Link is UP, Start RX and TX traffic */ 1283 if (MVGBE_IS_LINKUP(sc)) { 1284 /* Enable port RX/TX. */ 1285 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1286 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1287 } 1288 1289 /* Enable interrupt masks */ 1290 MVGBE_WRITE(sc, MVGBE_PIM, 1291 MVGBE_IC_RXBUF | 1292 MVGBE_IC_EXTEND | 1293 MVGBE_IC_RXBUFQ_MASK | 1294 MVGBE_IC_RXERROR | 1295 MVGBE_IC_RXERRQ_MASK); 1296 MVGBE_WRITE(sc, MVGBE_PEIM, 1297 MVGBE_ICE_TXBUF_MASK | 1298 MVGBE_ICE_TXERR_MASK | 1299 MVGBE_ICE_LINKCHG); 1300 1301 callout_schedule(&sc->sc_tick_ch, hz); 1302 1303 ifp->if_flags |= IFF_RUNNING; 1304 ifp->if_flags &= ~IFF_OACTIVE; 1305 1306 return 0; 1307 } 1308 1309 /* ARGSUSED */ 1310 static void 1311 mvgbe_stop(struct ifnet *ifp, int disable) 1312 { 1313 struct mvgbe_softc *sc = ifp->if_softc; 1314 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1315 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1316 uint32_t reg, txinprog, txfifoemp; 1317 int i, cnt; 1318 1319 DPRINTFN(2, ("mvgbe_stop\n")); 1320 1321 callout_stop(&sc->sc_tick_ch); 1322 1323 /* Stop Rx port activity. Check port Rx activity. */ 1324 reg = MVGBE_READ(sc, MVGBE_RQC); 1325 if (reg & MVGBE_RQC_ENQ_MASK) 1326 /* Issue stop command for active channels only */ 1327 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1328 1329 /* Stop Tx port activity. Check port Tx activity. */ 1330 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ(0)) 1331 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1332 1333 /* Force link down */ 1334 if (sc->sc_version >= 0x10) { 1335 reg = MVGBE_READ(csc, MVGBE_PANC); 1336 MVGBE_WRITE(csc, MVGBE_PANC, reg | MVGBE_PANC_FORCELINKFAIL); 1337 1338 txinprog = MVGBE_PS_TXINPROG_(0); 1339 txfifoemp = MVGBE_PS_TXFIFOEMP_(0); 1340 } else { 1341 reg = MVGBE_READ(sc, MVGBE_PSC); 1342 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1343 1344 txinprog = MVGBE_PS_TXINPROG; 1345 txfifoemp = MVGBE_PS_TXFIFOEMP; 1346 } 1347 1348 #define RX_DISABLE_TIMEOUT 0x1000000 1349 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1350 /* Wait for all Rx activity to terminate. */ 1351 cnt = 0; 1352 do { 1353 if (cnt >= RX_DISABLE_TIMEOUT) { 1354 aprint_error_ifnet(ifp, 1355 "timeout for RX stopped. rqc 0x%x\n", reg); 1356 break; 1357 } 1358 cnt++; 1359 1360 /* 1361 * Check Receive Queue Command register that all Rx queues 1362 * are stopped 1363 */ 1364 reg = MVGBE_READ(sc, MVGBE_RQC); 1365 } while (reg & 0xff); 1366 1367 /* Double check to verify that TX FIFO is empty */ 1368 cnt = 0; 1369 while (1) { 1370 do { 1371 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1372 aprint_error_ifnet(ifp, 1373 "timeout for TX FIFO empty. status 0x%x\n", 1374 reg); 1375 break; 1376 } 1377 cnt++; 1378 1379 reg = MVGBE_READ(sc, MVGBE_PS); 1380 } while (!(reg & txfifoemp) || reg & txinprog); 1381 1382 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1383 break; 1384 1385 /* Double check */ 1386 reg = MVGBE_READ(sc, MVGBE_PS); 1387 if (reg & txfifoemp && !(reg & txinprog)) 1388 break; 1389 else 1390 aprint_error_ifnet(ifp, 1391 "TX FIFO empty double check failed." 1392 " %d loops, status 0x%x\n", cnt, reg); 1393 } 1394 1395 /* Reset the Enable bit */ 1396 if (sc->sc_version >= 0x10) { 1397 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1398 MVGBE_WRITE(csc, MVGBE_PMACC0, reg & ~MVGBE_PMACC0_PORTEN); 1399 } else { 1400 reg = MVGBE_READ(sc, MVGBE_PSC); 1401 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1402 } 1403 1404 /* 1405 * Disable and clear interrupts 1406 * 0) controller interrupt 1407 * 1) port interrupt cause 1408 * 2) port interrupt mask 1409 */ 1410 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 1411 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 1412 MVGBE_WRITE(sc, MVGBE_IC, 0); 1413 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1414 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1415 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1416 1417 /* Free RX and TX mbufs still in the queues. */ 1418 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1419 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1420 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1421 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1422 } 1423 } 1424 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1425 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1426 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1427 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1428 } 1429 } 1430 1431 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1432 } 1433 1434 static void 1435 mvgbe_watchdog(struct ifnet *ifp) 1436 { 1437 struct mvgbe_softc *sc = ifp->if_softc; 1438 1439 /* 1440 * Reclaim first as there is a possibility of losing Tx completion 1441 * interrupts. 1442 */ 1443 mvgbe_txeof(sc); 1444 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1445 if (sc->sc_wdogsoft) { 1446 /* 1447 * There is race condition between CPU and DMA 1448 * engine. When DMA engine encounters queue end, 1449 * it clears MVGBE_TQC_ENQ bit. 1450 */ 1451 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1452 ifp->if_timer = 5; 1453 sc->sc_wdogsoft = 0; 1454 MVGBE_EVCNT_INCR(&sc->sc_ev_wdogsoft); 1455 } else { 1456 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1457 1458 ifp->if_oerrors++; 1459 1460 mvgbe_init(ifp); 1461 } 1462 } 1463 } 1464 1465 static int 1466 mvgbe_ifflags_cb(struct ethercom *ec) 1467 { 1468 struct ifnet *ifp = &ec->ec_if; 1469 struct mvgbe_softc *sc = ifp->if_softc; 1470 int change = ifp->if_flags ^ sc->sc_if_flags; 1471 1472 if (change != 0) 1473 sc->sc_if_flags = ifp->if_flags; 1474 1475 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1476 return ENETRESET; 1477 1478 if ((change & IFF_PROMISC) != 0) 1479 mvgbe_filter_setup(sc); 1480 1481 return 0; 1482 } 1483 1484 /* 1485 * Set media options. 1486 */ 1487 static int 1488 mvgbe_mediachange(struct ifnet *ifp) 1489 { 1490 return ether_mediachange(ifp); 1491 } 1492 1493 /* 1494 * Report current media status. 1495 */ 1496 static void 1497 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1498 { 1499 ether_mediastatus(ifp, ifmr); 1500 } 1501 1502 1503 static int 1504 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1505 { 1506 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1507 struct mvgbe_ring_data *rd = sc->sc_rdata; 1508 int i; 1509 1510 memset(rd->mvgbe_rx_ring, 0, 1511 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1512 1513 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1514 cd->mvgbe_rx_chain[i].mvgbe_desc = 1515 &rd->mvgbe_rx_ring[i]; 1516 if (i == MVGBE_RX_RING_CNT - 1) { 1517 cd->mvgbe_rx_chain[i].mvgbe_next = 1518 &cd->mvgbe_rx_chain[0]; 1519 rd->mvgbe_rx_ring[i].nextdescptr = 1520 MVGBE_RX_RING_ADDR(sc, 0); 1521 } else { 1522 cd->mvgbe_rx_chain[i].mvgbe_next = 1523 &cd->mvgbe_rx_chain[i + 1]; 1524 rd->mvgbe_rx_ring[i].nextdescptr = 1525 MVGBE_RX_RING_ADDR(sc, i + 1); 1526 } 1527 } 1528 1529 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1530 if (mvgbe_newbuf(sc, i, NULL, 1531 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1532 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1533 "failed alloc of %dth mbuf\n", i); 1534 return ENOBUFS; 1535 } 1536 } 1537 sc->sc_cdata.mvgbe_rx_prod = 0; 1538 sc->sc_cdata.mvgbe_rx_cons = 0; 1539 1540 return 0; 1541 } 1542 1543 static int 1544 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1545 { 1546 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1547 struct mvgbe_ring_data *rd = sc->sc_rdata; 1548 int i; 1549 1550 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1551 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1552 1553 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1554 cd->mvgbe_tx_chain[i].mvgbe_desc = 1555 &rd->mvgbe_tx_ring[i]; 1556 if (i == MVGBE_TX_RING_CNT - 1) { 1557 cd->mvgbe_tx_chain[i].mvgbe_next = 1558 &cd->mvgbe_tx_chain[0]; 1559 rd->mvgbe_tx_ring[i].nextdescptr = 1560 MVGBE_TX_RING_ADDR(sc, 0); 1561 } else { 1562 cd->mvgbe_tx_chain[i].mvgbe_next = 1563 &cd->mvgbe_tx_chain[i + 1]; 1564 rd->mvgbe_tx_ring[i].nextdescptr = 1565 MVGBE_TX_RING_ADDR(sc, i + 1); 1566 } 1567 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1568 } 1569 1570 sc->sc_cdata.mvgbe_tx_prod = 0; 1571 sc->sc_cdata.mvgbe_tx_cons = 0; 1572 sc->sc_cdata.mvgbe_tx_cnt = 0; 1573 1574 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1575 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1576 1577 return 0; 1578 } 1579 1580 static int 1581 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1582 bus_dmamap_t dmamap) 1583 { 1584 struct mbuf *m_new = NULL; 1585 struct mvgbe_chain *c; 1586 struct mvgbe_rx_desc *r; 1587 int align; 1588 vaddr_t offset; 1589 1590 if (m == NULL) { 1591 void *buf = NULL; 1592 1593 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1594 if (m_new == NULL) { 1595 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1596 "no memory for rx list -- packet dropped!\n"); 1597 return ENOBUFS; 1598 } 1599 1600 /* Allocate the jumbo buffer */ 1601 buf = mvgbe_jalloc(sc); 1602 if (buf == NULL) { 1603 m_freem(m_new); 1604 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1605 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1606 return ENOBUFS; 1607 } 1608 1609 /* Attach the buffer to the mbuf */ 1610 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1611 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1612 } else { 1613 /* 1614 * We're re-using a previously allocated mbuf; 1615 * be sure to re-init pointers and lengths to 1616 * default values. 1617 */ 1618 m_new = m; 1619 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1620 m_new->m_data = m_new->m_ext.ext_buf; 1621 } 1622 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1623 if (align != 0) { 1624 DPRINTFN(1,("align = %d\n", align)); 1625 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1626 } 1627 1628 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1629 r = c->mvgbe_desc; 1630 c->mvgbe_mbuf = m_new; 1631 offset = (vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf; 1632 r->bufptr = dmamap->dm_segs[0].ds_addr + offset; 1633 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1634 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1635 1636 /* Invalidate RX buffer */ 1637 bus_dmamap_sync(sc->sc_dmat, dmamap, offset, r->bufsize, 1638 BUS_DMASYNC_PREREAD); 1639 1640 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1641 1642 return 0; 1643 } 1644 1645 /* 1646 * Memory management for jumbo frames. 1647 */ 1648 1649 static int 1650 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1651 { 1652 char *ptr, *kva; 1653 bus_dma_segment_t seg; 1654 int i, rseg, state, error; 1655 struct mvgbe_jpool_entry *entry; 1656 1657 state = error = 0; 1658 1659 /* Grab a big chunk o' storage. */ 1660 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1661 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1662 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1663 return ENOBUFS; 1664 } 1665 1666 state = 1; 1667 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1668 (void **)&kva, BUS_DMA_NOWAIT)) { 1669 aprint_error_dev(sc->sc_dev, 1670 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1671 error = ENOBUFS; 1672 goto out; 1673 } 1674 1675 state = 2; 1676 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1677 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1678 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1679 error = ENOBUFS; 1680 goto out; 1681 } 1682 1683 state = 3; 1684 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1685 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1686 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1687 error = ENOBUFS; 1688 goto out; 1689 } 1690 1691 state = 4; 1692 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1693 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1694 1695 LIST_INIT(&sc->sc_jfree_listhead); 1696 LIST_INIT(&sc->sc_jinuse_listhead); 1697 1698 /* 1699 * Now divide it up into 9K pieces and save the addresses 1700 * in an array. 1701 */ 1702 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1703 for (i = 0; i < MVGBE_JSLOTS; i++) { 1704 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1705 ptr += MVGBE_JLEN; 1706 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1707 entry->slot = i; 1708 if (i) 1709 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1710 jpool_entries); 1711 else 1712 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1713 jpool_entries); 1714 } 1715 out: 1716 if (error != 0) { 1717 switch (state) { 1718 case 4: 1719 bus_dmamap_unload(sc->sc_dmat, 1720 sc->sc_cdata.mvgbe_rx_jumbo_map); 1721 case 3: 1722 bus_dmamap_destroy(sc->sc_dmat, 1723 sc->sc_cdata.mvgbe_rx_jumbo_map); 1724 case 2: 1725 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1726 case 1: 1727 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1728 break; 1729 default: 1730 break; 1731 } 1732 } 1733 1734 return error; 1735 } 1736 1737 /* 1738 * Allocate a jumbo buffer. 1739 */ 1740 static void * 1741 mvgbe_jalloc(struct mvgbe_softc *sc) 1742 { 1743 struct mvgbe_jpool_entry *entry; 1744 1745 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1746 1747 if (entry == NULL) 1748 return NULL; 1749 1750 LIST_REMOVE(entry, jpool_entries); 1751 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1752 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1753 } 1754 1755 /* 1756 * Release a jumbo buffer. 1757 */ 1758 static void 1759 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1760 { 1761 struct mvgbe_jpool_entry *entry; 1762 struct mvgbe_softc *sc; 1763 int i, s; 1764 1765 /* Extract the softc struct pointer. */ 1766 sc = (struct mvgbe_softc *)arg; 1767 1768 if (sc == NULL) 1769 panic("%s: can't find softc pointer!", __func__); 1770 1771 /* calculate the slot this buffer belongs to */ 1772 1773 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1774 1775 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1776 panic("%s: asked to free buffer that we don't manage!", 1777 __func__); 1778 1779 s = splvm(); 1780 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1781 if (entry == NULL) 1782 panic("%s: buffer not in use!", __func__); 1783 entry->slot = i; 1784 LIST_REMOVE(entry, jpool_entries); 1785 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1786 1787 if (__predict_true(m != NULL)) 1788 pool_cache_put(mb_cache, m); 1789 splx(s); 1790 } 1791 1792 static int 1793 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1794 uint32_t *txidx) 1795 { 1796 struct mvgbe_tx_desc *f = NULL; 1797 struct mvgbe_txmap_entry *entry; 1798 bus_dma_segment_t *txseg; 1799 bus_dmamap_t txmap; 1800 uint32_t first, current, last, cmdsts; 1801 int m_csumflags, i; 1802 bool needs_defrag = false; 1803 1804 DPRINTFN(3, ("mvgbe_encap\n")); 1805 1806 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1807 if (entry == NULL) { 1808 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1809 return ENOBUFS; 1810 } 1811 txmap = entry->dmamap; 1812 1813 first = current = last = *txidx; 1814 1815 /* 1816 * Preserve m_pkthdr.csum_flags here since m_head might be 1817 * updated by m_defrag() 1818 */ 1819 m_csumflags = m_head->m_pkthdr.csum_flags; 1820 1821 do_defrag: 1822 if (__predict_false(needs_defrag == true)) { 1823 /* A small unaligned segment was detected. */ 1824 struct mbuf *m_new; 1825 m_new = m_defrag(m_head, M_DONTWAIT); 1826 if (m_new == NULL) 1827 return EFBIG; 1828 m_head = m_new; 1829 } 1830 1831 /* 1832 * Start packing the mbufs in this chain into 1833 * the fragment pointers. Stop when we run out 1834 * of fragments or hit the end of the mbuf chain. 1835 */ 1836 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1837 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1838 return ENOBUFS; 1839 } 1840 1841 txseg = txmap->dm_segs; 1842 1843 if (__predict_true(needs_defrag == false)) { 1844 /* 1845 * Detect rarely encountered DMA limitation. 1846 */ 1847 for (i = 0; i < txmap->dm_nsegs; i++) { 1848 if (((txseg[i].ds_addr & 7) != 0) && 1849 (txseg[i].ds_len <= 8) && 1850 (txseg[i].ds_len >= 1) 1851 ) { 1852 txseg = NULL; 1853 bus_dmamap_unload(sc->sc_dmat, txmap); 1854 needs_defrag = true; 1855 goto do_defrag; 1856 } 1857 } 1858 } 1859 1860 /* Sync the DMA map. */ 1861 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1862 BUS_DMASYNC_PREWRITE); 1863 1864 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1865 MVGBE_TX_RING_CNT) { 1866 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1867 bus_dmamap_unload(sc->sc_dmat, txmap); 1868 return ENOBUFS; 1869 } 1870 1871 1872 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1873 1874 for (i = 0; i < txmap->dm_nsegs; i++) { 1875 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1876 f->bufptr = txseg[i].ds_addr; 1877 f->bytecnt = txseg[i].ds_len; 1878 if (i != 0) 1879 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1880 last = current; 1881 current = MVGBE_TX_RING_NEXT(current); 1882 } 1883 1884 cmdsts = sc->sc_cmdsts_opts; 1885 if (m_csumflags & M_CSUM_IPv4) 1886 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1887 if (m_csumflags & M_CSUM_TCPv4) 1888 cmdsts |= 1889 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1890 if (m_csumflags & M_CSUM_UDPv4) 1891 cmdsts |= 1892 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1893 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1894 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1895 1896 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1897 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1898 } 1899 if (txmap->dm_nsegs == 1) 1900 f->cmdsts = cmdsts | 1901 MVGBE_TX_ENABLE_INTERRUPT | 1902 MVGBE_TX_ZERO_PADDING | 1903 MVGBE_TX_FIRST_DESC | 1904 MVGBE_TX_LAST_DESC; 1905 else { 1906 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1907 f->cmdsts = cmdsts | MVGBE_TX_FIRST_DESC; 1908 1909 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1910 f->cmdsts = 1911 MVGBE_BUFFER_OWNED_BY_DMA | 1912 MVGBE_TX_ENABLE_INTERRUPT | 1913 MVGBE_TX_ZERO_PADDING | 1914 MVGBE_TX_LAST_DESC; 1915 1916 /* Sync descriptors except first */ 1917 MVGBE_CDTXSYNC(sc, 1918 (MVGBE_TX_RING_CNT - 1 == *txidx) ? 0 : (*txidx) + 1, 1919 txmap->dm_nsegs - 1, 1920 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1921 } 1922 1923 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1924 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1925 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1926 1927 /* Finally, sync first descriptor */ 1928 sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |= 1929 MVGBE_BUFFER_OWNED_BY_DMA; 1930 MVGBE_CDTXSYNC(sc, *txidx, 1, 1931 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1932 1933 sc->sc_cdata.mvgbe_tx_cnt += i; 1934 *txidx = current; 1935 1936 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1937 1938 return 0; 1939 } 1940 1941 static void 1942 mvgbe_rxeof(struct mvgbe_softc *sc) 1943 { 1944 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1945 struct mvgbe_rx_desc *cur_rx; 1946 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1947 struct mbuf *m; 1948 bus_dmamap_t dmamap; 1949 uint32_t rxstat; 1950 uint16_t bufsize; 1951 int idx, cur, total_len; 1952 1953 idx = sc->sc_cdata.mvgbe_rx_prod; 1954 1955 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1956 1957 for (;;) { 1958 cur = idx; 1959 1960 /* Sync the descriptor */ 1961 MVGBE_CDRXSYNC(sc, idx, 1962 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1963 1964 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1965 1966 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1967 MVGBE_BUFFER_OWNED_BY_DMA) { 1968 /* Invalidate the descriptor -- it's not ready yet */ 1969 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1970 sc->sc_cdata.mvgbe_rx_prod = idx; 1971 break; 1972 } 1973 #ifdef DIAGNOSTIC 1974 if ((cur_rx->cmdsts & 1975 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1976 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1977 panic( 1978 "mvgbe_rxeof: buffer size is smaller than packet"); 1979 #endif 1980 1981 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1982 1983 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1984 BUS_DMASYNC_POSTREAD); 1985 1986 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1987 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1988 total_len = cur_rx->bytecnt - ETHER_CRC_LEN; 1989 rxstat = cur_rx->cmdsts; 1990 bufsize = cur_rx->bufsize; 1991 1992 cdata->mvgbe_rx_map[idx] = NULL; 1993 1994 idx = MVGBE_RX_RING_NEXT(idx); 1995 1996 if (rxstat & MVGBE_ERROR_SUMMARY) { 1997 #if 0 1998 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1999 2000 if (err == MVGBE_RX_CRC_ERROR) 2001 ifp->if_ierrors++; 2002 if (err == MVGBE_RX_OVERRUN_ERROR) 2003 ifp->if_ierrors++; 2004 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 2005 ifp->if_ierrors++; 2006 if (err == MVGBE_RX_RESOURCE_ERROR) 2007 ifp->if_ierrors++; 2008 #else 2009 ifp->if_ierrors++; 2010 #endif 2011 mvgbe_newbuf(sc, cur, m, dmamap); 2012 continue; 2013 } 2014 2015 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 2016 int flgs = 0; 2017 2018 /* Check IPv4 header checksum */ 2019 flgs |= M_CSUM_IPv4; 2020 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 2021 flgs |= M_CSUM_IPv4_BAD; 2022 else if ((bufsize & MVGBE_RX_IP_FRAGMENT) == 0) { 2023 /* 2024 * Check TCPv4/UDPv4 checksum for 2025 * non-fragmented packet only. 2026 * 2027 * It seemd that sometimes 2028 * MVGBE_RX_L4_CHECKSUM_OK bit was set to 0 2029 * even if the checksum is correct and the 2030 * packet was not fragmented. So we don't set 2031 * M_CSUM_TCP_UDP_BAD even if csum bit is 0. 2032 */ 2033 2034 if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2035 MVGBE_RX_L4_TYPE_TCP) && 2036 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2037 flgs |= M_CSUM_TCPv4; 2038 else if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2039 MVGBE_RX_L4_TYPE_UDP) && 2040 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2041 flgs |= M_CSUM_UDPv4; 2042 } 2043 m->m_pkthdr.csum_flags = flgs; 2044 } 2045 2046 /* 2047 * Try to allocate a new jumbo buffer. If that 2048 * fails, copy the packet to mbufs and put the 2049 * jumbo buffer back in the ring so it can be 2050 * re-used. If allocating mbufs fails, then we 2051 * have to drop the packet. 2052 */ 2053 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 2054 struct mbuf *m0; 2055 2056 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 2057 mvgbe_newbuf(sc, cur, m, dmamap); 2058 if (m0 == NULL) { 2059 aprint_error_ifnet(ifp, 2060 "no receive buffers available --" 2061 " packet dropped!\n"); 2062 ifp->if_ierrors++; 2063 continue; 2064 } 2065 m = m0; 2066 } else { 2067 m_set_rcvif(m, ifp); 2068 m->m_pkthdr.len = m->m_len = total_len; 2069 } 2070 2071 /* Skip on first 2byte (HW header) */ 2072 m_adj(m, MVGBE_HWHEADER_SIZE); 2073 2074 /* pass it on. */ 2075 if_percpuq_enqueue(ifp->if_percpuq, m); 2076 } 2077 } 2078 2079 static void 2080 mvgbe_txeof(struct mvgbe_softc *sc) 2081 { 2082 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 2083 struct mvgbe_tx_desc *cur_tx; 2084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2085 struct mvgbe_txmap_entry *entry; 2086 int idx; 2087 2088 DPRINTFN(3, ("mvgbe_txeof\n")); 2089 2090 /* 2091 * Go through our tx ring and free mbufs for those 2092 * frames that have been sent. 2093 */ 2094 idx = cdata->mvgbe_tx_cons; 2095 while (idx != cdata->mvgbe_tx_prod) { 2096 MVGBE_CDTXSYNC(sc, idx, 1, 2097 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2098 2099 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 2100 #ifdef MVGBE_DEBUG 2101 if (mvgbe_debug >= 3) 2102 mvgbe_dump_txdesc(cur_tx, idx); 2103 #endif 2104 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 2105 MVGBE_BUFFER_OWNED_BY_DMA) { 2106 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 2107 break; 2108 } 2109 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 2110 ifp->if_opackets++; 2111 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 2112 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 2113 2114 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 2115 ifp->if_collisions++; 2116 if (err == MVGBE_TX_UNDERRUN_ERROR) 2117 ifp->if_oerrors++; 2118 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 2119 ifp->if_collisions++; 2120 } 2121 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 2122 entry = cdata->mvgbe_tx_map[idx]; 2123 2124 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 2125 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 2126 2127 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 2128 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2129 2130 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 2131 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 2132 cdata->mvgbe_tx_map[idx] = NULL; 2133 } 2134 cdata->mvgbe_tx_cnt--; 2135 idx = MVGBE_TX_RING_NEXT(idx); 2136 } 2137 if (cdata->mvgbe_tx_cnt == 0) 2138 ifp->if_timer = 0; 2139 2140 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 2141 ifp->if_flags &= ~IFF_OACTIVE; 2142 2143 cdata->mvgbe_tx_cons = idx; 2144 } 2145 2146 static uint8_t 2147 mvgbe_crc8(const uint8_t *data, size_t size) 2148 { 2149 int bit; 2150 uint8_t byte; 2151 uint8_t crc = 0; 2152 const uint8_t poly = 0x07; 2153 2154 while(size--) 2155 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2156 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2157 2158 return crc; 2159 } 2160 2161 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 2162 2163 static void 2164 mvgbe_filter_setup(struct mvgbe_softc *sc) 2165 { 2166 struct ethercom *ec = &sc->sc_ethercom; 2167 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2168 struct ether_multi *enm; 2169 struct ether_multistep step; 2170 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT]; 2171 uint32_t pxc; 2172 int i; 2173 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2174 2175 memset(dfut, 0, sizeof(dfut)); 2176 memset(dfsmt, 0, sizeof(dfsmt)); 2177 memset(dfomt, 0, sizeof(dfomt)); 2178 2179 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2180 goto allmulti; 2181 } 2182 2183 ETHER_FIRST_MULTI(step, ec, enm); 2184 while (enm != NULL) { 2185 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2186 /* ranges are complex and somewhat rare */ 2187 goto allmulti; 2188 } 2189 /* chip handles some IPv4 multicast specially */ 2190 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2191 i = enm->enm_addrlo[5]; 2192 dfsmt[i>>2] |= 2193 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2194 } else { 2195 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2196 dfomt[i>>2] |= 2197 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2198 } 2199 2200 ETHER_NEXT_MULTI(step, enm); 2201 } 2202 goto set; 2203 2204 allmulti: 2205 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2206 for (i = 0; i < MVGBE_NDFSMT; i++) { 2207 dfsmt[i] = dfomt[i] = 2208 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2209 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2210 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2211 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2212 } 2213 } 2214 2215 set: 2216 pxc = MVGBE_READ(sc, MVGBE_PXC); 2217 pxc &= ~MVGBE_PXC_UPM; 2218 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 2219 if (ifp->if_flags & IFF_BROADCAST) { 2220 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 2221 } 2222 if (ifp->if_flags & IFF_PROMISC) { 2223 pxc |= MVGBE_PXC_UPM; 2224 } 2225 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 2226 2227 /* Set Destination Address Filter Unicast Table */ 2228 if (ifp->if_flags & IFF_PROMISC) { 2229 /* pass all unicast addresses */ 2230 for (i = 0; i < MVGBE_NDFUT; i++) { 2231 dfut[i] = 2232 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2233 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2234 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2235 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2236 } 2237 } else { 2238 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2239 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2240 } 2241 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 2242 2243 /* Set Destination Address Filter Multicast Tables */ 2244 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 2245 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 2246 } 2247 2248 #ifdef MVGBE_DEBUG 2249 static void 2250 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 2251 { 2252 #define DESC_PRINT(X) \ 2253 if (X) \ 2254 printf("txdesc[%d]." #X "=%#x\n", idx, X); 2255 2256 #if BYTE_ORDER == BIG_ENDIAN 2257 DESC_PRINT(desc->bytecnt); 2258 DESC_PRINT(desc->l4ichk); 2259 DESC_PRINT(desc->cmdsts); 2260 DESC_PRINT(desc->nextdescptr); 2261 DESC_PRINT(desc->bufptr); 2262 #else /* LITTLE_ENDIAN */ 2263 DESC_PRINT(desc->cmdsts); 2264 DESC_PRINT(desc->l4ichk); 2265 DESC_PRINT(desc->bytecnt); 2266 DESC_PRINT(desc->bufptr); 2267 DESC_PRINT(desc->nextdescptr); 2268 #endif 2269 #undef DESC_PRINT 2270 } 2271 #endif 2272 2273 SYSCTL_SETUP(sysctl_mvgbe, "sysctl mvgbe subtree setup") 2274 { 2275 int rc; 2276 const struct sysctlnode *node; 2277 2278 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2279 0, CTLTYPE_NODE, "mvgbe", 2280 SYSCTL_DESCR("mvgbe interface controls"), 2281 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2282 goto err; 2283 } 2284 2285 mvgbe_root_num = node->sysctl_num; 2286 return; 2287 2288 err: 2289 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2290 } 2291 2292 static void 2293 sysctl_mvgbe_init(struct mvgbe_softc *sc) 2294 { 2295 const struct sysctlnode *node; 2296 int mvgbe_nodenum; 2297 2298 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2299 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 2300 SYSCTL_DESCR("mvgbe per-controller controls"), 2301 NULL, 0, NULL, 0, CTL_HW, mvgbe_root_num, CTL_CREATE, 2302 CTL_EOL) != 0) { 2303 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 2304 return; 2305 } 2306 mvgbe_nodenum = node->sysctl_num; 2307 2308 /* interrupt moderation sysctls */ 2309 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2310 CTLFLAG_READWRITE, CTLTYPE_INT, "ipginttx", 2311 SYSCTL_DESCR("mvgbe TX interrupt moderation timer"), 2312 mvgbe_sysctl_ipginttx, 0, (void *)sc, 2313 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2314 CTL_EOL) != 0) { 2315 aprint_normal_dev(sc->sc_dev, 2316 "couldn't create ipginttx sysctl node\n"); 2317 } 2318 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2319 CTLFLAG_READWRITE, CTLTYPE_INT, "ipgintrx", 2320 SYSCTL_DESCR("mvgbe RX interrupt moderation timer"), 2321 mvgbe_sysctl_ipgintrx, 0, (void *)sc, 2322 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2323 CTL_EOL) != 0) { 2324 aprint_normal_dev(sc->sc_dev, 2325 "couldn't create ipginttx sysctl node\n"); 2326 } 2327 } 2328 2329 static int 2330 mvgbe_sysctl_ipginttx(SYSCTLFN_ARGS) 2331 { 2332 int error; 2333 unsigned int t; 2334 struct sysctlnode node; 2335 struct mvgbec_softc *csc; 2336 struct mvgbe_softc *sc; 2337 2338 node = *rnode; 2339 sc = node.sysctl_data; 2340 csc = device_private(device_parent(sc->sc_dev)); 2341 t = sc->sc_ipginttx; 2342 node.sysctl_data = &t; 2343 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2344 if (error || newp == NULL) 2345 return error; 2346 2347 if (mvgbe_ipginttx(csc, sc, t) < 0) 2348 return EINVAL; 2349 /* 2350 * update the softc with sysctl-changed value, and mark 2351 * for hardware update 2352 */ 2353 sc->sc_ipginttx = t; 2354 2355 return 0; 2356 } 2357 2358 static int 2359 mvgbe_sysctl_ipgintrx(SYSCTLFN_ARGS) 2360 { 2361 int error; 2362 unsigned int t; 2363 struct sysctlnode node; 2364 struct mvgbec_softc *csc; 2365 struct mvgbe_softc *sc; 2366 2367 node = *rnode; 2368 sc = node.sysctl_data; 2369 csc = device_private(device_parent(sc->sc_dev)); 2370 t = sc->sc_ipgintrx; 2371 node.sysctl_data = &t; 2372 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2373 if (error || newp == NULL) 2374 return error; 2375 2376 if (mvgbe_ipgintrx(csc, sc, t) < 0) 2377 return EINVAL; 2378 /* 2379 * update the softc with sysctl-changed value, and mark 2380 * for hardware update 2381 */ 2382 sc->sc_ipgintrx = t; 2383 2384 return 0; 2385 } 2386