1 /* $NetBSD: if_mvgbe.c,v 1.46 2016/12/08 01:12:01 ozaki-r Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.46 2016/12/08 01:12:01 ozaki-r Exp $"); 29 30 #include "opt_multiprocessor.h" 31 32 #if defined MULTIPROCESSOR 33 #warning Queue Management Method 'Counters' not support. Please use mvxpe instead of this. 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/callout.h> 39 #include <sys/device.h> 40 #include <sys/endian.h> 41 #include <sys/errno.h> 42 #include <sys/evcnt.h> 43 #include <sys/kernel.h> 44 #include <sys/kmem.h> 45 #include <sys/mutex.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/marvell/mvgbereg.h> 52 53 #include <net/if.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 61 #include <net/bpf.h> 62 #include <sys/rndsource.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include "locators.h" 68 69 /* #define MVGBE_DEBUG 3 */ 70 #ifdef MVGBE_DEBUG 71 #define DPRINTF(x) if (mvgbe_debug) printf x 72 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 73 int mvgbe_debug = MVGBE_DEBUG; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 80 #define MVGBE_READ(sc, reg) \ 81 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 82 #define MVGBE_WRITE(sc, reg, val) \ 83 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 84 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 85 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 86 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 87 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 88 89 #define MVGBE_LINKUP_READ(sc) \ 90 bus_space_read_4((sc)->sc_iot, (sc)->sc_linkup.ioh, 0) 91 #define MVGBE_IS_LINKUP(sc) (MVGBE_LINKUP_READ(sc) & (sc)->sc_linkup.bit) 92 93 #define MVGBE_TX_RING_CNT 256 94 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 95 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 96 #define MVGBE_RX_RING_CNT 256 97 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 98 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 99 100 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 101 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 102 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 103 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 104 105 #define MVGBE_JSLOTS 384 /* XXXX */ 106 #define MVGBE_JLEN \ 107 ((MVGBE_MRU + MVGBE_HWHEADER_SIZE + MVGBE_RXBUF_ALIGN - 1) & \ 108 ~MVGBE_RXBUF_MASK) 109 #define MVGBE_NTXSEG 30 110 #define MVGBE_JPAGESZ PAGE_SIZE 111 #define MVGBE_RESID \ 112 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 113 #define MVGBE_JMEM \ 114 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 115 116 #define MVGBE_TX_RING_ADDR(sc, i) \ 117 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 118 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 119 120 #define MVGBE_RX_RING_ADDR(sc, i) \ 121 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 122 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 123 124 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 125 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 126 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 127 128 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 129 do { \ 130 int __x, __n; \ 131 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 132 \ 133 __x = (x); \ 134 __n = (n); \ 135 \ 136 /* If it will wrap around, sync to the end of the ring. */ \ 137 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 138 bus_dmamap_sync((sc)->sc_dmat, \ 139 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 140 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 141 __n -= (MVGBE_TX_RING_CNT - __x); \ 142 __x = 0; \ 143 } \ 144 \ 145 /* Now sync whatever is left. */ \ 146 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 147 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 148 } while (0 /*CONSTCOND*/) 149 150 #define MVGBE_CDRXSYNC(sc, x, ops) \ 151 do { \ 152 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 153 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 154 } while (/*CONSTCOND*/0) 155 156 #define MVGBE_IPGINTTX_DEFAULT 768 157 #define MVGBE_IPGINTRX_DEFAULT 768 158 159 #ifdef MVGBE_EVENT_COUNTERS 160 #define MVGBE_EVCNT_INCR(ev) (ev)->ev_count++ 161 #define MVGBE_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 162 #else 163 #define MVGBE_EVCNT_INCR(ev) /* nothing */ 164 #define MVGBE_EVCNT_ADD(ev, val) /* nothing */ 165 #endif 166 167 struct mvgbe_jpool_entry { 168 int slot; 169 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 170 }; 171 172 struct mvgbe_chain { 173 void *mvgbe_desc; 174 struct mbuf *mvgbe_mbuf; 175 struct mvgbe_chain *mvgbe_next; 176 }; 177 178 struct mvgbe_txmap_entry { 179 bus_dmamap_t dmamap; 180 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 181 }; 182 183 struct mvgbe_chain_data { 184 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 185 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 186 int mvgbe_tx_prod; 187 int mvgbe_tx_cons; 188 int mvgbe_tx_cnt; 189 190 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 191 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 192 bus_dmamap_t mvgbe_rx_jumbo_map; 193 int mvgbe_rx_prod; 194 int mvgbe_rx_cons; 195 int mvgbe_rx_cnt; 196 197 /* Stick the jumbo mem management stuff here too. */ 198 void *mvgbe_jslots[MVGBE_JSLOTS]; 199 void *mvgbe_jumbo_buf; 200 }; 201 202 struct mvgbe_ring_data { 203 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 204 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 205 }; 206 207 struct mvgbec_softc { 208 device_t sc_dev; 209 210 bus_space_tag_t sc_iot; 211 bus_space_handle_t sc_ioh; 212 213 kmutex_t sc_mtx; 214 215 int sc_flags; 216 }; 217 218 struct mvgbe_softc { 219 device_t sc_dev; 220 int sc_port; 221 uint32_t sc_version; 222 223 bus_space_tag_t sc_iot; 224 bus_space_handle_t sc_ioh; 225 bus_space_handle_t sc_dafh; /* dest address filter handle */ 226 bus_dma_tag_t sc_dmat; 227 228 struct ethercom sc_ethercom; 229 struct mii_data sc_mii; 230 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 231 232 callout_t sc_tick_ch; /* tick callout */ 233 234 struct mvgbe_chain_data sc_cdata; 235 struct mvgbe_ring_data *sc_rdata; 236 bus_dmamap_t sc_ring_map; 237 int sc_if_flags; 238 unsigned int sc_ipginttx; 239 unsigned int sc_ipgintrx; 240 int sc_wdogsoft; 241 242 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 243 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 244 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 245 246 struct { 247 bus_space_handle_t ioh; 248 uint32_t bit; 249 } sc_linkup; 250 uint32_t sc_cmdsts_opts; 251 252 krndsource_t sc_rnd_source; 253 struct sysctllog *mvgbe_clog; 254 #ifdef MVGBE_EVENT_COUNTERS 255 struct evcnt sc_ev_rxoverrun; 256 struct evcnt sc_ev_wdogsoft; 257 #endif 258 }; 259 260 261 /* Gigabit Ethernet Unit Global part functions */ 262 263 static int mvgbec_match(device_t, struct cfdata *, void *); 264 static void mvgbec_attach(device_t, device_t, void *); 265 266 static int mvgbec_print(void *, const char *); 267 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 268 269 /* MII funcstions */ 270 static int mvgbec_miibus_readreg(device_t, int, int); 271 static void mvgbec_miibus_writereg(device_t, int, int, int); 272 static void mvgbec_miibus_statchg(struct ifnet *); 273 274 static void mvgbec_wininit(struct mvgbec_softc *, enum marvell_tags *); 275 276 /* Gigabit Ethernet Port part functions */ 277 278 static int mvgbe_match(device_t, struct cfdata *, void *); 279 static void mvgbe_attach(device_t, device_t, void *); 280 281 static void mvgbe_tick(void *); 282 static int mvgbe_intr(void *); 283 284 static void mvgbe_start(struct ifnet *); 285 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 286 static int mvgbe_init(struct ifnet *); 287 static void mvgbe_stop(struct ifnet *, int); 288 static void mvgbe_watchdog(struct ifnet *); 289 290 static int mvgbe_ifflags_cb(struct ethercom *); 291 292 static int mvgbe_mediachange(struct ifnet *); 293 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 294 295 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 296 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 297 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 298 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 299 static void *mvgbe_jalloc(struct mvgbe_softc *); 300 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 301 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 302 static void mvgbe_rxeof(struct mvgbe_softc *); 303 static void mvgbe_txeof(struct mvgbe_softc *); 304 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 305 static void mvgbe_filter_setup(struct mvgbe_softc *); 306 #ifdef MVGBE_DEBUG 307 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 308 #endif 309 static int mvgbe_ipginttx(struct mvgbec_softc *, struct mvgbe_softc *, 310 unsigned int); 311 static int mvgbe_ipgintrx(struct mvgbec_softc *, struct mvgbe_softc *, 312 unsigned int); 313 static void sysctl_mvgbe_init(struct mvgbe_softc *); 314 static int mvgbe_sysctl_ipginttx(SYSCTLFN_PROTO); 315 static int mvgbe_sysctl_ipgintrx(SYSCTLFN_PROTO); 316 317 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 318 mvgbec_match, mvgbec_attach, NULL, NULL); 319 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 320 mvgbec_match, mvgbec_attach, NULL, NULL); 321 322 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 323 mvgbe_match, mvgbe_attach, NULL, NULL); 324 325 device_t mvgbec0 = NULL; 326 static int mvgbe_root_num; 327 328 struct mvgbe_port { 329 int model; 330 int unit; 331 int ports; 332 int irqs[3]; 333 int flags; 334 #define FLAGS_FIX_TQTB (1 << 0) 335 #define FLAGS_FIX_MTU (1 << 1) 336 #define FLAGS_IPG1 (1 << 2) 337 #define FLAGS_IPG2 (1 << 3) 338 #define FLAGS_HAS_PV (1 << 4) /* Has Port Version Register */ 339 } mvgbe_ports[] = { 340 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 341 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 342 #if 0 343 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 344 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 345 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 346 #endif 347 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 348 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU }, 349 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 350 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 351 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU | FLAGS_IPG1 }, 352 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 353 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU }, 354 355 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 356 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 357 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 358 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 359 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 360 { MARVELL_KIRKWOOD_88F6282, 0, 1, { 11 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 361 { MARVELL_KIRKWOOD_88F6282, 1, 1, { 15 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 362 363 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 364 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 365 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 366 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 367 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 368 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB | FLAGS_IPG2 }, 369 370 { MARVELL_ARMADAXP_MV78130, 0, 1, { 66 }, FLAGS_HAS_PV }, 371 { MARVELL_ARMADAXP_MV78130, 1, 1, { 70 }, FLAGS_HAS_PV }, 372 { MARVELL_ARMADAXP_MV78130, 2, 1, { 74 }, FLAGS_HAS_PV }, 373 { MARVELL_ARMADAXP_MV78160, 0, 1, { 66 }, FLAGS_HAS_PV }, 374 { MARVELL_ARMADAXP_MV78160, 1, 1, { 70 }, FLAGS_HAS_PV }, 375 { MARVELL_ARMADAXP_MV78160, 2, 1, { 74 }, FLAGS_HAS_PV }, 376 { MARVELL_ARMADAXP_MV78160, 3, 1, { 78 }, FLAGS_HAS_PV }, 377 { MARVELL_ARMADAXP_MV78230, 0, 1, { 66 }, FLAGS_HAS_PV }, 378 { MARVELL_ARMADAXP_MV78230, 1, 1, { 70 }, FLAGS_HAS_PV }, 379 { MARVELL_ARMADAXP_MV78230, 2, 1, { 74 }, FLAGS_HAS_PV }, 380 { MARVELL_ARMADAXP_MV78260, 0, 1, { 66 }, FLAGS_HAS_PV }, 381 { MARVELL_ARMADAXP_MV78260, 1, 1, { 70 }, FLAGS_HAS_PV }, 382 { MARVELL_ARMADAXP_MV78260, 2, 1, { 74 }, FLAGS_HAS_PV }, 383 { MARVELL_ARMADAXP_MV78260, 3, 1, { 78 }, FLAGS_HAS_PV }, 384 { MARVELL_ARMADAXP_MV78460, 0, 1, { 66 }, FLAGS_HAS_PV }, 385 { MARVELL_ARMADAXP_MV78460, 1, 1, { 70 }, FLAGS_HAS_PV }, 386 { MARVELL_ARMADAXP_MV78460, 2, 1, { 74 }, FLAGS_HAS_PV }, 387 { MARVELL_ARMADAXP_MV78460, 3, 1, { 78 }, FLAGS_HAS_PV }, 388 389 { MARVELL_ARMADA370_MV6707, 0, 1, { 66 }, FLAGS_HAS_PV }, 390 { MARVELL_ARMADA370_MV6707, 1, 1, { 70 }, FLAGS_HAS_PV }, 391 { MARVELL_ARMADA370_MV6710, 0, 1, { 66 }, FLAGS_HAS_PV }, 392 { MARVELL_ARMADA370_MV6710, 1, 1, { 70 }, FLAGS_HAS_PV }, 393 { MARVELL_ARMADA370_MV6W11, 0, 1, { 66 }, FLAGS_HAS_PV }, 394 { MARVELL_ARMADA370_MV6W11, 1, 1, { 70 }, FLAGS_HAS_PV }, 395 }; 396 397 398 /* ARGSUSED */ 399 static int 400 mvgbec_match(device_t parent, cfdata_t match, void *aux) 401 { 402 struct marvell_attach_args *mva = aux; 403 int i; 404 405 if (strcmp(mva->mva_name, match->cf_name) != 0) 406 return 0; 407 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 408 return 0; 409 410 for (i = 0; i < __arraycount(mvgbe_ports); i++) 411 if (mva->mva_model == mvgbe_ports[i].model) { 412 mva->mva_size = MVGBE_SIZE; 413 return 1; 414 } 415 return 0; 416 } 417 418 /* ARGSUSED */ 419 static void 420 mvgbec_attach(device_t parent, device_t self, void *aux) 421 { 422 struct mvgbec_softc *csc = device_private(self); 423 struct marvell_attach_args *mva = aux, gbea; 424 struct mvgbe_softc *port; 425 struct mii_softc *mii; 426 device_t child; 427 uint32_t phyaddr; 428 int i, j; 429 430 aprint_naive("\n"); 431 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 432 433 csc->sc_dev = self; 434 csc->sc_iot = mva->mva_iot; 435 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 436 mva->mva_size, &csc->sc_ioh)) { 437 aprint_error_dev(self, "Cannot map registers\n"); 438 return; 439 } 440 441 if (mvgbec0 == NULL) 442 mvgbec0 = self; 443 444 phyaddr = 0; 445 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 446 447 mutex_init(&csc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 448 449 /* Disable and clear Gigabit Ethernet Unit interrupts */ 450 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 451 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 452 453 mvgbec_wininit(csc, mva->mva_tags); 454 455 memset(&gbea, 0, sizeof(gbea)); 456 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 457 if (mvgbe_ports[i].model != mva->mva_model || 458 mvgbe_ports[i].unit != mva->mva_unit) 459 continue; 460 461 csc->sc_flags = mvgbe_ports[i].flags; 462 463 for (j = 0; j < mvgbe_ports[i].ports; j++) { 464 gbea.mva_name = "mvgbe"; 465 gbea.mva_model = mva->mva_model; 466 gbea.mva_iot = csc->sc_iot; 467 gbea.mva_ioh = csc->sc_ioh; 468 gbea.mva_unit = j; 469 gbea.mva_dmat = mva->mva_dmat; 470 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 471 child = config_found_sm_loc(csc->sc_dev, "mvgbec", NULL, 472 &gbea, mvgbec_print, mvgbec_search); 473 if (child) { 474 port = device_private(child); 475 mii = LIST_FIRST(&port->sc_mii.mii_phys); 476 if (mii != NULL) 477 phyaddr |= MVGBE_PHYADDR_PHYAD(j, 478 mii->mii_phy); 479 } 480 } 481 break; 482 } 483 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 484 } 485 486 static int 487 mvgbec_print(void *aux, const char *pnp) 488 { 489 struct marvell_attach_args *gbea = aux; 490 491 if (pnp) 492 aprint_normal("%s at %s port %d", 493 gbea->mva_name, pnp, gbea->mva_unit); 494 else { 495 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 496 aprint_normal(" port %d", gbea->mva_unit); 497 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 498 aprint_normal(" irq %d", gbea->mva_irq); 499 } 500 return UNCONF; 501 } 502 503 /* ARGSUSED */ 504 static int 505 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 506 { 507 struct marvell_attach_args *gbea = aux; 508 509 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 510 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 511 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 512 513 return config_match(parent, cf, aux); 514 } 515 516 static int 517 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 518 { 519 struct mvgbe_softc *sc = device_private(dev); 520 struct mvgbec_softc *csc; 521 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 522 uint32_t smi, val; 523 int i; 524 525 if (mvgbec0 == NULL) { 526 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 527 return -1; 528 } 529 csc = device_private(mvgbec0); 530 531 mutex_enter(&csc->sc_mtx); 532 533 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 534 DELAY(1); 535 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 536 break; 537 } 538 if (i == MVGBE_PHY_TIMEOUT) { 539 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 540 mutex_exit(&csc->sc_mtx); 541 return -1; 542 } 543 544 smi = 545 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 546 MVGBE_WRITE(csc, MVGBE_SMI, smi); 547 548 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 549 DELAY(1); 550 smi = MVGBE_READ(csc, MVGBE_SMI); 551 if (smi & MVGBE_SMI_READVALID) 552 break; 553 } 554 555 mutex_exit(&csc->sc_mtx); 556 557 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 558 i, MVGBE_PHY_TIMEOUT)); 559 560 val = smi & MVGBE_SMI_DATA_MASK; 561 562 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 563 phy, reg, val)); 564 565 return val; 566 } 567 568 static void 569 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 570 { 571 struct mvgbe_softc *sc = device_private(dev); 572 struct mvgbec_softc *csc; 573 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 574 uint32_t smi; 575 int i; 576 577 if (mvgbec0 == NULL) { 578 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 579 return; 580 } 581 csc = device_private(mvgbec0); 582 583 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 584 phy, reg, val)); 585 586 mutex_enter(&csc->sc_mtx); 587 588 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 589 DELAY(1); 590 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 591 break; 592 } 593 if (i == MVGBE_PHY_TIMEOUT) { 594 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 595 mutex_exit(&csc->sc_mtx); 596 return; 597 } 598 599 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 600 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 601 MVGBE_WRITE(csc, MVGBE_SMI, smi); 602 603 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 604 DELAY(1); 605 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 606 break; 607 } 608 609 mutex_exit(&csc->sc_mtx); 610 611 if (i == MVGBE_PHY_TIMEOUT) 612 aprint_error_ifnet(ifp, "phy write timed out\n"); 613 } 614 615 static void 616 mvgbec_miibus_statchg(struct ifnet *ifp) 617 { 618 619 /* nothing to do */ 620 } 621 622 623 static void 624 mvgbec_wininit(struct mvgbec_softc *sc, enum marvell_tags *tags) 625 { 626 device_t pdev = device_parent(sc->sc_dev); 627 uint64_t base; 628 uint32_t en, ac, size; 629 int window, target, attr, rv, i; 630 631 /* First disable all address decode windows */ 632 en = MVGBE_BARE_EN_MASK; 633 MVGBE_WRITE(sc, MVGBE_BARE, en); 634 635 ac = 0; 636 for (window = 0, i = 0; 637 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 638 rv = marvell_winparams_by_tag(pdev, tags[i], 639 &target, &attr, &base, &size); 640 if (rv != 0 || size == 0) 641 continue; 642 643 if (base > 0xffffffffULL) { 644 if (window >= MVGBE_NREMAP) { 645 aprint_error_dev(sc->sc_dev, 646 "can't remap window %d\n", window); 647 continue; 648 } 649 MVGBE_WRITE(sc, MVGBE_HA(window), 650 (base >> 32) & 0xffffffff); 651 } 652 653 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 654 MVGBE_BASEADDR_TARGET(target) | 655 MVGBE_BASEADDR_ATTR(attr) | 656 MVGBE_BASEADDR_BASE(base)); 657 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 658 659 en &= ~(1 << window); 660 /* set full access (r/w) */ 661 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 662 window++; 663 } 664 /* allow to access decode window */ 665 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 666 667 MVGBE_WRITE(sc, MVGBE_BARE, en); 668 } 669 670 671 /* ARGSUSED */ 672 static int 673 mvgbe_match(device_t parent, cfdata_t match, void *aux) 674 { 675 struct marvell_attach_args *mva = aux; 676 uint32_t pbase, maddrh, maddrl; 677 prop_dictionary_t dict; 678 679 dict = device_properties(parent); 680 if (dict) { 681 if (prop_dictionary_get(dict, "mac-address")) 682 return 1; 683 } 684 685 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 686 maddrh = 687 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 688 maddrl = 689 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 690 if ((maddrh | maddrl) == 0) 691 return 0; 692 693 return 1; 694 } 695 696 /* ARGSUSED */ 697 static void 698 mvgbe_attach(device_t parent, device_t self, void *aux) 699 { 700 struct mvgbec_softc *csc = device_private(parent); 701 struct mvgbe_softc *sc = device_private(self); 702 struct marvell_attach_args *mva = aux; 703 struct mvgbe_txmap_entry *entry; 704 prop_dictionary_t dict; 705 prop_data_t enaddrp; 706 struct ifnet *ifp; 707 bus_dma_segment_t seg; 708 bus_dmamap_t dmamap; 709 int rseg, i; 710 uint32_t maddrh, maddrl; 711 uint8_t enaddr[ETHER_ADDR_LEN]; 712 void *kva; 713 714 aprint_naive("\n"); 715 aprint_normal("\n"); 716 717 dict = device_properties(parent); 718 if (dict) 719 enaddrp = prop_dictionary_get(dict, "mac-address"); 720 else 721 enaddrp = NULL; 722 723 sc->sc_dev = self; 724 sc->sc_port = mva->mva_unit; 725 sc->sc_iot = mva->mva_iot; 726 callout_init(&sc->sc_tick_ch, 0); 727 callout_setfunc(&sc->sc_tick_ch, mvgbe_tick, sc); 728 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 729 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 730 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 731 aprint_error_dev(self, "Cannot map registers\n"); 732 return; 733 } 734 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 735 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 736 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 737 aprint_error_dev(self, 738 "Cannot map destination address filter registers\n"); 739 return; 740 } 741 sc->sc_dmat = mva->mva_dmat; 742 743 if (csc->sc_flags & FLAGS_HAS_PV) { 744 /* GbE port has Port Version register. */ 745 sc->sc_version = MVGBE_READ(sc, MVGBE_PV); 746 aprint_normal_dev(self, "Port Version 0x%x\n", sc->sc_version); 747 } 748 749 if (sc->sc_version >= 0x10) { 750 /* 751 * Armada XP 752 */ 753 754 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 755 MVGBE_PS0, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 756 aprint_error_dev(self, "Cannot map linkup register\n"); 757 return; 758 } 759 sc->sc_linkup.bit = MVGBE_PS0_LINKUP; 760 csc->sc_flags |= FLAGS_IPG2; 761 } else { 762 if (bus_space_subregion(mva->mva_iot, sc->sc_ioh, 763 MVGBE_PS, sizeof(uint32_t), &sc->sc_linkup.ioh)) { 764 aprint_error_dev(self, "Cannot map linkup register\n"); 765 return; 766 } 767 sc->sc_linkup.bit = MVGBE_PS_LINKUP; 768 } 769 770 if (enaddrp) { 771 memcpy(enaddr, prop_data_data_nocopy(enaddrp), ETHER_ADDR_LEN); 772 maddrh = enaddr[0] << 24; 773 maddrh |= enaddr[1] << 16; 774 maddrh |= enaddr[2] << 8; 775 maddrh |= enaddr[3]; 776 maddrl = enaddr[4] << 8; 777 maddrl |= enaddr[5]; 778 MVGBE_WRITE(sc, MVGBE_MACAH, maddrh); 779 MVGBE_WRITE(sc, MVGBE_MACAL, maddrl); 780 } 781 782 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 783 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 784 sc->sc_enaddr[0] = maddrh >> 24; 785 sc->sc_enaddr[1] = maddrh >> 16; 786 sc->sc_enaddr[2] = maddrh >> 8; 787 sc->sc_enaddr[3] = maddrh >> 0; 788 sc->sc_enaddr[4] = maddrl >> 8; 789 sc->sc_enaddr[5] = maddrl >> 0; 790 aprint_normal_dev(self, "Ethernet address %s\n", 791 ether_sprintf(sc->sc_enaddr)); 792 793 /* clear all ethernet port interrupts */ 794 MVGBE_WRITE(sc, MVGBE_IC, 0); 795 MVGBE_WRITE(sc, MVGBE_ICE, 0); 796 797 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 798 799 /* Allocate the descriptor queues. */ 800 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 801 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 802 aprint_error_dev(self, "can't alloc rx buffers\n"); 803 return; 804 } 805 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 806 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 807 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 808 (u_long)sizeof(struct mvgbe_ring_data)); 809 goto fail1; 810 } 811 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 812 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 813 &sc->sc_ring_map)) { 814 aprint_error_dev(self, "can't create dma map\n"); 815 goto fail2; 816 } 817 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 818 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 819 aprint_error_dev(self, "can't load dma map\n"); 820 goto fail3; 821 } 822 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 823 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 824 825 SIMPLEQ_INIT(&sc->sc_txmap_head); 826 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 827 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 828 829 if (bus_dmamap_create(sc->sc_dmat, 830 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 831 BUS_DMA_NOWAIT, &dmamap)) { 832 aprint_error_dev(self, "Can't create TX dmamap\n"); 833 goto fail4; 834 } 835 836 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 837 if (!entry) { 838 aprint_error_dev(self, "Can't alloc txmap entry\n"); 839 bus_dmamap_destroy(sc->sc_dmat, dmamap); 840 goto fail4; 841 } 842 entry->dmamap = dmamap; 843 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 844 } 845 846 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 847 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 848 849 /* 850 * We can support 802.1Q VLAN-sized frames and jumbo 851 * Ethernet frames. 852 */ 853 sc->sc_ethercom.ec_capabilities |= 854 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 855 856 /* Try to allocate memory for jumbo buffers. */ 857 if (mvgbe_alloc_jumbo_mem(sc)) { 858 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 859 goto fail4; 860 } 861 862 ifp = &sc->sc_ethercom.ec_if; 863 ifp->if_softc = sc; 864 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 865 ifp->if_start = mvgbe_start; 866 ifp->if_ioctl = mvgbe_ioctl; 867 ifp->if_init = mvgbe_init; 868 ifp->if_stop = mvgbe_stop; 869 ifp->if_watchdog = mvgbe_watchdog; 870 /* 871 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 872 */ 873 sc->sc_ethercom.ec_if.if_capabilities |= 874 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 875 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 876 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 877 /* 878 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 879 */ 880 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 881 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 882 IFQ_SET_READY(&ifp->if_snd); 883 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 884 885 mvgbe_stop(ifp, 0); 886 887 /* 888 * Do MII setup. 889 */ 890 sc->sc_mii.mii_ifp = ifp; 891 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 892 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 893 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 894 895 sc->sc_ethercom.ec_mii = &sc->sc_mii; 896 ifmedia_init(&sc->sc_mii.mii_media, 0, 897 mvgbe_mediachange, mvgbe_mediastatus); 898 mii_attach(self, &sc->sc_mii, 0xffffffff, 899 MII_PHY_ANY, parent == mvgbec0 ? 0 : 1, 0); 900 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 901 aprint_error_dev(self, "no PHY found!\n"); 902 ifmedia_add(&sc->sc_mii.mii_media, 903 IFM_ETHER|IFM_MANUAL, 0, NULL); 904 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 905 } else 906 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 907 908 /* 909 * Call MI attach routines. 910 */ 911 if_attach(ifp); 912 if_deferred_start_init(ifp, NULL); 913 914 ether_ifattach(ifp, sc->sc_enaddr); 915 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 916 917 sysctl_mvgbe_init(sc); 918 #ifdef MVGBE_EVENT_COUNTERS 919 /* Attach event counters. */ 920 evcnt_attach_dynamic(&sc->sc_ev_rxoverrun, EVCNT_TYPE_MISC, 921 NULL, device_xname(sc->sc_dev), "rxoverrrun"); 922 evcnt_attach_dynamic(&sc->sc_ev_wdogsoft, EVCNT_TYPE_MISC, 923 NULL, device_xname(sc->sc_dev), "wdogsoft"); 924 #endif 925 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 926 RND_TYPE_NET, RND_FLAG_DEFAULT); 927 928 return; 929 930 fail4: 931 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 932 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 933 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 934 } 935 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 936 fail3: 937 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 938 fail2: 939 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 940 fail1: 941 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 942 return; 943 } 944 945 static int 946 mvgbe_ipginttx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 947 unsigned int ipginttx) 948 { 949 uint32_t reg; 950 reg = MVGBE_READ(sc, MVGBE_PTFUT); 951 952 if (csc->sc_flags & FLAGS_IPG2) { 953 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V2_MAX) 954 return -1; 955 reg &= ~MVGBE_PTFUT_IPGINTTX_V2_MASK; 956 reg |= MVGBE_PTFUT_IPGINTTX_V2(ipginttx); 957 } else if (csc->sc_flags & FLAGS_IPG1) { 958 if (ipginttx > MVGBE_PTFUT_IPGINTTX_V1_MAX) 959 return -1; 960 reg &= ~MVGBE_PTFUT_IPGINTTX_V1_MASK; 961 reg |= MVGBE_PTFUT_IPGINTTX_V1(ipginttx); 962 } 963 MVGBE_WRITE(sc, MVGBE_PTFUT, reg); 964 965 return 0; 966 } 967 968 static int 969 mvgbe_ipgintrx(struct mvgbec_softc *csc, struct mvgbe_softc *sc, 970 unsigned int ipgintrx) 971 { 972 uint32_t reg; 973 reg = MVGBE_READ(sc, MVGBE_SDC); 974 975 if (csc->sc_flags & FLAGS_IPG2) { 976 if (ipgintrx > MVGBE_SDC_IPGINTRX_V2_MAX) 977 return -1; 978 reg &= ~MVGBE_SDC_IPGINTRX_V2_MASK; 979 reg |= MVGBE_SDC_IPGINTRX_V2(ipgintrx); 980 } else if (csc->sc_flags & FLAGS_IPG1) { 981 if (ipgintrx > MVGBE_SDC_IPGINTRX_V1_MAX) 982 return -1; 983 reg &= ~MVGBE_SDC_IPGINTRX_V1_MASK; 984 reg |= MVGBE_SDC_IPGINTRX_V1(ipgintrx); 985 } 986 MVGBE_WRITE(sc, MVGBE_SDC, reg); 987 988 return 0; 989 } 990 991 static void 992 mvgbe_tick(void *arg) 993 { 994 struct mvgbe_softc *sc = arg; 995 struct mii_data *mii = &sc->sc_mii; 996 int s; 997 998 s = splnet(); 999 mii_tick(mii); 1000 /* Need more work */ 1001 MVGBE_EVCNT_ADD(&sc->sc_ev_rxoverrun, MVGBE_READ(sc, MVGBE_POFC)); 1002 splx(s); 1003 1004 callout_schedule(&sc->sc_tick_ch, hz); 1005 } 1006 1007 static int 1008 mvgbe_intr(void *arg) 1009 { 1010 struct mvgbe_softc *sc = arg; 1011 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1012 uint32_t ic, ice, datum = 0; 1013 int claimed = 0; 1014 1015 for (;;) { 1016 ice = MVGBE_READ(sc, MVGBE_ICE); 1017 ic = MVGBE_READ(sc, MVGBE_IC); 1018 1019 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 1020 if (ic == 0 && ice == 0) 1021 break; 1022 1023 datum = datum ^ ic ^ ice; 1024 1025 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 1026 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 1027 1028 claimed = 1; 1029 1030 if (!(ifp->if_flags & IFF_RUNNING)) 1031 break; 1032 1033 if (ice & MVGBE_ICE_LINKCHG) { 1034 if (MVGBE_IS_LINKUP(sc)) { 1035 /* Enable port RX and TX. */ 1036 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1037 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1038 } else { 1039 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 1040 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1041 } 1042 1043 /* Notify link change event to mii layer */ 1044 mii_pollstat(&sc->sc_mii); 1045 } 1046 1047 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 1048 mvgbe_rxeof(sc); 1049 1050 if (ice & (MVGBE_ICE_TXBUF_MASK | MVGBE_ICE_TXERR_MASK)) 1051 mvgbe_txeof(sc); 1052 } 1053 1054 if_schedule_deferred_start(ifp); 1055 1056 rnd_add_uint32(&sc->sc_rnd_source, datum); 1057 1058 return claimed; 1059 } 1060 1061 static void 1062 mvgbe_start(struct ifnet *ifp) 1063 { 1064 struct mvgbe_softc *sc = ifp->if_softc; 1065 struct mbuf *m_head = NULL; 1066 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 1067 int pkts = 0; 1068 1069 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 1070 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 1071 1072 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1073 return; 1074 /* If Link is DOWN, can't start TX */ 1075 if (!MVGBE_IS_LINKUP(sc)) 1076 return; 1077 1078 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 1079 IFQ_POLL(&ifp->if_snd, m_head); 1080 if (m_head == NULL) 1081 break; 1082 1083 /* 1084 * Pack the data into the transmit ring. If we 1085 * don't have room, set the OACTIVE flag and wait 1086 * for the NIC to drain the ring. 1087 */ 1088 if (mvgbe_encap(sc, m_head, &idx)) { 1089 if (sc->sc_cdata.mvgbe_tx_cnt > 0) 1090 ifp->if_flags |= IFF_OACTIVE; 1091 break; 1092 } 1093 1094 /* now we are committed to transmit the packet */ 1095 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1096 pkts++; 1097 1098 /* 1099 * If there's a BPF listener, bounce a copy of this frame 1100 * to him. 1101 */ 1102 bpf_mtap(ifp, m_head); 1103 } 1104 if (pkts == 0) 1105 return; 1106 1107 /* Transmit at Queue 0 */ 1108 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 1109 sc->sc_cdata.mvgbe_tx_prod = idx; 1110 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1111 1112 /* 1113 * Set a timeout in case the chip goes out to lunch. 1114 */ 1115 ifp->if_timer = 1; 1116 sc->sc_wdogsoft = 1; 1117 } 1118 } 1119 1120 static int 1121 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1122 { 1123 struct mvgbe_softc *sc = ifp->if_softc; 1124 struct ifreq *ifr = data; 1125 int s, error = 0; 1126 1127 s = splnet(); 1128 1129 switch (cmd) { 1130 case SIOCGIFMEDIA: 1131 case SIOCSIFMEDIA: 1132 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 1133 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1134 break; 1135 default: 1136 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 1137 error = ether_ioctl(ifp, cmd, data); 1138 if (error == ENETRESET) { 1139 if (ifp->if_flags & IFF_RUNNING) { 1140 mvgbe_filter_setup(sc); 1141 } 1142 error = 0; 1143 } 1144 break; 1145 } 1146 1147 splx(s); 1148 1149 return error; 1150 } 1151 1152 static int 1153 mvgbe_init(struct ifnet *ifp) 1154 { 1155 struct mvgbe_softc *sc = ifp->if_softc; 1156 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1157 struct mii_data *mii = &sc->sc_mii; 1158 uint32_t reg; 1159 int i; 1160 1161 DPRINTFN(2, ("mvgbe_init\n")); 1162 1163 /* Cancel pending I/O and free all RX/TX buffers. */ 1164 mvgbe_stop(ifp, 0); 1165 1166 /* clear all ethernet port interrupts */ 1167 MVGBE_WRITE(sc, MVGBE_IC, 0); 1168 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1169 1170 /* Init TX/RX descriptors */ 1171 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 1172 aprint_error_ifnet(ifp, 1173 "initialization failed: no memory for tx buffers\n"); 1174 return ENOBUFS; 1175 } 1176 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 1177 aprint_error_ifnet(ifp, 1178 "initialization failed: no memory for rx buffers\n"); 1179 return ENOBUFS; 1180 } 1181 1182 if ((csc->sc_flags & FLAGS_IPG1) || (csc->sc_flags & FLAGS_IPG2)) { 1183 sc->sc_ipginttx = MVGBE_IPGINTTX_DEFAULT; 1184 sc->sc_ipgintrx = MVGBE_IPGINTRX_DEFAULT; 1185 } 1186 if (csc->sc_flags & FLAGS_FIX_MTU) 1187 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */ 1188 if (sc->sc_version >= 0x10) { 1189 MVGBE_WRITE(csc, MVGBE_PANC, 1190 MVGBE_PANC_FORCELINKPASS | 1191 MVGBE_PANC_INBANDANBYPASSEN | 1192 MVGBE_PANC_SETMIISPEED | 1193 MVGBE_PANC_SETGMIISPEED | 1194 MVGBE_PANC_ANSPEEDEN | 1195 MVGBE_PANC_SETFCEN | 1196 MVGBE_PANC_PAUSEADV | 1197 MVGBE_PANC_SETFULLDX | 1198 MVGBE_PANC_ANDUPLEXEN | 1199 MVGBE_PANC_RESERVED); 1200 MVGBE_WRITE(csc, MVGBE_PMACC0, 1201 MVGBE_PMACC0_RESERVED | 1202 MVGBE_PMACC0_FRAMESIZELIMIT(1600)); 1203 reg = MVGBE_READ(csc, MVGBE_PMACC2); 1204 reg &= MVGBE_PMACC2_PCSEN; /* keep PCSEN bit */ 1205 MVGBE_WRITE(csc, MVGBE_PMACC2, 1206 reg | MVGBE_PMACC2_RESERVED | MVGBE_PMACC2_RGMIIEN); 1207 1208 MVGBE_WRITE(sc, MVGBE_PXCX, 1209 MVGBE_READ(sc, MVGBE_PXCX) & ~MVGBE_PXCX_TXCRCDIS); 1210 1211 #ifndef MULTIPROCESSOR 1212 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_BM); 1213 #else 1214 MVGBE_WRITE(sc, MVGBE_PACC, MVGVE_PACC_ACCELERATIONMODE_EDM); 1215 #endif 1216 } else { 1217 MVGBE_WRITE(sc, MVGBE_PSC, 1218 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 1219 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 1220 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 1221 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 1222 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 1223 /* XXXX: mvgbe(4) always use RGMII. */ 1224 MVGBE_WRITE(sc, MVGBE_PSC1, 1225 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 1226 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 1227 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 1228 1229 sc->sc_cmdsts_opts = MVGBE_TX_GENERATE_CRC; 1230 } 1231 1232 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 1233 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 1234 1235 if (csc->sc_flags & FLAGS_FIX_TQTB) { 1236 /* 1237 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1238 * And offset 0x72704 must be programmed to 0x03ffffff. 1239 * Queue 1 through 7 must be programmed to 0x0. 1240 */ 1241 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1242 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1243 for (i = 1; i < 8; i++) { 1244 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1245 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1246 } 1247 } else if (sc->sc_version < 0x10) 1248 for (i = 1; i < 8; i++) { 1249 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1250 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1251 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1252 } 1253 1254 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1255 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1256 1257 /* Set SDC register except IPGINT bits */ 1258 MVGBE_WRITE(sc, MVGBE_SDC, 1259 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1260 #if BYTE_ORDER == LITTLE_ENDIAN 1261 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1262 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1263 #endif 1264 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1265 /* And then set IPGINT bits */ 1266 mvgbe_ipgintrx(csc, sc, sc->sc_ipgintrx); 1267 1268 /* Tx side */ 1269 MVGBE_WRITE(sc, MVGBE_PTFUT, 0); 1270 mvgbe_ipginttx(csc, sc, sc->sc_ipginttx); 1271 1272 mvgbe_filter_setup(sc); 1273 1274 mii_mediachg(mii); 1275 1276 /* Enable port */ 1277 if (sc->sc_version >= 0x10) { 1278 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1279 MVGBE_WRITE(csc, MVGBE_PMACC0, reg | MVGBE_PMACC0_PORTEN); 1280 } else { 1281 reg = MVGBE_READ(sc, MVGBE_PSC); 1282 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1283 } 1284 1285 /* If Link is UP, Start RX and TX traffic */ 1286 if (MVGBE_IS_LINKUP(sc)) { 1287 /* Enable port RX/TX. */ 1288 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1289 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1290 } 1291 1292 /* Enable interrupt masks */ 1293 MVGBE_WRITE(sc, MVGBE_PIM, 1294 MVGBE_IC_RXBUF | 1295 MVGBE_IC_EXTEND | 1296 MVGBE_IC_RXBUFQ_MASK | 1297 MVGBE_IC_RXERROR | 1298 MVGBE_IC_RXERRQ_MASK); 1299 MVGBE_WRITE(sc, MVGBE_PEIM, 1300 MVGBE_ICE_TXBUF_MASK | 1301 MVGBE_ICE_TXERR_MASK | 1302 MVGBE_ICE_LINKCHG); 1303 1304 callout_schedule(&sc->sc_tick_ch, hz); 1305 1306 ifp->if_flags |= IFF_RUNNING; 1307 ifp->if_flags &= ~IFF_OACTIVE; 1308 1309 return 0; 1310 } 1311 1312 /* ARGSUSED */ 1313 static void 1314 mvgbe_stop(struct ifnet *ifp, int disable) 1315 { 1316 struct mvgbe_softc *sc = ifp->if_softc; 1317 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1318 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1319 uint32_t reg, txinprog, txfifoemp; 1320 int i, cnt; 1321 1322 DPRINTFN(2, ("mvgbe_stop\n")); 1323 1324 callout_stop(&sc->sc_tick_ch); 1325 1326 /* Stop Rx port activity. Check port Rx activity. */ 1327 reg = MVGBE_READ(sc, MVGBE_RQC); 1328 if (reg & MVGBE_RQC_ENQ_MASK) 1329 /* Issue stop command for active channels only */ 1330 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1331 1332 /* Stop Tx port activity. Check port Tx activity. */ 1333 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ(0)) 1334 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ(0)); 1335 1336 /* Force link down */ 1337 if (sc->sc_version >= 0x10) { 1338 reg = MVGBE_READ(csc, MVGBE_PANC); 1339 MVGBE_WRITE(csc, MVGBE_PANC, reg | MVGBE_PANC_FORCELINKFAIL); 1340 1341 txinprog = MVGBE_PS_TXINPROG_(0); 1342 txfifoemp = MVGBE_PS_TXFIFOEMP_(0); 1343 } else { 1344 reg = MVGBE_READ(sc, MVGBE_PSC); 1345 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1346 1347 txinprog = MVGBE_PS_TXINPROG; 1348 txfifoemp = MVGBE_PS_TXFIFOEMP; 1349 } 1350 1351 #define RX_DISABLE_TIMEOUT 0x1000000 1352 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1353 /* Wait for all Rx activity to terminate. */ 1354 cnt = 0; 1355 do { 1356 if (cnt >= RX_DISABLE_TIMEOUT) { 1357 aprint_error_ifnet(ifp, 1358 "timeout for RX stopped. rqc 0x%x\n", reg); 1359 break; 1360 } 1361 cnt++; 1362 1363 /* 1364 * Check Receive Queue Command register that all Rx queues 1365 * are stopped 1366 */ 1367 reg = MVGBE_READ(sc, MVGBE_RQC); 1368 } while (reg & 0xff); 1369 1370 /* Double check to verify that TX FIFO is empty */ 1371 cnt = 0; 1372 while (1) { 1373 do { 1374 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1375 aprint_error_ifnet(ifp, 1376 "timeout for TX FIFO empty. status 0x%x\n", 1377 reg); 1378 break; 1379 } 1380 cnt++; 1381 1382 reg = MVGBE_READ(sc, MVGBE_PS); 1383 } while (!(reg & txfifoemp) || reg & txinprog); 1384 1385 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1386 break; 1387 1388 /* Double check */ 1389 reg = MVGBE_READ(sc, MVGBE_PS); 1390 if (reg & txfifoemp && !(reg & txinprog)) 1391 break; 1392 else 1393 aprint_error_ifnet(ifp, 1394 "TX FIFO empty double check failed." 1395 " %d loops, status 0x%x\n", cnt, reg); 1396 } 1397 1398 /* Reset the Enable bit */ 1399 if (sc->sc_version >= 0x10) { 1400 reg = MVGBE_READ(csc, MVGBE_PMACC0); 1401 MVGBE_WRITE(csc, MVGBE_PMACC0, reg & ~MVGBE_PMACC0_PORTEN); 1402 } else { 1403 reg = MVGBE_READ(sc, MVGBE_PSC); 1404 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1405 } 1406 1407 /* 1408 * Disable and clear interrupts 1409 * 0) controller interrupt 1410 * 1) port interrupt cause 1411 * 2) port interrupt mask 1412 */ 1413 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 1414 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 1415 MVGBE_WRITE(sc, MVGBE_IC, 0); 1416 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1417 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1418 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1419 1420 /* Free RX and TX mbufs still in the queues. */ 1421 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1422 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1423 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1424 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1425 } 1426 } 1427 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1428 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1429 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1430 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1431 } 1432 } 1433 1434 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1435 } 1436 1437 static void 1438 mvgbe_watchdog(struct ifnet *ifp) 1439 { 1440 struct mvgbe_softc *sc = ifp->if_softc; 1441 1442 /* 1443 * Reclaim first as there is a possibility of losing Tx completion 1444 * interrupts. 1445 */ 1446 mvgbe_txeof(sc); 1447 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1448 if (sc->sc_wdogsoft) { 1449 /* 1450 * There is race condition between CPU and DMA 1451 * engine. When DMA engine encounters queue end, 1452 * it clears MVGBE_TQC_ENQ bit. 1453 */ 1454 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ(0)); 1455 ifp->if_timer = 5; 1456 sc->sc_wdogsoft = 0; 1457 MVGBE_EVCNT_INCR(&sc->sc_ev_wdogsoft); 1458 } else { 1459 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1460 1461 ifp->if_oerrors++; 1462 1463 mvgbe_init(ifp); 1464 } 1465 } 1466 } 1467 1468 static int 1469 mvgbe_ifflags_cb(struct ethercom *ec) 1470 { 1471 struct ifnet *ifp = &ec->ec_if; 1472 struct mvgbe_softc *sc = ifp->if_softc; 1473 int change = ifp->if_flags ^ sc->sc_if_flags; 1474 1475 if (change != 0) 1476 sc->sc_if_flags = ifp->if_flags; 1477 1478 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1479 return ENETRESET; 1480 1481 if ((change & IFF_PROMISC) != 0) 1482 mvgbe_filter_setup(sc); 1483 1484 return 0; 1485 } 1486 1487 /* 1488 * Set media options. 1489 */ 1490 static int 1491 mvgbe_mediachange(struct ifnet *ifp) 1492 { 1493 return ether_mediachange(ifp); 1494 } 1495 1496 /* 1497 * Report current media status. 1498 */ 1499 static void 1500 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1501 { 1502 ether_mediastatus(ifp, ifmr); 1503 } 1504 1505 1506 static int 1507 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1508 { 1509 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1510 struct mvgbe_ring_data *rd = sc->sc_rdata; 1511 int i; 1512 1513 memset(rd->mvgbe_rx_ring, 0, 1514 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1515 1516 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1517 cd->mvgbe_rx_chain[i].mvgbe_desc = 1518 &rd->mvgbe_rx_ring[i]; 1519 if (i == MVGBE_RX_RING_CNT - 1) { 1520 cd->mvgbe_rx_chain[i].mvgbe_next = 1521 &cd->mvgbe_rx_chain[0]; 1522 rd->mvgbe_rx_ring[i].nextdescptr = 1523 MVGBE_RX_RING_ADDR(sc, 0); 1524 } else { 1525 cd->mvgbe_rx_chain[i].mvgbe_next = 1526 &cd->mvgbe_rx_chain[i + 1]; 1527 rd->mvgbe_rx_ring[i].nextdescptr = 1528 MVGBE_RX_RING_ADDR(sc, i + 1); 1529 } 1530 } 1531 1532 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1533 if (mvgbe_newbuf(sc, i, NULL, 1534 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1535 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1536 "failed alloc of %dth mbuf\n", i); 1537 return ENOBUFS; 1538 } 1539 } 1540 sc->sc_cdata.mvgbe_rx_prod = 0; 1541 sc->sc_cdata.mvgbe_rx_cons = 0; 1542 1543 return 0; 1544 } 1545 1546 static int 1547 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1548 { 1549 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1550 struct mvgbe_ring_data *rd = sc->sc_rdata; 1551 int i; 1552 1553 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1554 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1555 1556 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1557 cd->mvgbe_tx_chain[i].mvgbe_desc = 1558 &rd->mvgbe_tx_ring[i]; 1559 if (i == MVGBE_TX_RING_CNT - 1) { 1560 cd->mvgbe_tx_chain[i].mvgbe_next = 1561 &cd->mvgbe_tx_chain[0]; 1562 rd->mvgbe_tx_ring[i].nextdescptr = 1563 MVGBE_TX_RING_ADDR(sc, 0); 1564 } else { 1565 cd->mvgbe_tx_chain[i].mvgbe_next = 1566 &cd->mvgbe_tx_chain[i + 1]; 1567 rd->mvgbe_tx_ring[i].nextdescptr = 1568 MVGBE_TX_RING_ADDR(sc, i + 1); 1569 } 1570 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1571 } 1572 1573 sc->sc_cdata.mvgbe_tx_prod = 0; 1574 sc->sc_cdata.mvgbe_tx_cons = 0; 1575 sc->sc_cdata.mvgbe_tx_cnt = 0; 1576 1577 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1578 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1579 1580 return 0; 1581 } 1582 1583 static int 1584 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1585 bus_dmamap_t dmamap) 1586 { 1587 struct mbuf *m_new = NULL; 1588 struct mvgbe_chain *c; 1589 struct mvgbe_rx_desc *r; 1590 int align; 1591 vaddr_t offset; 1592 1593 if (m == NULL) { 1594 void *buf = NULL; 1595 1596 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1597 if (m_new == NULL) { 1598 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1599 "no memory for rx list -- packet dropped!\n"); 1600 return ENOBUFS; 1601 } 1602 1603 /* Allocate the jumbo buffer */ 1604 buf = mvgbe_jalloc(sc); 1605 if (buf == NULL) { 1606 m_freem(m_new); 1607 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1608 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1609 return ENOBUFS; 1610 } 1611 1612 /* Attach the buffer to the mbuf */ 1613 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1614 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1615 } else { 1616 /* 1617 * We're re-using a previously allocated mbuf; 1618 * be sure to re-init pointers and lengths to 1619 * default values. 1620 */ 1621 m_new = m; 1622 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1623 m_new->m_data = m_new->m_ext.ext_buf; 1624 } 1625 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1626 if (align != 0) { 1627 DPRINTFN(1,("align = %d\n", align)); 1628 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1629 } 1630 1631 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1632 r = c->mvgbe_desc; 1633 c->mvgbe_mbuf = m_new; 1634 offset = (vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf; 1635 r->bufptr = dmamap->dm_segs[0].ds_addr + offset; 1636 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1637 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1638 1639 /* Invalidate RX buffer */ 1640 bus_dmamap_sync(sc->sc_dmat, dmamap, offset, r->bufsize, 1641 BUS_DMASYNC_PREREAD); 1642 1643 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1644 1645 return 0; 1646 } 1647 1648 /* 1649 * Memory management for jumbo frames. 1650 */ 1651 1652 static int 1653 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1654 { 1655 char *ptr, *kva; 1656 bus_dma_segment_t seg; 1657 int i, rseg, state, error; 1658 struct mvgbe_jpool_entry *entry; 1659 1660 state = error = 0; 1661 1662 /* Grab a big chunk o' storage. */ 1663 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1664 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1665 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1666 return ENOBUFS; 1667 } 1668 1669 state = 1; 1670 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1671 (void **)&kva, BUS_DMA_NOWAIT)) { 1672 aprint_error_dev(sc->sc_dev, 1673 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1674 error = ENOBUFS; 1675 goto out; 1676 } 1677 1678 state = 2; 1679 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1680 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1681 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1682 error = ENOBUFS; 1683 goto out; 1684 } 1685 1686 state = 3; 1687 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1688 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1689 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1690 error = ENOBUFS; 1691 goto out; 1692 } 1693 1694 state = 4; 1695 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1696 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1697 1698 LIST_INIT(&sc->sc_jfree_listhead); 1699 LIST_INIT(&sc->sc_jinuse_listhead); 1700 1701 /* 1702 * Now divide it up into 9K pieces and save the addresses 1703 * in an array. 1704 */ 1705 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1706 for (i = 0; i < MVGBE_JSLOTS; i++) { 1707 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1708 ptr += MVGBE_JLEN; 1709 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1710 if (entry == NULL) { 1711 aprint_error_dev(sc->sc_dev, 1712 "no memory for jumbo buffer queue!\n"); 1713 error = ENOBUFS; 1714 goto out; 1715 } 1716 entry->slot = i; 1717 if (i) 1718 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1719 jpool_entries); 1720 else 1721 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1722 jpool_entries); 1723 } 1724 out: 1725 if (error != 0) { 1726 switch (state) { 1727 case 4: 1728 bus_dmamap_unload(sc->sc_dmat, 1729 sc->sc_cdata.mvgbe_rx_jumbo_map); 1730 case 3: 1731 bus_dmamap_destroy(sc->sc_dmat, 1732 sc->sc_cdata.mvgbe_rx_jumbo_map); 1733 case 2: 1734 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1735 case 1: 1736 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1737 break; 1738 default: 1739 break; 1740 } 1741 } 1742 1743 return error; 1744 } 1745 1746 /* 1747 * Allocate a jumbo buffer. 1748 */ 1749 static void * 1750 mvgbe_jalloc(struct mvgbe_softc *sc) 1751 { 1752 struct mvgbe_jpool_entry *entry; 1753 1754 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1755 1756 if (entry == NULL) 1757 return NULL; 1758 1759 LIST_REMOVE(entry, jpool_entries); 1760 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1761 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1762 } 1763 1764 /* 1765 * Release a jumbo buffer. 1766 */ 1767 static void 1768 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1769 { 1770 struct mvgbe_jpool_entry *entry; 1771 struct mvgbe_softc *sc; 1772 int i, s; 1773 1774 /* Extract the softc struct pointer. */ 1775 sc = (struct mvgbe_softc *)arg; 1776 1777 if (sc == NULL) 1778 panic("%s: can't find softc pointer!", __func__); 1779 1780 /* calculate the slot this buffer belongs to */ 1781 1782 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1783 1784 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1785 panic("%s: asked to free buffer that we don't manage!", 1786 __func__); 1787 1788 s = splvm(); 1789 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1790 if (entry == NULL) 1791 panic("%s: buffer not in use!", __func__); 1792 entry->slot = i; 1793 LIST_REMOVE(entry, jpool_entries); 1794 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1795 1796 if (__predict_true(m != NULL)) 1797 pool_cache_put(mb_cache, m); 1798 splx(s); 1799 } 1800 1801 static int 1802 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1803 uint32_t *txidx) 1804 { 1805 struct mvgbe_tx_desc *f = NULL; 1806 struct mvgbe_txmap_entry *entry; 1807 bus_dma_segment_t *txseg; 1808 bus_dmamap_t txmap; 1809 uint32_t first, current, last, cmdsts; 1810 int m_csumflags, i; 1811 bool needs_defrag = false; 1812 1813 DPRINTFN(3, ("mvgbe_encap\n")); 1814 1815 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1816 if (entry == NULL) { 1817 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1818 return ENOBUFS; 1819 } 1820 txmap = entry->dmamap; 1821 1822 first = current = last = *txidx; 1823 1824 /* 1825 * Preserve m_pkthdr.csum_flags here since m_head might be 1826 * updated by m_defrag() 1827 */ 1828 m_csumflags = m_head->m_pkthdr.csum_flags; 1829 1830 do_defrag: 1831 if (__predict_false(needs_defrag == true)) { 1832 /* A small unaligned segment was detected. */ 1833 struct mbuf *m_new; 1834 m_new = m_defrag(m_head, M_DONTWAIT); 1835 if (m_new == NULL) 1836 return EFBIG; 1837 m_head = m_new; 1838 } 1839 1840 /* 1841 * Start packing the mbufs in this chain into 1842 * the fragment pointers. Stop when we run out 1843 * of fragments or hit the end of the mbuf chain. 1844 */ 1845 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1846 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1847 return ENOBUFS; 1848 } 1849 1850 txseg = txmap->dm_segs; 1851 1852 if (__predict_true(needs_defrag == false)) { 1853 /* 1854 * Detect rarely encountered DMA limitation. 1855 */ 1856 for (i = 0; i < txmap->dm_nsegs; i++) { 1857 if (((txseg[i].ds_addr & 7) != 0) && 1858 (txseg[i].ds_len <= 8) && 1859 (txseg[i].ds_len >= 1) 1860 ) { 1861 txseg = NULL; 1862 bus_dmamap_unload(sc->sc_dmat, txmap); 1863 needs_defrag = true; 1864 goto do_defrag; 1865 } 1866 } 1867 } 1868 1869 /* Sync the DMA map. */ 1870 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1871 BUS_DMASYNC_PREWRITE); 1872 1873 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1874 MVGBE_TX_RING_CNT) { 1875 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1876 bus_dmamap_unload(sc->sc_dmat, txmap); 1877 return ENOBUFS; 1878 } 1879 1880 1881 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1882 1883 for (i = 0; i < txmap->dm_nsegs; i++) { 1884 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1885 f->bufptr = txseg[i].ds_addr; 1886 f->bytecnt = txseg[i].ds_len; 1887 if (i != 0) 1888 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1889 last = current; 1890 current = MVGBE_TX_RING_NEXT(current); 1891 } 1892 1893 cmdsts = sc->sc_cmdsts_opts; 1894 if (m_csumflags & M_CSUM_IPv4) 1895 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1896 if (m_csumflags & M_CSUM_TCPv4) 1897 cmdsts |= 1898 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1899 if (m_csumflags & M_CSUM_UDPv4) 1900 cmdsts |= 1901 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1902 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1903 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1904 1905 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1906 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1907 } 1908 if (txmap->dm_nsegs == 1) 1909 f->cmdsts = cmdsts | 1910 MVGBE_TX_ENABLE_INTERRUPT | 1911 MVGBE_TX_ZERO_PADDING | 1912 MVGBE_TX_FIRST_DESC | 1913 MVGBE_TX_LAST_DESC; 1914 else { 1915 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1916 f->cmdsts = cmdsts | MVGBE_TX_FIRST_DESC; 1917 1918 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1919 f->cmdsts = 1920 MVGBE_BUFFER_OWNED_BY_DMA | 1921 MVGBE_TX_ENABLE_INTERRUPT | 1922 MVGBE_TX_ZERO_PADDING | 1923 MVGBE_TX_LAST_DESC; 1924 1925 /* Sync descriptors except first */ 1926 MVGBE_CDTXSYNC(sc, 1927 (MVGBE_TX_RING_CNT - 1 == *txidx) ? 0 : (*txidx) + 1, 1928 txmap->dm_nsegs - 1, 1929 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1930 } 1931 1932 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1933 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1934 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1935 1936 /* Finally, sync first descriptor */ 1937 sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |= 1938 MVGBE_BUFFER_OWNED_BY_DMA; 1939 MVGBE_CDTXSYNC(sc, *txidx, 1, 1940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1941 1942 sc->sc_cdata.mvgbe_tx_cnt += i; 1943 *txidx = current; 1944 1945 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1946 1947 return 0; 1948 } 1949 1950 static void 1951 mvgbe_rxeof(struct mvgbe_softc *sc) 1952 { 1953 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1954 struct mvgbe_rx_desc *cur_rx; 1955 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1956 struct mbuf *m; 1957 bus_dmamap_t dmamap; 1958 uint32_t rxstat; 1959 uint16_t bufsize; 1960 int idx, cur, total_len; 1961 1962 idx = sc->sc_cdata.mvgbe_rx_prod; 1963 1964 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1965 1966 for (;;) { 1967 cur = idx; 1968 1969 /* Sync the descriptor */ 1970 MVGBE_CDRXSYNC(sc, idx, 1971 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1972 1973 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1974 1975 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1976 MVGBE_BUFFER_OWNED_BY_DMA) { 1977 /* Invalidate the descriptor -- it's not ready yet */ 1978 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1979 sc->sc_cdata.mvgbe_rx_prod = idx; 1980 break; 1981 } 1982 #ifdef DIAGNOSTIC 1983 if ((cur_rx->cmdsts & 1984 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1985 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1986 panic( 1987 "mvgbe_rxeof: buffer size is smaller than packet"); 1988 #endif 1989 1990 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1991 1992 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1993 BUS_DMASYNC_POSTREAD); 1994 1995 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1996 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1997 total_len = cur_rx->bytecnt - ETHER_CRC_LEN; 1998 rxstat = cur_rx->cmdsts; 1999 bufsize = cur_rx->bufsize; 2000 2001 cdata->mvgbe_rx_map[idx] = NULL; 2002 2003 idx = MVGBE_RX_RING_NEXT(idx); 2004 2005 if (rxstat & MVGBE_ERROR_SUMMARY) { 2006 #if 0 2007 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 2008 2009 if (err == MVGBE_RX_CRC_ERROR) 2010 ifp->if_ierrors++; 2011 if (err == MVGBE_RX_OVERRUN_ERROR) 2012 ifp->if_ierrors++; 2013 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 2014 ifp->if_ierrors++; 2015 if (err == MVGBE_RX_RESOURCE_ERROR) 2016 ifp->if_ierrors++; 2017 #else 2018 ifp->if_ierrors++; 2019 #endif 2020 mvgbe_newbuf(sc, cur, m, dmamap); 2021 continue; 2022 } 2023 2024 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 2025 int flgs = 0; 2026 2027 /* Check IPv4 header checksum */ 2028 flgs |= M_CSUM_IPv4; 2029 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 2030 flgs |= M_CSUM_IPv4_BAD; 2031 else if ((bufsize & MVGBE_RX_IP_FRAGMENT) == 0) { 2032 /* 2033 * Check TCPv4/UDPv4 checksum for 2034 * non-fragmented packet only. 2035 * 2036 * It seemd that sometimes 2037 * MVGBE_RX_L4_CHECKSUM_OK bit was set to 0 2038 * even if the checksum is correct and the 2039 * packet was not fragmented. So we don't set 2040 * M_CSUM_TCP_UDP_BAD even if csum bit is 0. 2041 */ 2042 2043 if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2044 MVGBE_RX_L4_TYPE_TCP) && 2045 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2046 flgs |= M_CSUM_TCPv4; 2047 else if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 2048 MVGBE_RX_L4_TYPE_UDP) && 2049 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 2050 flgs |= M_CSUM_UDPv4; 2051 } 2052 m->m_pkthdr.csum_flags = flgs; 2053 } 2054 2055 /* 2056 * Try to allocate a new jumbo buffer. If that 2057 * fails, copy the packet to mbufs and put the 2058 * jumbo buffer back in the ring so it can be 2059 * re-used. If allocating mbufs fails, then we 2060 * have to drop the packet. 2061 */ 2062 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 2063 struct mbuf *m0; 2064 2065 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 2066 mvgbe_newbuf(sc, cur, m, dmamap); 2067 if (m0 == NULL) { 2068 aprint_error_ifnet(ifp, 2069 "no receive buffers available --" 2070 " packet dropped!\n"); 2071 ifp->if_ierrors++; 2072 continue; 2073 } 2074 m = m0; 2075 } else { 2076 m_set_rcvif(m, ifp); 2077 m->m_pkthdr.len = m->m_len = total_len; 2078 } 2079 2080 /* Skip on first 2byte (HW header) */ 2081 m_adj(m, MVGBE_HWHEADER_SIZE); 2082 2083 ifp->if_ipackets++; 2084 2085 bpf_mtap(ifp, m); 2086 2087 /* pass it on. */ 2088 if_percpuq_enqueue(ifp->if_percpuq, m); 2089 } 2090 } 2091 2092 static void 2093 mvgbe_txeof(struct mvgbe_softc *sc) 2094 { 2095 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 2096 struct mvgbe_tx_desc *cur_tx; 2097 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2098 struct mvgbe_txmap_entry *entry; 2099 int idx; 2100 2101 DPRINTFN(3, ("mvgbe_txeof\n")); 2102 2103 /* 2104 * Go through our tx ring and free mbufs for those 2105 * frames that have been sent. 2106 */ 2107 idx = cdata->mvgbe_tx_cons; 2108 while (idx != cdata->mvgbe_tx_prod) { 2109 MVGBE_CDTXSYNC(sc, idx, 1, 2110 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2111 2112 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 2113 #ifdef MVGBE_DEBUG 2114 if (mvgbe_debug >= 3) 2115 mvgbe_dump_txdesc(cur_tx, idx); 2116 #endif 2117 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 2118 MVGBE_BUFFER_OWNED_BY_DMA) { 2119 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 2120 break; 2121 } 2122 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 2123 ifp->if_opackets++; 2124 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 2125 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 2126 2127 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 2128 ifp->if_collisions++; 2129 if (err == MVGBE_TX_UNDERRUN_ERROR) 2130 ifp->if_oerrors++; 2131 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 2132 ifp->if_collisions++; 2133 } 2134 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 2135 entry = cdata->mvgbe_tx_map[idx]; 2136 2137 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 2138 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 2139 2140 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 2141 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2142 2143 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 2144 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 2145 cdata->mvgbe_tx_map[idx] = NULL; 2146 } 2147 cdata->mvgbe_tx_cnt--; 2148 idx = MVGBE_TX_RING_NEXT(idx); 2149 } 2150 if (cdata->mvgbe_tx_cnt == 0) 2151 ifp->if_timer = 0; 2152 2153 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 2154 ifp->if_flags &= ~IFF_OACTIVE; 2155 2156 cdata->mvgbe_tx_cons = idx; 2157 } 2158 2159 static uint8_t 2160 mvgbe_crc8(const uint8_t *data, size_t size) 2161 { 2162 int bit; 2163 uint8_t byte; 2164 uint8_t crc = 0; 2165 const uint8_t poly = 0x07; 2166 2167 while(size--) 2168 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2169 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2170 2171 return crc; 2172 } 2173 2174 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 2175 2176 static void 2177 mvgbe_filter_setup(struct mvgbe_softc *sc) 2178 { 2179 struct ethercom *ec = &sc->sc_ethercom; 2180 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2181 struct ether_multi *enm; 2182 struct ether_multistep step; 2183 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT]; 2184 uint32_t pxc; 2185 int i; 2186 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2187 2188 memset(dfut, 0, sizeof(dfut)); 2189 memset(dfsmt, 0, sizeof(dfsmt)); 2190 memset(dfomt, 0, sizeof(dfomt)); 2191 2192 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2193 goto allmulti; 2194 } 2195 2196 ETHER_FIRST_MULTI(step, ec, enm); 2197 while (enm != NULL) { 2198 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2199 /* ranges are complex and somewhat rare */ 2200 goto allmulti; 2201 } 2202 /* chip handles some IPv4 multicast specially */ 2203 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2204 i = enm->enm_addrlo[5]; 2205 dfsmt[i>>2] |= 2206 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2207 } else { 2208 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2209 dfomt[i>>2] |= 2210 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2211 } 2212 2213 ETHER_NEXT_MULTI(step, enm); 2214 } 2215 goto set; 2216 2217 allmulti: 2218 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2219 for (i = 0; i < MVGBE_NDFSMT; i++) { 2220 dfsmt[i] = dfomt[i] = 2221 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2222 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2223 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2224 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2225 } 2226 } 2227 2228 set: 2229 pxc = MVGBE_READ(sc, MVGBE_PXC); 2230 pxc &= ~MVGBE_PXC_UPM; 2231 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 2232 if (ifp->if_flags & IFF_BROADCAST) { 2233 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 2234 } 2235 if (ifp->if_flags & IFF_PROMISC) { 2236 pxc |= MVGBE_PXC_UPM; 2237 } 2238 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 2239 2240 /* Set Destination Address Filter Unicast Table */ 2241 if (ifp->if_flags & IFF_PROMISC) { 2242 /* pass all unicast addresses */ 2243 for (i = 0; i < MVGBE_NDFUT; i++) { 2244 dfut[i] = 2245 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2246 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2247 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 2248 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2249 } 2250 } else { 2251 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2252 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2253 } 2254 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 2255 2256 /* Set Destination Address Filter Multicast Tables */ 2257 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 2258 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 2259 } 2260 2261 #ifdef MVGBE_DEBUG 2262 static void 2263 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 2264 { 2265 #define DESC_PRINT(X) \ 2266 if (X) \ 2267 printf("txdesc[%d]." #X "=%#x\n", idx, X); 2268 2269 #if BYTE_ORDER == BIG_ENDIAN 2270 DESC_PRINT(desc->bytecnt); 2271 DESC_PRINT(desc->l4ichk); 2272 DESC_PRINT(desc->cmdsts); 2273 DESC_PRINT(desc->nextdescptr); 2274 DESC_PRINT(desc->bufptr); 2275 #else /* LITTLE_ENDIAN */ 2276 DESC_PRINT(desc->cmdsts); 2277 DESC_PRINT(desc->l4ichk); 2278 DESC_PRINT(desc->bytecnt); 2279 DESC_PRINT(desc->bufptr); 2280 DESC_PRINT(desc->nextdescptr); 2281 #endif 2282 #undef DESC_PRINT 2283 } 2284 #endif 2285 2286 SYSCTL_SETUP(sysctl_mvgbe, "sysctl mvgbe subtree setup") 2287 { 2288 int rc; 2289 const struct sysctlnode *node; 2290 2291 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2292 0, CTLTYPE_NODE, "mvgbe", 2293 SYSCTL_DESCR("mvgbe interface controls"), 2294 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2295 goto err; 2296 } 2297 2298 mvgbe_root_num = node->sysctl_num; 2299 return; 2300 2301 err: 2302 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2303 } 2304 2305 static void 2306 sysctl_mvgbe_init(struct mvgbe_softc *sc) 2307 { 2308 const struct sysctlnode *node; 2309 int mvgbe_nodenum; 2310 2311 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2312 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 2313 SYSCTL_DESCR("mvgbe per-controller controls"), 2314 NULL, 0, NULL, 0, CTL_HW, mvgbe_root_num, CTL_CREATE, 2315 CTL_EOL) != 0) { 2316 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 2317 return; 2318 } 2319 mvgbe_nodenum = node->sysctl_num; 2320 2321 /* interrupt moderation sysctls */ 2322 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2323 CTLFLAG_READWRITE, CTLTYPE_INT, "ipginttx", 2324 SYSCTL_DESCR("mvgbe TX interrupt moderation timer"), 2325 mvgbe_sysctl_ipginttx, 0, (void *)sc, 2326 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2327 CTL_EOL) != 0) { 2328 aprint_normal_dev(sc->sc_dev, 2329 "couldn't create ipginttx sysctl node\n"); 2330 } 2331 if (sysctl_createv(&sc->mvgbe_clog, 0, NULL, &node, 2332 CTLFLAG_READWRITE, CTLTYPE_INT, "ipgintrx", 2333 SYSCTL_DESCR("mvgbe RX interrupt moderation timer"), 2334 mvgbe_sysctl_ipgintrx, 0, (void *)sc, 2335 0, CTL_HW, mvgbe_root_num, mvgbe_nodenum, CTL_CREATE, 2336 CTL_EOL) != 0) { 2337 aprint_normal_dev(sc->sc_dev, 2338 "couldn't create ipginttx sysctl node\n"); 2339 } 2340 } 2341 2342 static int 2343 mvgbe_sysctl_ipginttx(SYSCTLFN_ARGS) 2344 { 2345 int error; 2346 unsigned int t; 2347 struct sysctlnode node; 2348 struct mvgbec_softc *csc; 2349 struct mvgbe_softc *sc; 2350 2351 node = *rnode; 2352 sc = node.sysctl_data; 2353 csc = device_private(device_parent(sc->sc_dev)); 2354 t = sc->sc_ipginttx; 2355 node.sysctl_data = &t; 2356 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2357 if (error || newp == NULL) 2358 return error; 2359 2360 if (mvgbe_ipginttx(csc, sc, t) < 0) 2361 return EINVAL; 2362 /* 2363 * update the softc with sysctl-changed value, and mark 2364 * for hardware update 2365 */ 2366 sc->sc_ipginttx = t; 2367 2368 return 0; 2369 } 2370 2371 static int 2372 mvgbe_sysctl_ipgintrx(SYSCTLFN_ARGS) 2373 { 2374 int error; 2375 unsigned int t; 2376 struct sysctlnode node; 2377 struct mvgbec_softc *csc; 2378 struct mvgbe_softc *sc; 2379 2380 node = *rnode; 2381 sc = node.sysctl_data; 2382 csc = device_private(device_parent(sc->sc_dev)); 2383 t = sc->sc_ipgintrx; 2384 node.sysctl_data = &t; 2385 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2386 if (error || newp == NULL) 2387 return error; 2388 2389 if (mvgbe_ipgintrx(csc, sc, t) < 0) 2390 return EINVAL; 2391 /* 2392 * update the softc with sysctl-changed value, and mark 2393 * for hardware update 2394 */ 2395 sc->sc_ipgintrx = t; 2396 2397 return 0; 2398 } 2399