1 /* $NetBSD: if_gfe.c,v 1.49 2018/06/26 06:48:01 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.49 2018/06/26 06:48:01 msaitoh Exp $"); 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/bus.h> 51 #include <sys/callout.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/ioctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/mutex.h> 57 #include <sys/socket.h> 58 59 #include <uvm/uvm.h> 60 #include <net/if.h> 61 #include <net/if_dl.h> 62 #include <net/if_ether.h> 63 #include <net/if_media.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/if_inarp.h> 68 #endif 69 #include <net/bpf.h> 70 #include <sys/rndsource.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/marvell/gtreg.h> 76 #include <dev/marvell/gtvar.h> 77 #include <dev/marvell/gtethreg.h> 78 #include <dev/marvell/if_gfevar.h> 79 #include <dev/marvell/marvellreg.h> 80 #include <dev/marvell/marvellvar.h> 81 82 #include <prop/proplib.h> 83 84 #include "locators.h" 85 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) \ 100 do { \ 101 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 102 printf a; \ 103 } while (0 /* CONSTCOND */) 104 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 105 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 106 #else 107 #define GE_DPRINTF(sc, a) do { } while (0) 108 #define GE_FUNC_ENTER(sc, func) do { } while (0) 109 #define GE_FUNC_EXIT(sc, str) do { } while (0) 110 #endif 111 enum gfe_whack_op { 112 GE_WHACK_START, GE_WHACK_RESTART, 113 GE_WHACK_CHANGE, GE_WHACK_STOP 114 }; 115 116 enum gfe_hash_op { 117 GE_HASH_ADD, GE_HASH_REMOVE, 118 }; 119 120 #if 1 121 #define htogt32(a) htobe32(a) 122 #define gt32toh(a) be32toh(a) 123 #else 124 #define htogt32(a) htole32(a) 125 #define gt32toh(a) le32toh(a) 126 #endif 127 128 #define GE_RXDSYNC(sc, rxq, n, ops) \ 129 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 130 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 131 (ops)) 132 #define GE_RXDPRESYNC(sc, rxq, n) \ 133 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 134 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 135 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 136 137 #define GE_TXDSYNC(sc, txq, n, ops) \ 138 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 139 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 140 (ops)) 141 #define GE_TXDPRESYNC(sc, txq, n) \ 142 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 143 #define GE_TXDPOSTSYNC(sc, txq, n) \ 144 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 145 146 #define STATIC 147 148 149 STATIC int gfec_match(device_t, cfdata_t, void *); 150 STATIC void gfec_attach(device_t, device_t, void *); 151 152 STATIC int gfec_print(void *, const char *); 153 STATIC int gfec_search(device_t, cfdata_t, const int *, void *); 154 155 STATIC int gfec_enet_phy(device_t, int); 156 STATIC int gfec_mii_read(device_t, int, int); 157 STATIC void gfec_mii_write(device_t, int, int, int); 158 STATIC void gfec_mii_statchg(struct ifnet *); 159 160 STATIC int gfe_match(device_t, cfdata_t, void *); 161 STATIC void gfe_attach(device_t, device_t, void *); 162 163 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 164 size_t, int); 165 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 166 167 STATIC int gfe_ifioctl(struct ifnet *, u_long, void *); 168 STATIC void gfe_ifstart(struct ifnet *); 169 STATIC void gfe_ifwatchdog(struct ifnet *); 170 171 STATIC void gfe_tick(void *arg); 172 173 STATIC void gfe_tx_restart(void *); 174 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 175 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 176 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 177 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 178 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 179 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 180 181 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 182 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 183 STATIC int gfe_rx_prime(struct gfe_softc *); 184 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 185 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 186 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 187 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 188 189 STATIC int gfe_intr(void *); 190 191 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 192 193 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 194 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 195 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 196 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 197 u_long); 198 STATIC int gfe_hash_fill(struct gfe_softc *); 199 STATIC int gfe_hash_alloc(struct gfe_softc *); 200 201 202 CFATTACH_DECL_NEW(gfec, sizeof(struct gfec_softc), 203 gfec_match, gfec_attach, NULL, NULL); 204 CFATTACH_DECL_NEW(gfe, sizeof(struct gfe_softc), 205 gfe_match, gfe_attach, NULL, NULL); 206 207 208 /* ARGSUSED */ 209 int 210 gfec_match(device_t parent, cfdata_t cf, void *aux) 211 { 212 struct marvell_attach_args *mva = aux; 213 214 if (strcmp(mva->mva_name, cf->cf_name) != 0) 215 return 0; 216 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 217 return 0; 218 219 mva->mva_size = ETHC_SIZE; 220 return 1; 221 } 222 223 /* ARGSUSED */ 224 void 225 gfec_attach(device_t parent, device_t self, void *aux) 226 { 227 struct gfec_softc *sc = device_private(self); 228 struct marvell_attach_args *mva = aux, gfea; 229 static int gfe_irqs[] = { 32, 33, 34 }; 230 int i; 231 232 aprint_naive("\n"); 233 aprint_normal(": Ethernet Controller\n"); 234 235 sc->sc_dev = self; 236 sc->sc_iot = mva->mva_iot; 237 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 238 mva->mva_size, &sc->sc_ioh)) { 239 aprint_error_dev(self, "Cannot map registers\n"); 240 return; 241 } 242 243 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 244 245 for (i = 0; i < ETH_NUM; i++) { 246 gfea.mva_name = "gfe"; 247 gfea.mva_model = mva->mva_model; 248 gfea.mva_iot = sc->sc_iot; 249 gfea.mva_ioh = sc->sc_ioh; 250 gfea.mva_unit = i; 251 gfea.mva_dmat = mva->mva_dmat; 252 gfea.mva_irq = gfe_irqs[i]; 253 config_found_sm_loc(sc->sc_dev, "gfec", NULL, &gfea, 254 gfec_print, gfec_search); 255 } 256 } 257 258 int 259 gfec_print(void *aux, const char *pnp) 260 { 261 struct marvell_attach_args *gfea = aux; 262 263 if (pnp) 264 aprint_normal("%s at %s port %d", 265 gfea->mva_name, pnp, gfea->mva_unit); 266 else { 267 if (gfea->mva_unit != GFECCF_PORT_DEFAULT) 268 aprint_normal(" port %d", gfea->mva_unit); 269 if (gfea->mva_irq != GFECCF_IRQ_DEFAULT) 270 aprint_normal(" irq %d", gfea->mva_irq); 271 } 272 return UNCONF; 273 } 274 275 /* ARGSUSED */ 276 int 277 gfec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 278 { 279 struct marvell_attach_args *gfea = aux; 280 281 if (cf->cf_loc[GFECCF_PORT] == gfea->mva_unit && 282 cf->cf_loc[GFECCF_IRQ] != GFECCF_IRQ_DEFAULT) 283 gfea->mva_irq = cf->cf_loc[GFECCF_IRQ]; 284 285 return config_match(parent, cf, aux); 286 } 287 288 int 289 gfec_enet_phy(device_t dev, int unit) 290 { 291 struct gfec_softc *sc = device_private(dev); 292 uint32_t epar; 293 294 epar = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ETH_EPAR); 295 return ETH_EPAR_PhyAD_GET(epar, unit); 296 } 297 298 int 299 gfec_mii_read(device_t dev, int phy, int reg) 300 { 301 struct gfec_softc *csc = device_private(device_parent(dev)); 302 uint32_t data; 303 int count = 10000; 304 305 mutex_enter(&csc->sc_mtx); 306 307 do { 308 DELAY(10); 309 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 310 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 311 312 if (count == 0) { 313 aprint_error_dev(dev, 314 "mii read for phy %d reg %d busied out\n", phy, reg); 315 mutex_exit(&csc->sc_mtx); 316 return ETH_ESMIR_Value_GET(data); 317 } 318 319 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 320 ETH_ESMIR_READ(phy, reg)); 321 322 count = 10000; 323 do { 324 DELAY(10); 325 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 326 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 327 328 mutex_exit(&csc->sc_mtx); 329 330 if (count == 0) 331 aprint_error_dev(dev, 332 "mii read for phy %d reg %d timed out\n", phy, reg); 333 #if defined(GTMIIDEBUG) 334 aprint_normal_dev(dev, "mii_read(%d, %d): %#x data %#x\n", 335 phy, reg, data, ETH_ESMIR_Value_GET(data)); 336 #endif 337 return ETH_ESMIR_Value_GET(data); 338 } 339 340 void 341 gfec_mii_write (device_t dev, int phy, int reg, int value) 342 { 343 struct gfec_softc *csc = device_private(device_parent(dev)); 344 uint32_t data; 345 int count = 10000; 346 347 mutex_enter(&csc->sc_mtx); 348 349 do { 350 DELAY(10); 351 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 352 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 353 354 if (count == 0) { 355 aprint_error_dev(dev, 356 "mii write for phy %d reg %d busied out (busy)\n", 357 phy, reg); 358 mutex_exit(&csc->sc_mtx); 359 return; 360 } 361 362 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 363 ETH_ESMIR_WRITE(phy, reg, value)); 364 365 count = 10000; 366 do { 367 DELAY(10); 368 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 369 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 370 371 mutex_exit(&csc->sc_mtx); 372 373 if (count == 0) 374 aprint_error_dev(dev, 375 "mii write for phy %d reg %d timed out\n", phy, reg); 376 #if defined(GTMIIDEBUG) 377 aprint_normal_dev(dev, "mii_write(%d, %d, %#x)\n", phy, reg, value); 378 #endif 379 } 380 381 void 382 gfec_mii_statchg(struct ifnet *ifp) 383 { 384 /* struct gfe_softc *sc = ifp->if_softc; */ 385 /* do nothing? */ 386 } 387 388 /* ARGSUSED */ 389 int 390 gfe_match(device_t parent, cfdata_t cf, void *aux) 391 { 392 393 return 1; 394 } 395 396 /* ARGSUSED */ 397 void 398 gfe_attach(device_t parent, device_t self, void *aux) 399 { 400 struct marvell_attach_args *mva = aux; 401 struct gfe_softc * const sc = device_private(self); 402 struct ifnet * const ifp = &sc->sc_ec.ec_if; 403 uint32_t sdcr; 404 int phyaddr, error; 405 prop_data_t ea; 406 uint8_t enaddr[6]; 407 408 aprint_naive("\n"); 409 aprint_normal(": Ethernet Controller\n"); 410 411 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 412 mva->mva_offset, mva->mva_size, &sc->sc_memh)) { 413 aprint_error_dev(self, "failed to map registers\n"); 414 return; 415 } 416 sc->sc_dev = self; 417 sc->sc_memt = mva->mva_iot; 418 sc->sc_dmat = mva->mva_dmat; 419 sc->sc_macno = (mva->mva_offset == ETH_BASE(0)) ? 0 : 420 ((mva->mva_offset == ETH_BASE(1)) ? 1 : 2); 421 422 callout_init(&sc->sc_co, 0); 423 424 phyaddr = gfec_enet_phy(parent, sc->sc_macno); 425 426 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-addr"); 427 if (ea != NULL) { 428 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 429 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 430 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 431 } 432 433 sc->sc_pcr = GE_READ(sc, ETH_EPCR); 434 sc->sc_pcxr = GE_READ(sc, ETH_EPCXR); 435 sc->sc_intrmask = GE_READ(sc, ETH_EIMR) | ETH_IR_MIIPhySTC; 436 437 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 438 439 #if defined(DEBUG) 440 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 441 #endif 442 443 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 444 if (device_cfdata(self)->cf_flags & 1) { 445 aprint_normal_dev(self, "phy %d (rmii)\n", phyaddr); 446 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 447 } else { 448 aprint_normal_dev(self, "phy %d (mii)\n", phyaddr); 449 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 450 } 451 if (device_cfdata(self)->cf_flags & 2) 452 sc->sc_flags |= GE_NOFREE; 453 /* Set Max Frame Length is 1536 */ 454 sc->sc_pcxr &= ~ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_MASK); 455 sc->sc_pcxr |= ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_1536); 456 sc->sc_max_frame_length = 1536; 457 458 if (sc->sc_pcr & ETH_EPCR_EN) { 459 int tries = 1000; 460 /* 461 * Abort transmitter and receiver and wait for them to quiese 462 */ 463 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR | ETH_ESDCMR_AT); 464 do { 465 delay(100); 466 if (tries-- <= 0) { 467 aprint_error_dev(self, "Abort TX/RX failed\n"); 468 break; 469 } 470 } while (GE_READ(sc, ETH_ESDCMR) & 471 (ETH_ESDCMR_AR | ETH_ESDCMR_AT)); 472 } 473 474 sc->sc_pcr &= 475 ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 476 477 #if defined(DEBUG) 478 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 479 #endif 480 481 /* 482 * Now turn off the GT. If it didn't quiese, too ***ing bad. 483 */ 484 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 485 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 486 sdcr = GE_READ(sc, ETH_ESDCR); 487 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 488 sdcr |= ETH_ESDCR_RIFB; 489 GE_WRITE(sc, ETH_ESDCR, sdcr); 490 491 sc->sc_mii.mii_ifp = ifp; 492 sc->sc_mii.mii_readreg = gfec_mii_read; 493 sc->sc_mii.mii_writereg = gfec_mii_write; 494 sc->sc_mii.mii_statchg = gfec_mii_statchg; 495 496 sc->sc_ec.ec_mii = &sc->sc_mii; 497 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 498 ether_mediastatus); 499 500 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 501 MII_OFFSET_ANY, MIIF_NOISOLATE); 502 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 503 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 504 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 505 } else { 506 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 507 } 508 509 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 510 ifp->if_softc = sc; 511 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 512 #if 0 513 ifp->if_flags |= IFF_DEBUG; 514 #endif 515 ifp->if_ioctl = gfe_ifioctl; 516 ifp->if_start = gfe_ifstart; 517 ifp->if_watchdog = gfe_ifwatchdog; 518 519 if (sc->sc_flags & GE_NOFREE) { 520 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 521 if (!error) 522 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 523 if (!error) 524 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 525 if (!error) 526 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 527 if (!error) 528 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 529 if (!error) 530 error = gfe_hash_alloc(sc); 531 if (error) 532 aprint_error_dev(self, 533 "failed to allocate resources: %d\n", error); 534 } 535 536 if_attach(ifp); 537 ether_ifattach(ifp, enaddr); 538 bpf_attach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 539 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 540 RND_FLAG_DEFAULT); 541 marvell_intr_establish(mva->mva_irq, IPL_NET, gfe_intr, sc); 542 } 543 544 int 545 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 546 size_t size, int flags) 547 { 548 int error = 0; 549 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 550 551 KASSERT(gdm->gdm_kva == NULL); 552 gdm->gdm_size = size; 553 gdm->gdm_maxsegs = maxsegs; 554 555 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 556 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 557 BUS_DMA_NOWAIT); 558 if (error) 559 goto fail; 560 561 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 562 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 563 if (error) 564 goto fail; 565 566 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 567 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 568 if (error) 569 goto fail; 570 571 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 572 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 573 if (error) 574 goto fail; 575 576 /* invalidate from cache */ 577 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 578 BUS_DMASYNC_PREREAD); 579 fail: 580 if (error) { 581 gfe_dmamem_free(sc, gdm); 582 GE_DPRINTF(sc, (":err=%d", error)); 583 } 584 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 585 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 586 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 587 GE_FUNC_EXIT(sc, ""); 588 return error; 589 } 590 591 void 592 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 593 { 594 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 595 if (gdm->gdm_map) 596 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 597 if (gdm->gdm_kva) 598 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 599 if (gdm->gdm_nsegs > 0) 600 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 601 gdm->gdm_map = NULL; 602 gdm->gdm_kva = NULL; 603 gdm->gdm_nsegs = 0; 604 GE_FUNC_EXIT(sc, ""); 605 } 606 607 int 608 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 609 { 610 struct gfe_softc * const sc = ifp->if_softc; 611 struct ifreq *ifr = (struct ifreq *) data; 612 struct ifaddr *ifa = (struct ifaddr *) data; 613 int s, error = 0; 614 615 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 616 s = splnet(); 617 618 switch (cmd) { 619 case SIOCINITIFADDR: 620 ifp->if_flags |= IFF_UP; 621 error = gfe_whack(sc, GE_WHACK_START); 622 switch (ifa->ifa_addr->sa_family) { 623 #ifdef INET 624 case AF_INET: 625 if (error == 0) 626 arp_ifinit(ifp, ifa); 627 break; 628 #endif 629 default: 630 break; 631 } 632 break; 633 634 case SIOCSIFFLAGS: 635 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 636 break; 637 /* XXX re-use ether_ioctl() */ 638 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 639 case IFF_UP|IFF_RUNNING:/* active->active, update */ 640 error = gfe_whack(sc, GE_WHACK_CHANGE); 641 break; 642 case IFF_RUNNING: /* not up, so we stop */ 643 error = gfe_whack(sc, GE_WHACK_STOP); 644 break; 645 case IFF_UP: /* not running, so we start */ 646 error = gfe_whack(sc, GE_WHACK_START); 647 break; 648 case 0: /* idle->idle: do nothing */ 649 break; 650 } 651 break; 652 653 case SIOCSIFMEDIA: 654 case SIOCGIFMEDIA: 655 case SIOCADDMULTI: 656 case SIOCDELMULTI: 657 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 658 if (ifp->if_flags & IFF_RUNNING) 659 error = gfe_whack(sc, GE_WHACK_CHANGE); 660 else 661 error = 0; 662 } 663 break; 664 665 case SIOCSIFMTU: 666 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 667 error = EINVAL; 668 break; 669 } 670 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 671 error = 0; 672 break; 673 674 default: 675 error = ether_ioctl(ifp, cmd, data); 676 break; 677 } 678 splx(s); 679 GE_FUNC_EXIT(sc, ""); 680 return error; 681 } 682 683 void 684 gfe_ifstart(struct ifnet *ifp) 685 { 686 struct gfe_softc * const sc = ifp->if_softc; 687 struct mbuf *m; 688 689 GE_FUNC_ENTER(sc, "gfe_ifstart"); 690 691 if ((ifp->if_flags & IFF_RUNNING) == 0) { 692 GE_FUNC_EXIT(sc, "$"); 693 return; 694 } 695 696 for (;;) { 697 IF_DEQUEUE(&ifp->if_snd, m); 698 if (m == NULL) { 699 ifp->if_flags &= ~IFF_OACTIVE; 700 GE_FUNC_EXIT(sc, ""); 701 return; 702 } 703 704 /* 705 * No space in the pending queue? try later. 706 */ 707 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 708 break; 709 710 /* 711 * Try to enqueue a mbuf to the device. If that fails, we 712 * can always try to map the next mbuf. 713 */ 714 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 715 GE_DPRINTF(sc, (">")); 716 #ifndef GE_NOTX 717 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 718 #endif 719 } 720 721 /* 722 * Attempt to queue the mbuf for send failed. 723 */ 724 IF_PREPEND(&ifp->if_snd, m); 725 ifp->if_flags |= IFF_OACTIVE; 726 GE_FUNC_EXIT(sc, "%%"); 727 } 728 729 void 730 gfe_ifwatchdog(struct ifnet *ifp) 731 { 732 struct gfe_softc * const sc = ifp->if_softc; 733 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 734 735 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 736 aprint_error_dev(sc->sc_dev, "device timeout"); 737 if (ifp->if_flags & IFF_RUNNING) { 738 uint32_t curtxdnum; 739 740 curtxdnum = (GE_READ(sc, txq->txq_ectdp) - 741 txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 742 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 743 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 744 aprint_error(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 745 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 746 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 747 GE_READ(sc, ETH_EICR)); 748 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 749 GE_TXDPRESYNC(sc, txq, curtxdnum); 750 } 751 aprint_error("\n"); 752 ifp->if_oerrors++; 753 (void) gfe_whack(sc, GE_WHACK_RESTART); 754 GE_FUNC_EXIT(sc, ""); 755 } 756 757 int 758 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 759 { 760 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 761 int error; 762 763 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 764 GE_DPRINTF(sc, ("(%d)", rxprio)); 765 766 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 767 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 768 if (error) { 769 GE_FUNC_EXIT(sc, "!!"); 770 return error; 771 } 772 773 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 774 GE_RXBUF_MEMSIZE, 0); 775 if (error) { 776 GE_FUNC_EXIT(sc, "!!!"); 777 return error; 778 } 779 GE_FUNC_EXIT(sc, ""); 780 return error; 781 } 782 783 int 784 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 785 { 786 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 787 volatile struct gt_eth_desc *rxd; 788 const bus_dma_segment_t *ds; 789 int idx; 790 bus_addr_t nxtaddr; 791 bus_size_t boff; 792 793 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 794 GE_DPRINTF(sc, ("(%d)", rxprio)); 795 796 if ((sc->sc_flags & GE_NOFREE) == 0) { 797 int error = gfe_rx_rxqalloc(sc, rxprio); 798 if (error) { 799 GE_FUNC_EXIT(sc, "!"); 800 return error; 801 } 802 } else { 803 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 804 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 805 } 806 807 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 808 809 rxq->rxq_descs = 810 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 811 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 812 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 813 rxq->rxq_fi = 0; 814 rxq->rxq_active = GE_RXDESC_MAX; 815 boff = 0; 816 ds = rxq->rxq_buf_mem.gdm_map->dm_segs; 817 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 818 for (idx = 0, rxd = rxq->rxq_descs; idx < GE_RXDESC_MAX; 819 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 820 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 821 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 822 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 823 /* 824 * update the nxtptr to point to the next txd. 825 */ 826 if (idx == GE_RXDESC_MAX - 1) 827 nxtaddr = rxq->rxq_desc_busaddr; 828 rxd->ed_nxtptr = htogt32(nxtaddr); 829 boff += GE_RXBUF_SIZE; 830 if (boff == ds->ds_len) { 831 ds++; 832 boff = 0; 833 } 834 } 835 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 836 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 837 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 838 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 839 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 840 BUS_DMASYNC_PREREAD); 841 842 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 843 switch (rxprio) { 844 case GE_RXPRIO_HI: 845 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 846 rxq->rxq_efrdp = ETH_EFRDP3; 847 rxq->rxq_ecrdp = ETH_ECRDP3; 848 break; 849 case GE_RXPRIO_MEDHI: 850 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 851 rxq->rxq_efrdp = ETH_EFRDP2; 852 rxq->rxq_ecrdp = ETH_ECRDP2; 853 break; 854 case GE_RXPRIO_MEDLO: 855 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 856 rxq->rxq_efrdp = ETH_EFRDP1; 857 rxq->rxq_ecrdp = ETH_ECRDP1; 858 break; 859 case GE_RXPRIO_LO: 860 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 861 rxq->rxq_efrdp = ETH_EFRDP0; 862 rxq->rxq_ecrdp = ETH_ECRDP0; 863 break; 864 } 865 GE_FUNC_EXIT(sc, ""); 866 return 0; 867 } 868 869 void 870 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 871 { 872 struct ifnet * const ifp = &sc->sc_ec.ec_if; 873 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 874 struct mbuf *m = rxq->rxq_curpkt; 875 876 GE_FUNC_ENTER(sc, "gfe_rx_get"); 877 GE_DPRINTF(sc, ("(%d)", rxprio)); 878 879 while (rxq->rxq_active > 0) { 880 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 881 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 882 const struct ether_header *eh; 883 unsigned int cmdsts; 884 size_t buflen; 885 886 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 887 cmdsts = gt32toh(rxd->ed_cmdsts); 888 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 889 rxq->rxq_cmdsts = cmdsts; 890 /* 891 * Sometimes the GE "forgets" to reset the ownership bit. 892 * But if the length has been rewritten, the packet is ours 893 * so pretend the O bit is set. 894 */ 895 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 896 if ((cmdsts & RX_CMD_O) && buflen == 0) { 897 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 898 break; 899 } 900 901 /* 902 * If this is not a single buffer packet with no errors 903 * or for some reason it's bigger than our frame size, 904 * ignore it and go to the next packet. 905 */ 906 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 907 (RX_CMD_F|RX_CMD_L) || 908 buflen > sc->sc_max_frame_length) { 909 GE_DPRINTF(sc, ("!")); 910 --rxq->rxq_active; 911 ifp->if_ipackets++; 912 ifp->if_ierrors++; 913 goto give_it_back; 914 } 915 916 /* CRC is included with the packet; trim it off. */ 917 buflen -= ETHER_CRC_LEN; 918 919 if (m == NULL) { 920 MGETHDR(m, M_DONTWAIT, MT_DATA); 921 if (m == NULL) { 922 GE_DPRINTF(sc, ("?")); 923 break; 924 } 925 } 926 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 927 MCLGET(m, M_DONTWAIT); 928 if ((m->m_flags & M_EXT) == 0) { 929 GE_DPRINTF(sc, ("?")); 930 break; 931 } 932 } 933 m->m_data += 2; 934 m->m_len = 0; 935 m->m_pkthdr.len = 0; 936 m_set_rcvif(m, ifp); 937 rxq->rxq_cmdsts = cmdsts; 938 --rxq->rxq_active; 939 940 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 941 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 942 943 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 944 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 945 m->m_len = buflen; 946 m->m_pkthdr.len = buflen; 947 948 eh = (const struct ether_header *) m->m_data; 949 if ((ifp->if_flags & IFF_PROMISC) || 950 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 951 (rxq->rxq_cmdsts & RX_STS_HE) || 952 (eh->ether_dhost[0] & 1) != 0 || 953 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 954 ETHER_ADDR_LEN) == 0) { 955 if_percpuq_enqueue(ifp->if_percpuq, m); 956 m = NULL; 957 GE_DPRINTF(sc, (">")); 958 } else { 959 m->m_len = 0; 960 m->m_pkthdr.len = 0; 961 GE_DPRINTF(sc, ("+")); 962 } 963 rxq->rxq_cmdsts = 0; 964 965 give_it_back: 966 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 967 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 968 #if 0 969 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 970 rxq->rxq_fi, 971 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 972 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 973 #endif 974 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 975 if (++rxq->rxq_fi == GE_RXDESC_MAX) 976 rxq->rxq_fi = 0; 977 rxq->rxq_active++; 978 } 979 rxq->rxq_curpkt = m; 980 GE_FUNC_EXIT(sc, ""); 981 } 982 983 uint32_t 984 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 985 { 986 struct ifnet * const ifp = &sc->sc_ec.ec_if; 987 struct gfe_rxqueue *rxq; 988 uint32_t rxbits; 989 #define RXPRIO_DECODER 0xffffaa50 990 GE_FUNC_ENTER(sc, "gfe_rx_process"); 991 992 rxbits = ETH_IR_RxBuffer_GET(cause); 993 while (rxbits) { 994 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 995 GE_DPRINTF(sc, ("%1x", rxbits)); 996 rxbits &= ~(1 << rxprio); 997 gfe_rx_get(sc, rxprio); 998 } 999 1000 rxbits = ETH_IR_RxError_GET(cause); 1001 while (rxbits) { 1002 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 1003 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 1004 int idx; 1005 rxbits &= ~(1 << rxprio); 1006 rxq = &sc->sc_rxq[rxprio]; 1007 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 1008 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 1009 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 1010 sc->sc_tickflags |= GE_TICK_RX_RESTART; 1011 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 1012 } 1013 ifp->if_ierrors++; 1014 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 1015 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi)); 1016 memset(masks, 0, sizeof(masks)); 1017 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1018 0, rxq->rxq_desc_mem.gdm_size, 1019 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1020 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 1021 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 1022 1023 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 1024 masks[idx/32] |= 1 << (idx & 31); 1025 } 1026 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1027 0, rxq->rxq_desc_mem.gdm_size, 1028 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1029 #if defined(DEBUG) 1030 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 1031 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi, 1032 rxq->rxq_cmdsts, masks[0], masks[1]); 1033 #endif 1034 } 1035 if ((intrmask & ETH_IR_RxBits) == 0) 1036 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 1037 1038 GE_FUNC_EXIT(sc, ""); 1039 return intrmask; 1040 } 1041 1042 int 1043 gfe_rx_prime(struct gfe_softc *sc) 1044 { 1045 struct gfe_rxqueue *rxq; 1046 int error; 1047 1048 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 1049 1050 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 1051 if (error) 1052 goto bail; 1053 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1054 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1055 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1056 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1057 } 1058 sc->sc_intrmask |= rxq->rxq_intrbits; 1059 1060 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 1061 if (error) 1062 goto bail; 1063 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1064 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1065 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1066 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1067 sc->sc_intrmask |= rxq->rxq_intrbits; 1068 } 1069 1070 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 1071 if (error) 1072 goto bail; 1073 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1074 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1075 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1076 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1077 sc->sc_intrmask |= rxq->rxq_intrbits; 1078 } 1079 1080 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 1081 if (error) 1082 goto bail; 1083 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1084 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1085 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1086 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1087 sc->sc_intrmask |= rxq->rxq_intrbits; 1088 } 1089 1090 bail: 1091 GE_FUNC_EXIT(sc, ""); 1092 return error; 1093 } 1094 1095 void 1096 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 1097 { 1098 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 1099 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 1100 if (rxq == NULL) { 1101 GE_FUNC_EXIT(sc, ""); 1102 return; 1103 } 1104 1105 if (rxq->rxq_curpkt) 1106 m_freem(rxq->rxq_curpkt); 1107 if ((sc->sc_flags & GE_NOFREE) == 0) { 1108 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 1109 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 1110 } 1111 GE_FUNC_EXIT(sc, ""); 1112 } 1113 1114 void 1115 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1116 { 1117 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 1118 sc->sc_flags &= ~GE_RXACTIVE; 1119 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 1120 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 1121 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1122 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR); 1123 do { 1124 delay(10); 1125 } while (GE_READ(sc, ETH_ESDCMR) & ETH_ESDCMR_AR); 1126 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 1127 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 1128 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 1129 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 1130 GE_FUNC_EXIT(sc, ""); 1131 } 1132 1133 void 1134 gfe_tick(void *arg) 1135 { 1136 struct gfe_softc * const sc = arg; 1137 uint32_t intrmask; 1138 unsigned int tickflags; 1139 int s; 1140 1141 GE_FUNC_ENTER(sc, "gfe_tick"); 1142 1143 s = splnet(); 1144 1145 tickflags = sc->sc_tickflags; 1146 sc->sc_tickflags = 0; 1147 intrmask = sc->sc_intrmask; 1148 if (tickflags & GE_TICK_TX_IFSTART) 1149 gfe_ifstart(&sc->sc_ec.ec_if); 1150 if (tickflags & GE_TICK_RX_RESTART) { 1151 intrmask |= sc->sc_idlemask; 1152 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 1153 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1154 rxq->rxq_fi = 0; 1155 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1156 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1157 } 1158 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 1159 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1160 rxq->rxq_fi = 0; 1161 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1162 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1163 } 1164 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 1165 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1166 rxq->rxq_fi = 0; 1167 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1168 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1169 } 1170 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 1171 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1172 rxq->rxq_fi = 0; 1173 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1174 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1175 } 1176 sc->sc_idlemask = 0; 1177 } 1178 if (intrmask != sc->sc_intrmask) { 1179 sc->sc_intrmask = intrmask; 1180 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1181 } 1182 gfe_intr(sc); 1183 splx(s); 1184 1185 GE_FUNC_EXIT(sc, ""); 1186 } 1187 1188 int 1189 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1190 { 1191 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1192 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1193 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1194 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1195 uint32_t intrmask = sc->sc_intrmask; 1196 size_t buflen; 1197 struct mbuf *m; 1198 1199 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1200 1201 /* 1202 * Anything in the pending queue to enqueue? if not, punt. Likewise 1203 * if the txq is not yet created. 1204 * otherwise grab its dmamap. 1205 */ 1206 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1207 GE_FUNC_EXIT(sc, "-"); 1208 return 0; 1209 } 1210 1211 /* 1212 * Have we [over]consumed our limit of descriptors? 1213 * Do we have enough free descriptors? 1214 */ 1215 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1216 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1217 uint32_t cmdsts; 1218 size_t pktlen; 1219 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1220 cmdsts = gt32toh(txd2->ed_cmdsts); 1221 if (cmdsts & TX_CMD_O) { 1222 int nextin; 1223 /* 1224 * Sometime the Discovery forgets to update the 1225 * last descriptor. See if we own the descriptor 1226 * after it (since we know we've turned that to 1227 * the discovery and if we owned it, the Discovery 1228 * gave it back). If we do, we know the Discovery 1229 * gave back this one but forgot to mark it as ours. 1230 */ 1231 nextin = txq->txq_fi + 1; 1232 if (nextin == GE_TXDESC_MAX) 1233 nextin = 0; 1234 GE_TXDPOSTSYNC(sc, txq, nextin); 1235 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1236 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1237 GE_TXDPRESYNC(sc, txq, nextin); 1238 GE_FUNC_EXIT(sc, "@"); 1239 return 0; 1240 } 1241 #ifdef DEBUG 1242 printf("%s: txenqueue: transmitter resynced at %d\n", 1243 device_xname(sc->sc_dev), txq->txq_fi); 1244 #endif 1245 } 1246 if (++txq->txq_fi == GE_TXDESC_MAX) 1247 txq->txq_fi = 0; 1248 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1249 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1250 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1251 txq->txq_nactive--; 1252 1253 /* statistics */ 1254 ifp->if_opackets++; 1255 if (cmdsts & TX_STS_ES) 1256 ifp->if_oerrors++; 1257 GE_DPRINTF(sc, ("%%")); 1258 } 1259 1260 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1261 1262 /* 1263 * If this packet would wrap around the end of the buffer, reset back 1264 * to the beginning. 1265 */ 1266 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1267 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1268 txq->txq_outptr = 0; 1269 } 1270 1271 /* 1272 * Make sure the output packet doesn't run over the beginning of 1273 * what we've already given the GT. 1274 */ 1275 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1276 txq->txq_outptr + buflen > txq->txq_inptr) { 1277 intrmask |= txq->txq_intrbits & 1278 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1279 if (sc->sc_intrmask != intrmask) { 1280 sc->sc_intrmask = intrmask; 1281 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1282 } 1283 GE_FUNC_EXIT(sc, "#"); 1284 return 0; 1285 } 1286 1287 /* 1288 * The end-of-list descriptor we put on last time is the starting point 1289 * for this packet. The GT is supposed to terminate list processing on 1290 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1291 * must terminate the list. 1292 */ 1293 intrmask = sc->sc_intrmask; 1294 1295 m_copydata(m, 0, m->m_pkthdr.len, 1296 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1297 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1298 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1299 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1300 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1301 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1302 1303 /* 1304 * Request a buffer interrupt every 2/3 of the way thru the transmit 1305 * buffer. 1306 */ 1307 txq->txq_ei_gapcount += buflen; 1308 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1309 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1310 txq->txq_ei_gapcount = 0; 1311 } else { 1312 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1313 } 1314 #if 0 1315 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1316 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1317 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1318 #endif 1319 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1320 1321 txq->txq_outptr += buflen; 1322 /* 1323 * Tell the SDMA engine to "Fetch!" 1324 */ 1325 GE_WRITE(sc, ETH_ESDCMR, 1326 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1327 1328 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1329 1330 /* 1331 * Update the last out appropriately. 1332 */ 1333 txq->txq_nactive++; 1334 if (++txq->txq_lo == GE_TXDESC_MAX) 1335 txq->txq_lo = 0; 1336 1337 /* 1338 * Move mbuf from the pending queue to the snd queue. 1339 */ 1340 IF_DEQUEUE(&txq->txq_pendq, m); 1341 bpf_mtap(ifp, m, BPF_D_OUT); 1342 m_freem(m); 1343 ifp->if_flags &= ~IFF_OACTIVE; 1344 1345 /* 1346 * Since we have put an item into the packet queue, we now want 1347 * an interrupt when the transmit queue finishes processing the 1348 * list. But only update the mask if needs changing. 1349 */ 1350 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1351 if (sc->sc_intrmask != intrmask) { 1352 sc->sc_intrmask = intrmask; 1353 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1354 } 1355 if (ifp->if_timer == 0) 1356 ifp->if_timer = 5; 1357 GE_FUNC_EXIT(sc, "*"); 1358 return 1; 1359 } 1360 1361 uint32_t 1362 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1363 { 1364 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1365 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1366 1367 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1368 1369 if (txq == NULL) { 1370 GE_FUNC_EXIT(sc, ""); 1371 return intrmask; 1372 } 1373 1374 while (txq->txq_nactive > 0) { 1375 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1376 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1377 uint32_t cmdsts; 1378 size_t pktlen; 1379 1380 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1381 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1382 int nextin; 1383 1384 if (txq->txq_nactive == 1) { 1385 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1386 GE_FUNC_EXIT(sc, ""); 1387 return intrmask; 1388 } 1389 /* 1390 * Sometimes the Discovery forgets to update the 1391 * ownership bit in the descriptor. See if we own the 1392 * descriptor after it (since we know we've turned 1393 * that to the Discovery and if we own it now then the 1394 * Discovery gave it back). If we do, we know the 1395 * Discovery gave back this one but forgot to mark it 1396 * as ours. 1397 */ 1398 nextin = txq->txq_fi + 1; 1399 if (nextin == GE_TXDESC_MAX) 1400 nextin = 0; 1401 GE_TXDPOSTSYNC(sc, txq, nextin); 1402 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1403 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1404 GE_TXDPRESYNC(sc, txq, nextin); 1405 GE_FUNC_EXIT(sc, ""); 1406 return intrmask; 1407 } 1408 #ifdef DEBUG 1409 printf("%s: txdone: transmitter resynced at %d\n", 1410 device_xname(sc->sc_dev), txq->txq_fi); 1411 #endif 1412 } 1413 #if 0 1414 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1415 txq->txq_lo, 1416 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1417 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1418 #endif 1419 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1420 if (++txq->txq_fi == GE_TXDESC_MAX) 1421 txq->txq_fi = 0; 1422 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1423 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1424 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1425 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1426 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1427 1428 /* statistics */ 1429 ifp->if_opackets++; 1430 if (cmdsts & TX_STS_ES) 1431 ifp->if_oerrors++; 1432 1433 /* txd->ed_bufptr = 0; */ 1434 1435 ifp->if_timer = 5; 1436 --txq->txq_nactive; 1437 } 1438 if (txq->txq_nactive != 0) 1439 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1440 device_xname(sc->sc_dev), txprio, txq->txq_nactive); 1441 ifp->if_timer = 0; 1442 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1443 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1444 GE_FUNC_EXIT(sc, ""); 1445 return intrmask; 1446 } 1447 1448 int 1449 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1450 { 1451 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1452 int error; 1453 1454 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1455 1456 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1457 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1458 if (error) { 1459 GE_FUNC_EXIT(sc, ""); 1460 return error; 1461 } 1462 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1463 if (error) { 1464 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1465 GE_FUNC_EXIT(sc, ""); 1466 return error; 1467 } 1468 GE_FUNC_EXIT(sc, ""); 1469 return 0; 1470 } 1471 1472 int 1473 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1474 { 1475 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1476 volatile struct gt_eth_desc *txd; 1477 unsigned int i; 1478 bus_addr_t addr; 1479 1480 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1481 1482 sc->sc_intrmask &= 1483 ~(ETH_IR_TxEndHigh | 1484 ETH_IR_TxBufferHigh | 1485 ETH_IR_TxEndLow | 1486 ETH_IR_TxBufferLow); 1487 1488 if (sc->sc_flags & GE_NOFREE) { 1489 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1490 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1491 } else { 1492 int error = gfe_tx_txqalloc(sc, txprio); 1493 if (error) { 1494 GE_FUNC_EXIT(sc, "!"); 1495 return error; 1496 } 1497 } 1498 1499 txq->txq_descs = 1500 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1501 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1502 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1503 1504 txq->txq_pendq.ifq_maxlen = 10; 1505 txq->txq_ei_gapcount = 0; 1506 txq->txq_nactive = 0; 1507 txq->txq_fi = 0; 1508 txq->txq_lo = 0; 1509 txq->txq_inptr = GE_TXBUF_SIZE; 1510 txq->txq_outptr = 0; 1511 for (i = 0, txd = txq->txq_descs, 1512 addr = txq->txq_desc_busaddr + sizeof(*txd); 1513 i < GE_TXDESC_MAX - 1; i++, txd++, addr += sizeof(*txd)) { 1514 /* 1515 * update the nxtptr to point to the next txd. 1516 */ 1517 txd->ed_cmdsts = 0; 1518 txd->ed_nxtptr = htogt32(addr); 1519 } 1520 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1521 htogt32(txq->txq_desc_busaddr); 1522 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1523 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1524 1525 switch (txprio) { 1526 case GE_TXPRIO_HI: 1527 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1528 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1529 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1530 txq->txq_ectdp = ETH_ECTDP1; 1531 GE_WRITE(sc, ETH_ECTDP1, txq->txq_desc_busaddr); 1532 break; 1533 1534 case GE_TXPRIO_LO: 1535 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1536 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1537 txq->txq_epsrbits = ETH_EPSR_TxLow; 1538 txq->txq_ectdp = ETH_ECTDP0; 1539 GE_WRITE(sc, ETH_ECTDP0, txq->txq_desc_busaddr); 1540 break; 1541 1542 case GE_TXPRIO_NONE: 1543 break; 1544 } 1545 #if 0 1546 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1547 GE_WRITE(sc->sc_dev, txq->txq_ectdp, txq->txq_desc_busaddr); 1548 GE_DPRINTF(sc, (")")); 1549 #endif 1550 1551 /* 1552 * If we are restarting, there may be packets in the pending queue 1553 * waiting to be enqueued. Try enqueuing packets from both priority 1554 * queues until the pending queue is empty or there no room for them 1555 * on the device. 1556 */ 1557 while (gfe_tx_enqueue(sc, txprio)) 1558 continue; 1559 1560 GE_FUNC_EXIT(sc, ""); 1561 return 0; 1562 } 1563 1564 void 1565 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1566 { 1567 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1568 1569 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1570 if (txq == NULL) { 1571 GE_FUNC_EXIT(sc, ""); 1572 return; 1573 } 1574 1575 if (!flush) { 1576 GE_FUNC_EXIT(sc, ""); 1577 return; 1578 } 1579 1580 if ((sc->sc_flags & GE_NOFREE) == 0) { 1581 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1582 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1583 } 1584 GE_FUNC_EXIT(sc, "-F"); 1585 } 1586 1587 void 1588 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1589 { 1590 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1591 1592 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1593 1594 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1595 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1596 sc->sc_intrmask &= 1597 ~(ETH_IR_TxEndHigh | 1598 ETH_IR_TxBufferHigh | 1599 ETH_IR_TxEndLow | 1600 ETH_IR_TxBufferLow); 1601 1602 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1603 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1604 1605 sc->sc_ec.ec_if.if_timer = 0; 1606 GE_FUNC_EXIT(sc, ""); 1607 } 1608 1609 int 1610 gfe_intr(void *arg) 1611 { 1612 struct gfe_softc * const sc = arg; 1613 uint32_t cause; 1614 uint32_t intrmask = sc->sc_intrmask; 1615 int claim = 0; 1616 int cnt; 1617 1618 GE_FUNC_ENTER(sc, "gfe_intr"); 1619 1620 for (cnt = 0; cnt < 4; cnt++) { 1621 if (sc->sc_intrmask != intrmask) { 1622 sc->sc_intrmask = intrmask; 1623 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1624 } 1625 cause = GE_READ(sc, ETH_EICR); 1626 cause &= sc->sc_intrmask; 1627 GE_DPRINTF(sc, (".%#x", cause)); 1628 if (cause == 0) 1629 break; 1630 1631 claim = 1; 1632 1633 GE_WRITE(sc, ETH_EICR, ~cause); 1634 #ifndef GE_NORX 1635 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1636 intrmask = gfe_rx_process(sc, cause, intrmask); 1637 #endif 1638 1639 #ifndef GE_NOTX 1640 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1641 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1642 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1643 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1644 #endif 1645 if (cause & ETH_IR_MIIPhySTC) { 1646 sc->sc_flags |= GE_PHYSTSCHG; 1647 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1648 } 1649 } 1650 1651 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1652 continue; 1653 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1654 continue; 1655 1656 GE_FUNC_EXIT(sc, ""); 1657 return claim; 1658 } 1659 1660 int 1661 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1662 { 1663 int error = 0; 1664 GE_FUNC_ENTER(sc, "gfe_whack"); 1665 1666 switch (op) { 1667 case GE_WHACK_RESTART: 1668 #ifndef GE_NOTX 1669 gfe_tx_stop(sc, op); 1670 #endif 1671 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1672 /* FALLTHROUGH */ 1673 case GE_WHACK_START: 1674 #ifndef GE_NOHASH 1675 if (error == 0 && sc->sc_hashtable == NULL) { 1676 error = gfe_hash_alloc(sc); 1677 if (error) 1678 break; 1679 } 1680 if (op != GE_WHACK_RESTART) 1681 gfe_hash_fill(sc); 1682 #endif 1683 #ifndef GE_NORX 1684 if (op != GE_WHACK_RESTART) { 1685 error = gfe_rx_prime(sc); 1686 if (error) 1687 break; 1688 } 1689 #endif 1690 #ifndef GE_NOTX 1691 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1692 if (error) 1693 break; 1694 #endif 1695 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1696 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1697 GE_WRITE(sc, ETH_EPCXR, sc->sc_pcxr); 1698 GE_WRITE(sc, ETH_EICR, 0); 1699 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1700 #ifndef GE_NOHASH 1701 GE_WRITE(sc, ETH_EHTPR, 1702 sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1703 #endif 1704 #ifndef GE_NORX 1705 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_ERD); 1706 sc->sc_flags |= GE_RXACTIVE; 1707 #endif 1708 /* FALLTHROUGH */ 1709 case GE_WHACK_CHANGE: 1710 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1711 GE_READ(sc, ETH_EPCR), GE_READ(sc, ETH_EIMR))); 1712 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1713 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1714 gfe_ifstart(&sc->sc_ec.ec_if); 1715 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1716 GE_READ(sc, ETH_ECTDP0), GE_READ(sc, ETH_ECTDP1))); 1717 GE_FUNC_EXIT(sc, ""); 1718 return error; 1719 case GE_WHACK_STOP: 1720 break; 1721 } 1722 1723 #ifdef GE_DEBUG 1724 if (error) 1725 GE_DPRINTF(sc, (" failed: %d\n", error)); 1726 #endif 1727 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1728 GE_WRITE(sc, ETH_EIMR, 0); 1729 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1730 #ifndef GE_NOTX 1731 gfe_tx_stop(sc, GE_WHACK_STOP); 1732 #endif 1733 #ifndef GE_NORX 1734 gfe_rx_stop(sc, GE_WHACK_STOP); 1735 #endif 1736 #ifndef GE_NOHASH 1737 if ((sc->sc_flags & GE_NOFREE) == 0) { 1738 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1739 sc->sc_hashtable = NULL; 1740 } 1741 #endif 1742 1743 GE_FUNC_EXIT(sc, ""); 1744 return error; 1745 } 1746 1747 int 1748 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1749 { 1750 uint32_t w0, add0, add1; 1751 uint32_t result; 1752 1753 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1754 add0 = ((uint32_t) eaddr[5] << 0) | 1755 ((uint32_t) eaddr[4] << 8) | 1756 ((uint32_t) eaddr[3] << 16); 1757 1758 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1759 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1760 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1761 1762 add1 = ((uint32_t) eaddr[2] << 0) | 1763 ((uint32_t) eaddr[1] << 8) | 1764 ((uint32_t) eaddr[0] << 16); 1765 1766 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1767 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1768 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1769 1770 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1771 /* 1772 * hashResult is the 15 bits Hash entry address. 1773 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1774 * MAC address, by nibble swapping in every byte (i.e MAC address 1775 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1776 */ 1777 1778 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1779 /* 1780 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1781 * 1782 * hashFunc0 calculates the hashResult in the following manner: 1783 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1784 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1785 */ 1786 result = (add0 & 3) | ((add0 >> 6) & ~3); 1787 result ^= (add0 >> 15) ^ (add1 >> 0); 1788 result &= 0x1ff; 1789 /* 1790 * hashResult[14:9] = ethernetADD[7:2] 1791 */ 1792 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1793 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1794 } else { 1795 #define TRIBITFLIP 073516240 /* yes its in octal */ 1796 /* 1797 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1798 * 1799 * hashFunc1 calculates the hashResult in the following manner: 1800 * hashResult[08:00] = ethernetADD[06:14] 1801 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1802 */ 1803 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1804 /* 1805 * Now bitswap those 9 bits 1806 */ 1807 result = 0; 1808 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1809 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1810 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1811 1812 /* 1813 * hashResult[14:09] = ethernetADD[00:05] 1814 */ 1815 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1816 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1817 GE_DPRINTF(sc, ("1(%#x)", result)); 1818 } 1819 GE_FUNC_EXIT(sc, ""); 1820 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1821 } 1822 1823 int 1824 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1825 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1826 { 1827 uint64_t he; 1828 uint64_t *maybe_he_p = NULL; 1829 int limit; 1830 int hash; 1831 int maybe_hash = 0; 1832 1833 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1834 1835 hash = gfe_hash_compute(sc, eaddr); 1836 1837 if (sc->sc_hashtable == NULL) { 1838 panic("%s:%d: hashtable == NULL!", device_xname(sc->sc_dev), 1839 __LINE__); 1840 } 1841 1842 /* 1843 * Assume we are going to insert so create the hash entry we 1844 * are going to insert. We also use it to match entries we 1845 * will be removing. 1846 */ 1847 he = ((uint64_t) eaddr[5] << 43) | 1848 ((uint64_t) eaddr[4] << 35) | 1849 ((uint64_t) eaddr[3] << 27) | 1850 ((uint64_t) eaddr[2] << 19) | 1851 ((uint64_t) eaddr[1] << 11) | 1852 ((uint64_t) eaddr[0] << 3) | 1853 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1854 1855 /* 1856 * The GT will search upto 12 entries for a hit, so we must mimic that. 1857 */ 1858 hash &= sc->sc_hashmask / sizeof(he); 1859 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1860 /* 1861 * Does the GT wrap at the end, stop at the, or overrun the 1862 * end? Assume it wraps for now. Stash a copy of the 1863 * current hash entry. 1864 */ 1865 uint64_t *he_p = &sc->sc_hashtable[hash]; 1866 uint64_t thishe = *he_p; 1867 1868 /* 1869 * If the hash entry isn't valid, that break the chain. And 1870 * this entry a good candidate for reuse. 1871 */ 1872 if ((thishe & HSH_V) == 0) { 1873 maybe_he_p = he_p; 1874 break; 1875 } 1876 1877 /* 1878 * If the hash entry has the same address we are looking for 1879 * then ... if we are removing and the skip bit is set, its 1880 * already been removed. if are adding and the skip bit is 1881 * clear, then its already added. In either return EBUSY 1882 * indicating the op has already been done. Otherwise flip 1883 * the skip bit and return 0. 1884 */ 1885 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1886 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1887 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1888 return EBUSY; 1889 *he_p = thishe ^ HSH_S; 1890 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1891 hash * sizeof(he), sizeof(he), 1892 BUS_DMASYNC_PREWRITE); 1893 GE_FUNC_EXIT(sc, "^"); 1894 return 0; 1895 } 1896 1897 /* 1898 * If we haven't found a slot for the entry and this entry 1899 * is currently being skipped, return this entry. 1900 */ 1901 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1902 maybe_he_p = he_p; 1903 maybe_hash = hash; 1904 } 1905 1906 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1907 } 1908 1909 /* 1910 * If we got here, then there was no entry to remove. 1911 */ 1912 if (op == GE_HASH_REMOVE) { 1913 GE_FUNC_EXIT(sc, "?"); 1914 return ENOENT; 1915 } 1916 1917 /* 1918 * If we couldn't find a slot, return an error. 1919 */ 1920 if (maybe_he_p == NULL) { 1921 GE_FUNC_EXIT(sc, "!"); 1922 return ENOSPC; 1923 } 1924 1925 /* Update the entry. 1926 */ 1927 *maybe_he_p = he; 1928 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1929 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1930 GE_FUNC_EXIT(sc, "+"); 1931 return 0; 1932 } 1933 1934 int 1935 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, 1936 u_long cmd) 1937 { 1938 struct gfe_softc *sc = ec->ec_if.if_softc; 1939 int error; 1940 enum gfe_hash_op op; 1941 enum gfe_rxprio prio; 1942 1943 GE_FUNC_ENTER(sc, "hash_multichg"); 1944 /* 1945 * Is this a wildcard entry? If so and its being removed, recompute. 1946 */ 1947 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1948 if (cmd == SIOCDELMULTI) { 1949 GE_FUNC_EXIT(sc, ""); 1950 return ENETRESET; 1951 } 1952 1953 /* 1954 * Switch in 1955 */ 1956 sc->sc_flags |= GE_ALLMULTI; 1957 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1958 sc->sc_pcr |= ETH_EPCR_PM; 1959 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1960 GE_FUNC_EXIT(sc, ""); 1961 return 0; 1962 } 1963 GE_FUNC_EXIT(sc, ""); 1964 return ENETRESET; 1965 } 1966 1967 prio = GE_RXPRIO_MEDLO; 1968 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1969 1970 if (sc->sc_hashtable == NULL) { 1971 GE_FUNC_EXIT(sc, ""); 1972 return 0; 1973 } 1974 1975 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1976 if (error == EBUSY) { 1977 aprint_error_dev(sc->sc_dev, "multichg: tried to %s %s again\n", 1978 cmd == SIOCDELMULTI ? "remove" : "add", 1979 ether_sprintf(enm->enm_addrlo)); 1980 GE_FUNC_EXIT(sc, ""); 1981 return 0; 1982 } 1983 1984 if (error == ENOENT) { 1985 aprint_error_dev(sc->sc_dev, 1986 "multichg: failed to remove %s: not in table\n", 1987 ether_sprintf(enm->enm_addrlo)); 1988 GE_FUNC_EXIT(sc, ""); 1989 return 0; 1990 } 1991 1992 if (error == ENOSPC) { 1993 aprint_error_dev(sc->sc_dev, "multichg:" 1994 " failed to add %s: no space; regenerating table\n", 1995 ether_sprintf(enm->enm_addrlo)); 1996 GE_FUNC_EXIT(sc, ""); 1997 return ENETRESET; 1998 } 1999 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 2000 device_xname(sc->sc_dev), 2001 cmd == SIOCDELMULTI ? "remove" : "add", 2002 ether_sprintf(enm->enm_addrlo))); 2003 GE_FUNC_EXIT(sc, ""); 2004 return 0; 2005 } 2006 2007 int 2008 gfe_hash_fill(struct gfe_softc *sc) 2009 { 2010 struct ether_multistep step; 2011 struct ether_multi *enm; 2012 int error; 2013 2014 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 2015 2016 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 2017 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 2018 if (error) { 2019 GE_FUNC_EXIT(sc, "!"); 2020 return error; 2021 } 2022 2023 sc->sc_flags &= ~GE_ALLMULTI; 2024 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 2025 sc->sc_pcr &= ~ETH_EPCR_PM; 2026 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 2027 while (enm != NULL) { 2028 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2029 sc->sc_flags |= GE_ALLMULTI; 2030 sc->sc_pcr |= ETH_EPCR_PM; 2031 } else { 2032 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 2033 GE_RXPRIO_MEDLO, enm->enm_addrlo); 2034 if (error == ENOSPC) 2035 break; 2036 } 2037 ETHER_NEXT_MULTI(step, enm); 2038 } 2039 2040 GE_FUNC_EXIT(sc, ""); 2041 return error; 2042 } 2043 2044 int 2045 gfe_hash_alloc(struct gfe_softc *sc) 2046 { 2047 int error; 2048 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 2049 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 2050 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 2051 BUS_DMA_NOCACHE); 2052 if (error) { 2053 aprint_error_dev(sc->sc_dev, 2054 "failed to allocate %d bytes for hash table: %d\n", 2055 sc->sc_hashmask + 1, error); 2056 GE_FUNC_EXIT(sc, ""); 2057 return error; 2058 } 2059 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 2060 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 2061 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 2062 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 2063 GE_FUNC_EXIT(sc, ""); 2064 return 0; 2065 } 2066