1 /* $NetBSD: if_gfe.c,v 1.36 2010/04/28 13:51:56 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.36 2010/04/28 13:51:56 kiyohara Exp $"); 46 47 #include "opt_inet.h" 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/bus.h> 52 #include <sys/callout.h> 53 #include <sys/device.h> 54 #include <sys/errno.h> 55 #include <sys/ioctl.h> 56 #include <sys/mbuf.h> 57 #include <sys/mutex.h> 58 #include <sys/socket.h> 59 60 #include <uvm/uvm.h> 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 #include <net/bpf.h> 73 #if NRND > 0 74 #include <sys/rnd.h> 75 #endif 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <dev/marvell/gtreg.h> 81 #include <dev/marvell/gtvar.h> 82 #include <dev/marvell/gtethreg.h> 83 #include <dev/marvell/if_gfevar.h> 84 #include <dev/marvell/marvellreg.h> 85 #include <dev/marvell/marvellvar.h> 86 87 #include <prop/proplib.h> 88 89 #include "locators.h" 90 91 92 #define GE_READ(sc, reg) \ 93 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)) 94 #define GE_WRITE(sc, reg, v) \ 95 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (v)) 96 97 #define GE_DEBUG 98 #if 0 99 #define GE_NOHASH 100 #define GE_NORX 101 #endif 102 103 #ifdef GE_DEBUG 104 #define GE_DPRINTF(sc, a) \ 105 do { \ 106 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 107 printf a; \ 108 } while (0 /* CONSTCOND */) 109 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 110 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 111 #else 112 #define GE_DPRINTF(sc, a) do { } while (0) 113 #define GE_FUNC_ENTER(sc, func) do { } while (0) 114 #define GE_FUNC_EXIT(sc, str) do { } while (0) 115 #endif 116 enum gfe_whack_op { 117 GE_WHACK_START, GE_WHACK_RESTART, 118 GE_WHACK_CHANGE, GE_WHACK_STOP 119 }; 120 121 enum gfe_hash_op { 122 GE_HASH_ADD, GE_HASH_REMOVE, 123 }; 124 125 #if 1 126 #define htogt32(a) htobe32(a) 127 #define gt32toh(a) be32toh(a) 128 #else 129 #define htogt32(a) htole32(a) 130 #define gt32toh(a) le32toh(a) 131 #endif 132 133 #define GE_RXDSYNC(sc, rxq, n, ops) \ 134 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 135 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 136 (ops)) 137 #define GE_RXDPRESYNC(sc, rxq, n) \ 138 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 139 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 140 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 141 142 #define GE_TXDSYNC(sc, txq, n, ops) \ 143 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 144 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 145 (ops)) 146 #define GE_TXDPRESYNC(sc, txq, n) \ 147 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 148 #define GE_TXDPOSTSYNC(sc, txq, n) \ 149 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 150 151 #define STATIC 152 153 154 STATIC int gfec_match(device_t, cfdata_t, void *); 155 STATIC void gfec_attach(device_t, device_t, void *); 156 157 STATIC int gfec_print(void *, const char *); 158 STATIC int gfec_search(device_t, cfdata_t, const int *, void *); 159 160 STATIC int gfec_enet_phy(device_t, int); 161 STATIC int gfec_mii_read(device_t, int, int); 162 STATIC void gfec_mii_write(device_t, int, int, int); 163 STATIC void gfec_mii_statchg(device_t); 164 165 STATIC int gfe_match(device_t, cfdata_t, void *); 166 STATIC void gfe_attach(device_t, device_t, void *); 167 168 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 169 size_t, int); 170 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 171 172 STATIC int gfe_ifioctl(struct ifnet *, u_long, void *); 173 STATIC void gfe_ifstart(struct ifnet *); 174 STATIC void gfe_ifwatchdog(struct ifnet *); 175 176 STATIC void gfe_tick(void *arg); 177 178 STATIC void gfe_tx_restart(void *); 179 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 180 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 181 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 182 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 183 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 184 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 185 186 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 187 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 188 STATIC int gfe_rx_prime(struct gfe_softc *); 189 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 190 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 191 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 192 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 193 194 STATIC int gfe_intr(void *); 195 196 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 197 198 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 199 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 200 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 201 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 202 u_long); 203 STATIC int gfe_hash_fill(struct gfe_softc *); 204 STATIC int gfe_hash_alloc(struct gfe_softc *); 205 206 207 CFATTACH_DECL_NEW(gfec, sizeof(struct gfec_softc), 208 gfec_match, gfec_attach, NULL, NULL); 209 CFATTACH_DECL_NEW(gfe, sizeof(struct gfe_softc), 210 gfe_match, gfe_attach, NULL, NULL); 211 212 213 /* ARGSUSED */ 214 int 215 gfec_match(device_t parent, cfdata_t cf, void *aux) 216 { 217 struct marvell_attach_args *mva = aux; 218 219 if (strcmp(mva->mva_name, cf->cf_name) != 0) 220 return 0; 221 222 switch (mva->mva_model) { 223 case MARVELL_DISCOVERY: 224 break; 225 226 default: 227 return 0; 228 } 229 if (mva->mva_offset == GTCF_OFFSET_DEFAULT) 230 return 0; 231 232 mva->mva_size = ETHC_SIZE; 233 return 1; 234 } 235 236 /* ARGSUSED */ 237 void 238 gfec_attach(device_t parent, device_t self, void *aux) 239 { 240 struct gfec_softc *sc = device_private(self); 241 struct marvell_attach_args *mva = aux, gfea; 242 static int gfe_irqs[] = { 32, 33, 34 }; 243 int i; 244 245 aprint_naive("\n"); 246 aprint_normal(": Ethernet Controller\n"); 247 248 sc->sc_dev = self; 249 sc->sc_iot = mva->mva_iot; 250 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 251 mva->mva_size, &sc->sc_ioh)) { 252 aprint_error_dev(self, "Cannot map registers\n"); 253 return; 254 } 255 256 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 257 258 for (i = 0; i < ETH_NUM; i++) { 259 gfea.mva_name = "gfe"; 260 gfea.mva_model = mva->mva_model; 261 gfea.mva_iot = sc->sc_iot; 262 gfea.mva_ioh = sc->sc_ioh; 263 gfea.mva_unit = i; 264 gfea.mva_dmat = mva->mva_dmat; 265 gfea.mva_irq = gfe_irqs[i]; 266 config_found_sm_loc(sc->sc_dev, "gfec", NULL, &gfea, 267 gfec_print, gfec_search); 268 } 269 } 270 271 int 272 gfec_print(void *aux, const char *pnp) 273 { 274 struct marvell_attach_args *gfea = aux; 275 276 if (pnp) 277 aprint_normal("%s at %s port %d", 278 gfea->mva_name, pnp, gfea->mva_unit); 279 else { 280 if (gfea->mva_unit != GFECCF_PORT_DEFAULT) 281 aprint_normal(" port %d", gfea->mva_unit); 282 if (gfea->mva_irq != GFECCF_IRQ_DEFAULT) 283 aprint_normal(" irq %d", gfea->mva_irq); 284 } 285 return UNCONF; 286 } 287 288 /* ARGSUSED */ 289 int 290 gfec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 291 { 292 struct marvell_attach_args *gfea = aux; 293 294 if (cf->cf_loc[GFECCF_PORT] == gfea->mva_unit && 295 cf->cf_loc[GFECCF_IRQ] != GFECCF_IRQ_DEFAULT) 296 gfea->mva_irq = cf->cf_loc[GFECCF_IRQ]; 297 298 return config_match(parent, cf, aux); 299 } 300 301 int 302 gfec_enet_phy(device_t dev, int unit) 303 { 304 struct gfec_softc *sc = device_private(dev); 305 uint32_t epar; 306 307 epar = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ETH_EPAR); 308 return ETH_EPAR_PhyAD_GET(epar, unit); 309 } 310 311 int 312 gfec_mii_read(device_t dev, int phy, int reg) 313 { 314 struct gfec_softc *csc = device_private(device_parent(dev)); 315 uint32_t data; 316 int count = 10000; 317 318 mutex_enter(&csc->sc_mtx); 319 320 do { 321 DELAY(10); 322 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 323 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 324 325 if (count == 0) { 326 aprint_error_dev(dev, 327 "mii read for phy %d reg %d busied out\n", phy, reg); 328 mutex_exit(&csc->sc_mtx); 329 return ETH_ESMIR_Value_GET(data); 330 } 331 332 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 333 ETH_ESMIR_READ(phy, reg)); 334 335 count = 10000; 336 do { 337 DELAY(10); 338 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 339 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 340 341 mutex_exit(&csc->sc_mtx); 342 343 if (count == 0) 344 aprint_error_dev(dev, 345 "mii read for phy %d reg %d timed out\n", phy, reg); 346 #if defined(GTMIIDEBUG) 347 aprint_normal_dev(dev, "mii_read(%d, %d): %#x data %#x\n", 348 phy, reg, data, ETH_ESMIR_Value_GET(data)); 349 #endif 350 return ETH_ESMIR_Value_GET(data); 351 } 352 353 void 354 gfec_mii_write (device_t dev, int phy, int reg, int value) 355 { 356 struct gfec_softc *csc = device_private(device_parent(dev)); 357 uint32_t data; 358 int count = 10000; 359 360 mutex_enter(&csc->sc_mtx); 361 362 do { 363 DELAY(10); 364 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 365 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 366 367 if (count == 0) { 368 aprint_error_dev(dev, 369 "mii write for phy %d reg %d busied out (busy)\n", 370 phy, reg); 371 mutex_exit(&csc->sc_mtx); 372 return; 373 } 374 375 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 376 ETH_ESMIR_WRITE(phy, reg, value)); 377 378 count = 10000; 379 do { 380 DELAY(10); 381 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 382 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 383 384 mutex_exit(&csc->sc_mtx); 385 386 if (count == 0) 387 aprint_error_dev(dev, 388 "mii write for phy %d reg %d timed out\n", phy, reg); 389 #if defined(GTMIIDEBUG) 390 aprint_normal_dev(dev, "mii_write(%d, %d, %#x)\n", phy, reg, value); 391 #endif 392 } 393 394 void 395 gfec_mii_statchg(device_t dev) 396 { 397 /* struct gfe_softc *sc = device_private(self); */ 398 /* do nothing? */ 399 } 400 401 /* ARGSUSED */ 402 int 403 gfe_match(device_t parent, cfdata_t cf, void *aux) 404 { 405 406 return 1; 407 } 408 409 /* ARGSUSED */ 410 void 411 gfe_attach(device_t parent, device_t self, void *aux) 412 { 413 struct marvell_attach_args *mva = aux; 414 struct gfe_softc * const sc = device_private(self); 415 struct ifnet * const ifp = &sc->sc_ec.ec_if; 416 uint32_t sdcr; 417 int phyaddr, error; 418 prop_data_t ea; 419 uint8_t enaddr[6]; 420 421 aprint_naive("\n"); 422 aprint_normal(": Ethernet Controller\n"); 423 424 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 425 mva->mva_offset, mva->mva_size, &sc->sc_memh)) { 426 aprint_error_dev(self, "failed to map registers\n"); 427 return; 428 } 429 sc->sc_dev = self; 430 sc->sc_memt = mva->mva_iot; 431 sc->sc_dmat = mva->mva_dmat; 432 sc->sc_macno = (mva->mva_offset == ETH_BASE(0)) ? 0 : 433 ((mva->mva_offset == ETH_BASE(1)) ? 1 : 2); 434 435 callout_init(&sc->sc_co, 0); 436 437 phyaddr = gfec_enet_phy(parent, sc->sc_macno); 438 439 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-addr"); 440 if (ea != NULL) { 441 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 442 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 443 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 444 } 445 446 sc->sc_pcr = GE_READ(sc, ETH_EPCR); 447 sc->sc_pcxr = GE_READ(sc, ETH_EPCXR); 448 sc->sc_intrmask = GE_READ(sc, ETH_EIMR) | ETH_IR_MIIPhySTC; 449 450 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 451 452 #if defined(DEBUG) 453 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 454 #endif 455 456 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 457 if (device_cfdata(self)->cf_flags & 1) { 458 aprint_normal_dev(self, "phy %d (rmii)\n", phyaddr); 459 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 460 } else { 461 aprint_normal_dev(self, "phy %d (mii)\n", phyaddr); 462 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 463 } 464 if (device_cfdata(self)->cf_flags & 2) 465 sc->sc_flags |= GE_NOFREE; 466 /* Set Max Frame Length is 1536 */ 467 sc->sc_pcxr &= ~ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_MASK); 468 sc->sc_pcxr |= ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_1536); 469 sc->sc_max_frame_length = 1536; 470 471 if (sc->sc_pcr & ETH_EPCR_EN) { 472 int tries = 1000; 473 /* 474 * Abort transmitter and receiver and wait for them to quiese 475 */ 476 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR | ETH_ESDCMR_AT); 477 do { 478 delay(100); 479 if (tries-- <= 0) { 480 aprint_error_dev(self, "Abort TX/RX failed\n"); 481 break; 482 } 483 } while (GE_READ(sc, ETH_ESDCMR) & 484 (ETH_ESDCMR_AR | ETH_ESDCMR_AT)); 485 } 486 487 sc->sc_pcr &= 488 ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 489 490 #if defined(DEBUG) 491 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 492 #endif 493 494 /* 495 * Now turn off the GT. If it didn't quiese, too ***ing bad. 496 */ 497 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 498 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 499 sdcr = GE_READ(sc, ETH_ESDCR); 500 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 501 sdcr |= ETH_ESDCR_RIFB; 502 GE_WRITE(sc, ETH_ESDCR, sdcr); 503 504 sc->sc_mii.mii_ifp = ifp; 505 sc->sc_mii.mii_readreg = gfec_mii_read; 506 sc->sc_mii.mii_writereg = gfec_mii_write; 507 sc->sc_mii.mii_statchg = gfec_mii_statchg; 508 509 sc->sc_ec.ec_mii = &sc->sc_mii; 510 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 511 ether_mediastatus); 512 513 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 514 MII_OFFSET_ANY, MIIF_NOISOLATE); 515 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 516 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 517 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 518 } else { 519 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 520 } 521 522 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 523 ifp->if_softc = sc; 524 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 525 #if 0 526 ifp->if_flags |= IFF_DEBUG; 527 #endif 528 ifp->if_ioctl = gfe_ifioctl; 529 ifp->if_start = gfe_ifstart; 530 ifp->if_watchdog = gfe_ifwatchdog; 531 532 if (sc->sc_flags & GE_NOFREE) { 533 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 534 if (!error) 535 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 536 if (!error) 537 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 538 if (!error) 539 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 540 if (!error) 541 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 542 if (!error) 543 error = gfe_hash_alloc(sc); 544 if (error) 545 aprint_error_dev(self, 546 "failed to allocate resources: %d\n", error); 547 } 548 549 if_attach(ifp); 550 ether_ifattach(ifp, enaddr); 551 bpf_attach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 552 #if NRND > 0 553 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 554 0); 555 #endif 556 marvell_intr_establish(mva->mva_irq, IPL_NET, gfe_intr, sc); 557 } 558 559 int 560 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 561 size_t size, int flags) 562 { 563 int error = 0; 564 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 565 566 KASSERT(gdm->gdm_kva == NULL); 567 gdm->gdm_size = size; 568 gdm->gdm_maxsegs = maxsegs; 569 570 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 571 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 572 BUS_DMA_NOWAIT); 573 if (error) 574 goto fail; 575 576 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 577 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 578 if (error) 579 goto fail; 580 581 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 582 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 583 if (error) 584 goto fail; 585 586 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 587 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 588 if (error) 589 goto fail; 590 591 /* invalidate from cache */ 592 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 593 BUS_DMASYNC_PREREAD); 594 fail: 595 if (error) { 596 gfe_dmamem_free(sc, gdm); 597 GE_DPRINTF(sc, (":err=%d", error)); 598 } 599 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 600 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 601 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 602 GE_FUNC_EXIT(sc, ""); 603 return error; 604 } 605 606 void 607 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 608 { 609 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 610 if (gdm->gdm_map) 611 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 612 if (gdm->gdm_kva) 613 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 614 if (gdm->gdm_nsegs > 0) 615 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 616 gdm->gdm_map = NULL; 617 gdm->gdm_kva = NULL; 618 gdm->gdm_nsegs = 0; 619 GE_FUNC_EXIT(sc, ""); 620 } 621 622 int 623 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 624 { 625 struct gfe_softc * const sc = ifp->if_softc; 626 struct ifreq *ifr = (struct ifreq *) data; 627 struct ifaddr *ifa = (struct ifaddr *) data; 628 int s, error = 0; 629 630 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 631 s = splnet(); 632 633 switch (cmd) { 634 case SIOCINITIFADDR: 635 ifp->if_flags |= IFF_UP; 636 error = gfe_whack(sc, GE_WHACK_START); 637 switch (ifa->ifa_addr->sa_family) { 638 #ifdef INET 639 case AF_INET: 640 if (error == 0) 641 arp_ifinit(ifp, ifa); 642 break; 643 #endif 644 default: 645 break; 646 } 647 break; 648 649 case SIOCSIFFLAGS: 650 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 651 break; 652 /* XXX re-use ether_ioctl() */ 653 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 654 case IFF_UP|IFF_RUNNING:/* active->active, update */ 655 error = gfe_whack(sc, GE_WHACK_CHANGE); 656 break; 657 case IFF_RUNNING: /* not up, so we stop */ 658 error = gfe_whack(sc, GE_WHACK_STOP); 659 break; 660 case IFF_UP: /* not running, so we start */ 661 error = gfe_whack(sc, GE_WHACK_START); 662 break; 663 case 0: /* idle->idle: do nothing */ 664 break; 665 } 666 break; 667 668 case SIOCSIFMEDIA: 669 case SIOCGIFMEDIA: 670 case SIOCADDMULTI: 671 case SIOCDELMULTI: 672 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 673 if (ifp->if_flags & IFF_RUNNING) 674 error = gfe_whack(sc, GE_WHACK_CHANGE); 675 else 676 error = 0; 677 } 678 break; 679 680 case SIOCSIFMTU: 681 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 682 error = EINVAL; 683 break; 684 } 685 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 686 error = 0; 687 break; 688 689 default: 690 error = ether_ioctl(ifp, cmd, data); 691 break; 692 } 693 splx(s); 694 GE_FUNC_EXIT(sc, ""); 695 return error; 696 } 697 698 void 699 gfe_ifstart(struct ifnet *ifp) 700 { 701 struct gfe_softc * const sc = ifp->if_softc; 702 struct mbuf *m; 703 704 GE_FUNC_ENTER(sc, "gfe_ifstart"); 705 706 if ((ifp->if_flags & IFF_RUNNING) == 0) { 707 GE_FUNC_EXIT(sc, "$"); 708 return; 709 } 710 711 for (;;) { 712 IF_DEQUEUE(&ifp->if_snd, m); 713 if (m == NULL) { 714 ifp->if_flags &= ~IFF_OACTIVE; 715 GE_FUNC_EXIT(sc, ""); 716 return; 717 } 718 719 /* 720 * No space in the pending queue? try later. 721 */ 722 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 723 break; 724 725 /* 726 * Try to enqueue a mbuf to the device. If that fails, we 727 * can always try to map the next mbuf. 728 */ 729 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 730 GE_DPRINTF(sc, (">")); 731 #ifndef GE_NOTX 732 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 733 #endif 734 } 735 736 /* 737 * Attempt to queue the mbuf for send failed. 738 */ 739 IF_PREPEND(&ifp->if_snd, m); 740 ifp->if_flags |= IFF_OACTIVE; 741 GE_FUNC_EXIT(sc, "%%"); 742 } 743 744 void 745 gfe_ifwatchdog(struct ifnet *ifp) 746 { 747 struct gfe_softc * const sc = ifp->if_softc; 748 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 749 750 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 751 aprint_error_dev(sc->sc_dev, "device timeout"); 752 if (ifp->if_flags & IFF_RUNNING) { 753 uint32_t curtxdnum; 754 755 curtxdnum = (GE_READ(sc, txq->txq_ectdp) - 756 txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 757 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 758 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 759 aprint_error(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 760 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 761 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 762 GE_READ(sc, ETH_EICR)); 763 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 764 GE_TXDPRESYNC(sc, txq, curtxdnum); 765 } 766 aprint_error("\n"); 767 ifp->if_oerrors++; 768 (void) gfe_whack(sc, GE_WHACK_RESTART); 769 GE_FUNC_EXIT(sc, ""); 770 } 771 772 int 773 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 774 { 775 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 776 int error; 777 778 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 779 GE_DPRINTF(sc, ("(%d)", rxprio)); 780 781 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 782 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 783 if (error) { 784 GE_FUNC_EXIT(sc, "!!"); 785 return error; 786 } 787 788 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 789 GE_RXBUF_MEMSIZE, 0); 790 if (error) { 791 GE_FUNC_EXIT(sc, "!!!"); 792 return error; 793 } 794 GE_FUNC_EXIT(sc, ""); 795 return error; 796 } 797 798 int 799 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 800 { 801 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 802 volatile struct gt_eth_desc *rxd; 803 const bus_dma_segment_t *ds; 804 int idx; 805 bus_addr_t nxtaddr; 806 bus_size_t boff; 807 808 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 809 GE_DPRINTF(sc, ("(%d)", rxprio)); 810 811 if ((sc->sc_flags & GE_NOFREE) == 0) { 812 int error = gfe_rx_rxqalloc(sc, rxprio); 813 if (error) { 814 GE_FUNC_EXIT(sc, "!"); 815 return error; 816 } 817 } else { 818 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 819 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 820 } 821 822 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 823 824 rxq->rxq_descs = 825 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 826 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 827 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 828 rxq->rxq_fi = 0; 829 rxq->rxq_active = GE_RXDESC_MAX; 830 boff = 0; 831 ds = rxq->rxq_buf_mem.gdm_map->dm_segs; 832 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 833 for (idx = 0, rxd = rxq->rxq_descs; idx < GE_RXDESC_MAX; 834 idx++, nxtaddr += sizeof(*(++rxd))) { 835 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 836 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 837 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 838 /* 839 * update the nxtptr to point to the next txd. 840 */ 841 if (idx == GE_RXDESC_MAX - 1) 842 nxtaddr = rxq->rxq_desc_busaddr; 843 rxd->ed_nxtptr = htogt32(nxtaddr); 844 boff += GE_RXBUF_SIZE; 845 if (boff == ds->ds_len) { 846 ds++; 847 boff = 0; 848 } 849 } 850 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 851 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 852 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 853 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 854 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 855 BUS_DMASYNC_PREREAD); 856 857 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 858 switch (rxprio) { 859 case GE_RXPRIO_HI: 860 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 861 rxq->rxq_efrdp = ETH_EFRDP3; 862 rxq->rxq_ecrdp = ETH_ECRDP3; 863 break; 864 case GE_RXPRIO_MEDHI: 865 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 866 rxq->rxq_efrdp = ETH_EFRDP2; 867 rxq->rxq_ecrdp = ETH_ECRDP2; 868 break; 869 case GE_RXPRIO_MEDLO: 870 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 871 rxq->rxq_efrdp = ETH_EFRDP1; 872 rxq->rxq_ecrdp = ETH_ECRDP1; 873 break; 874 case GE_RXPRIO_LO: 875 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 876 rxq->rxq_efrdp = ETH_EFRDP0; 877 rxq->rxq_ecrdp = ETH_ECRDP0; 878 break; 879 } 880 GE_FUNC_EXIT(sc, ""); 881 return 0; 882 } 883 884 void 885 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 886 { 887 struct ifnet * const ifp = &sc->sc_ec.ec_if; 888 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 889 struct mbuf *m = rxq->rxq_curpkt; 890 891 GE_FUNC_ENTER(sc, "gfe_rx_get"); 892 GE_DPRINTF(sc, ("(%d)", rxprio)); 893 894 while (rxq->rxq_active > 0) { 895 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 896 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 897 const struct ether_header *eh; 898 unsigned int cmdsts; 899 size_t buflen; 900 901 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 902 cmdsts = gt32toh(rxd->ed_cmdsts); 903 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 904 rxq->rxq_cmdsts = cmdsts; 905 /* 906 * Sometimes the GE "forgets" to reset the ownership bit. 907 * But if the length has been rewritten, the packet is ours 908 * so pretend the O bit is set. 909 */ 910 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 911 if ((cmdsts & RX_CMD_O) && buflen == 0) { 912 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 913 break; 914 } 915 916 /* 917 * If this is not a single buffer packet with no errors 918 * or for some reason it's bigger than our frame size, 919 * ignore it and go to the next packet. 920 */ 921 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 922 (RX_CMD_F|RX_CMD_L) || 923 buflen > sc->sc_max_frame_length) { 924 GE_DPRINTF(sc, ("!")); 925 --rxq->rxq_active; 926 ifp->if_ipackets++; 927 ifp->if_ierrors++; 928 goto give_it_back; 929 } 930 931 /* CRC is included with the packet; trim it off. */ 932 buflen -= ETHER_CRC_LEN; 933 934 if (m == NULL) { 935 MGETHDR(m, M_DONTWAIT, MT_DATA); 936 if (m == NULL) { 937 GE_DPRINTF(sc, ("?")); 938 break; 939 } 940 } 941 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 942 MCLGET(m, M_DONTWAIT); 943 if ((m->m_flags & M_EXT) == 0) { 944 GE_DPRINTF(sc, ("?")); 945 break; 946 } 947 } 948 m->m_data += 2; 949 m->m_len = 0; 950 m->m_pkthdr.len = 0; 951 m->m_pkthdr.rcvif = ifp; 952 rxq->rxq_cmdsts = cmdsts; 953 --rxq->rxq_active; 954 955 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 956 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 957 958 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 959 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 960 m->m_len = buflen; 961 m->m_pkthdr.len = buflen; 962 963 ifp->if_ipackets++; 964 bpf_mtap(ifp, m); 965 966 eh = (const struct ether_header *) m->m_data; 967 if ((ifp->if_flags & IFF_PROMISC) || 968 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 969 (rxq->rxq_cmdsts & RX_STS_HE) || 970 (eh->ether_dhost[0] & 1) != 0 || 971 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 972 ETHER_ADDR_LEN) == 0) { 973 (*ifp->if_input)(ifp, m); 974 m = NULL; 975 GE_DPRINTF(sc, (">")); 976 } else { 977 m->m_len = 0; 978 m->m_pkthdr.len = 0; 979 GE_DPRINTF(sc, ("+")); 980 } 981 rxq->rxq_cmdsts = 0; 982 983 give_it_back: 984 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 985 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 986 #if 0 987 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 988 rxq->rxq_fi, 989 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 990 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 991 #endif 992 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 993 if (++rxq->rxq_fi == GE_RXDESC_MAX) 994 rxq->rxq_fi = 0; 995 rxq->rxq_active++; 996 } 997 rxq->rxq_curpkt = m; 998 GE_FUNC_EXIT(sc, ""); 999 } 1000 1001 uint32_t 1002 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 1003 { 1004 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1005 struct gfe_rxqueue *rxq; 1006 uint32_t rxbits; 1007 #define RXPRIO_DECODER 0xffffaa50 1008 GE_FUNC_ENTER(sc, "gfe_rx_process"); 1009 1010 rxbits = ETH_IR_RxBuffer_GET(cause); 1011 while (rxbits) { 1012 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 1013 GE_DPRINTF(sc, ("%1x", rxbits)); 1014 rxbits &= ~(1 << rxprio); 1015 gfe_rx_get(sc, rxprio); 1016 } 1017 1018 rxbits = ETH_IR_RxError_GET(cause); 1019 while (rxbits) { 1020 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 1021 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 1022 int idx; 1023 rxbits &= ~(1 << rxprio); 1024 rxq = &sc->sc_rxq[rxprio]; 1025 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 1026 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 1027 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 1028 sc->sc_tickflags |= GE_TICK_RX_RESTART; 1029 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 1030 } 1031 ifp->if_ierrors++; 1032 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 1033 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi)); 1034 memset(masks, 0, sizeof(masks)); 1035 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1036 0, rxq->rxq_desc_mem.gdm_size, 1037 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1038 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 1039 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 1040 1041 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 1042 masks[idx/32] |= 1 << (idx & 31); 1043 } 1044 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1045 0, rxq->rxq_desc_mem.gdm_size, 1046 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1047 #if defined(DEBUG) 1048 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 1049 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi, 1050 rxq->rxq_cmdsts, masks[0], masks[1]); 1051 #endif 1052 } 1053 if ((intrmask & ETH_IR_RxBits) == 0) 1054 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 1055 1056 GE_FUNC_EXIT(sc, ""); 1057 return intrmask; 1058 } 1059 1060 int 1061 gfe_rx_prime(struct gfe_softc *sc) 1062 { 1063 struct gfe_rxqueue *rxq; 1064 int error; 1065 1066 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 1067 1068 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 1069 if (error) 1070 goto bail; 1071 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1072 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1073 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1074 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1075 } 1076 sc->sc_intrmask |= rxq->rxq_intrbits; 1077 1078 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 1079 if (error) 1080 goto bail; 1081 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1082 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1083 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1084 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1085 sc->sc_intrmask |= rxq->rxq_intrbits; 1086 } 1087 1088 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 1089 if (error) 1090 goto bail; 1091 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1092 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1093 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1094 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1095 sc->sc_intrmask |= rxq->rxq_intrbits; 1096 } 1097 1098 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 1099 if (error) 1100 goto bail; 1101 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1102 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1103 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1104 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1105 sc->sc_intrmask |= rxq->rxq_intrbits; 1106 } 1107 1108 bail: 1109 GE_FUNC_EXIT(sc, ""); 1110 return error; 1111 } 1112 1113 void 1114 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 1115 { 1116 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 1117 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 1118 if (rxq == NULL) { 1119 GE_FUNC_EXIT(sc, ""); 1120 return; 1121 } 1122 1123 if (rxq->rxq_curpkt) 1124 m_freem(rxq->rxq_curpkt); 1125 if ((sc->sc_flags & GE_NOFREE) == 0) { 1126 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 1127 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 1128 } 1129 GE_FUNC_EXIT(sc, ""); 1130 } 1131 1132 void 1133 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1134 { 1135 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 1136 sc->sc_flags &= ~GE_RXACTIVE; 1137 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 1138 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 1139 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1140 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR); 1141 do { 1142 delay(10); 1143 } while (GE_READ(sc, ETH_ESDCMR) & ETH_ESDCMR_AR); 1144 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 1145 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 1146 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 1147 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 1148 GE_FUNC_EXIT(sc, ""); 1149 } 1150 1151 void 1152 gfe_tick(void *arg) 1153 { 1154 struct gfe_softc * const sc = arg; 1155 uint32_t intrmask; 1156 unsigned int tickflags; 1157 int s; 1158 1159 GE_FUNC_ENTER(sc, "gfe_tick"); 1160 1161 s = splnet(); 1162 1163 tickflags = sc->sc_tickflags; 1164 sc->sc_tickflags = 0; 1165 intrmask = sc->sc_intrmask; 1166 if (tickflags & GE_TICK_TX_IFSTART) 1167 gfe_ifstart(&sc->sc_ec.ec_if); 1168 if (tickflags & GE_TICK_RX_RESTART) { 1169 intrmask |= sc->sc_idlemask; 1170 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 1171 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1172 rxq->rxq_fi = 0; 1173 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1174 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1175 } 1176 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 1177 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1178 rxq->rxq_fi = 0; 1179 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1180 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1181 } 1182 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 1183 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1184 rxq->rxq_fi = 0; 1185 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1186 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1187 } 1188 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 1189 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1190 rxq->rxq_fi = 0; 1191 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1192 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1193 } 1194 sc->sc_idlemask = 0; 1195 } 1196 if (intrmask != sc->sc_intrmask) { 1197 sc->sc_intrmask = intrmask; 1198 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1199 } 1200 gfe_intr(sc); 1201 splx(s); 1202 1203 GE_FUNC_EXIT(sc, ""); 1204 } 1205 1206 int 1207 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1208 { 1209 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1210 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1211 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1212 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1213 uint32_t intrmask = sc->sc_intrmask; 1214 size_t buflen; 1215 struct mbuf *m; 1216 1217 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1218 1219 /* 1220 * Anything in the pending queue to enqueue? if not, punt. Likewise 1221 * if the txq is not yet created. 1222 * otherwise grab its dmamap. 1223 */ 1224 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1225 GE_FUNC_EXIT(sc, "-"); 1226 return 0; 1227 } 1228 1229 /* 1230 * Have we [over]consumed our limit of descriptors? 1231 * Do we have enough free descriptors? 1232 */ 1233 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1234 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1235 uint32_t cmdsts; 1236 size_t pktlen; 1237 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1238 cmdsts = gt32toh(txd2->ed_cmdsts); 1239 if (cmdsts & TX_CMD_O) { 1240 int nextin; 1241 /* 1242 * Sometime the Discovery forgets to update the 1243 * last descriptor. See if we own the descriptor 1244 * after it (since we know we've turned that to 1245 * the discovery and if we owned it, the Discovery 1246 * gave it back). If we do, we know the Discovery 1247 * gave back this one but forgot to mark it as ours. 1248 */ 1249 nextin = txq->txq_fi + 1; 1250 if (nextin == GE_TXDESC_MAX) 1251 nextin = 0; 1252 GE_TXDPOSTSYNC(sc, txq, nextin); 1253 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1254 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1255 GE_TXDPRESYNC(sc, txq, nextin); 1256 GE_FUNC_EXIT(sc, "@"); 1257 return 0; 1258 } 1259 #ifdef DEBUG 1260 printf("%s: txenqueue: transmitter resynced at %d\n", 1261 device_xname(sc->sc_dev), txq->txq_fi); 1262 #endif 1263 } 1264 if (++txq->txq_fi == GE_TXDESC_MAX) 1265 txq->txq_fi = 0; 1266 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1267 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1268 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1269 txq->txq_nactive--; 1270 1271 /* statistics */ 1272 ifp->if_opackets++; 1273 if (cmdsts & TX_STS_ES) 1274 ifp->if_oerrors++; 1275 GE_DPRINTF(sc, ("%%")); 1276 } 1277 1278 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1279 1280 /* 1281 * If this packet would wrap around the end of the buffer, reset back 1282 * to the beginning. 1283 */ 1284 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1285 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1286 txq->txq_outptr = 0; 1287 } 1288 1289 /* 1290 * Make sure the output packet doesn't run over the beginning of 1291 * what we've already given the GT. 1292 */ 1293 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1294 txq->txq_outptr + buflen > txq->txq_inptr) { 1295 intrmask |= txq->txq_intrbits & 1296 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1297 if (sc->sc_intrmask != intrmask) { 1298 sc->sc_intrmask = intrmask; 1299 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1300 } 1301 GE_FUNC_EXIT(sc, "#"); 1302 return 0; 1303 } 1304 1305 /* 1306 * The end-of-list descriptor we put on last time is the starting point 1307 * for this packet. The GT is supposed to terminate list processing on 1308 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1309 * must terminate the list. 1310 */ 1311 intrmask = sc->sc_intrmask; 1312 1313 m_copydata(m, 0, m->m_pkthdr.len, 1314 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1315 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1316 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1317 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1318 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1319 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1320 1321 /* 1322 * Request a buffer interrupt every 2/3 of the way thru the transmit 1323 * buffer. 1324 */ 1325 txq->txq_ei_gapcount += buflen; 1326 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1327 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1328 txq->txq_ei_gapcount = 0; 1329 } else { 1330 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1331 } 1332 #if 0 1333 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1334 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1335 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1336 #endif 1337 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1338 1339 txq->txq_outptr += buflen; 1340 /* 1341 * Tell the SDMA engine to "Fetch!" 1342 */ 1343 GE_WRITE(sc, ETH_ESDCMR, 1344 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1345 1346 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1347 1348 /* 1349 * Update the last out appropriately. 1350 */ 1351 txq->txq_nactive++; 1352 if (++txq->txq_lo == GE_TXDESC_MAX) 1353 txq->txq_lo = 0; 1354 1355 /* 1356 * Move mbuf from the pending queue to the snd queue. 1357 */ 1358 IF_DEQUEUE(&txq->txq_pendq, m); 1359 bpf_mtap(ifp, m); 1360 m_freem(m); 1361 ifp->if_flags &= ~IFF_OACTIVE; 1362 1363 /* 1364 * Since we have put an item into the packet queue, we now want 1365 * an interrupt when the transmit queue finishes processing the 1366 * list. But only update the mask if needs changing. 1367 */ 1368 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1369 if (sc->sc_intrmask != intrmask) { 1370 sc->sc_intrmask = intrmask; 1371 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1372 } 1373 if (ifp->if_timer == 0) 1374 ifp->if_timer = 5; 1375 GE_FUNC_EXIT(sc, "*"); 1376 return 1; 1377 } 1378 1379 uint32_t 1380 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1381 { 1382 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1383 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1384 1385 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1386 1387 if (txq == NULL) { 1388 GE_FUNC_EXIT(sc, ""); 1389 return intrmask; 1390 } 1391 1392 while (txq->txq_nactive > 0) { 1393 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1394 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1395 uint32_t cmdsts; 1396 size_t pktlen; 1397 1398 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1399 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1400 int nextin; 1401 1402 if (txq->txq_nactive == 1) { 1403 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1404 GE_FUNC_EXIT(sc, ""); 1405 return intrmask; 1406 } 1407 /* 1408 * Sometimes the Discovery forgets to update the 1409 * ownership bit in the descriptor. See if we own the 1410 * descriptor after it (since we know we've turned 1411 * that to the Discovery and if we own it now then the 1412 * Discovery gave it back). If we do, we know the 1413 * Discovery gave back this one but forgot to mark it 1414 * as ours. 1415 */ 1416 nextin = txq->txq_fi + 1; 1417 if (nextin == GE_TXDESC_MAX) 1418 nextin = 0; 1419 GE_TXDPOSTSYNC(sc, txq, nextin); 1420 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1421 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1422 GE_TXDPRESYNC(sc, txq, nextin); 1423 GE_FUNC_EXIT(sc, ""); 1424 return intrmask; 1425 } 1426 #ifdef DEBUG 1427 printf("%s: txdone: transmitter resynced at %d\n", 1428 device_xname(sc->sc_dev), txq->txq_fi); 1429 #endif 1430 } 1431 #if 0 1432 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1433 txq->txq_lo, 1434 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1435 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1436 #endif 1437 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1438 if (++txq->txq_fi == GE_TXDESC_MAX) 1439 txq->txq_fi = 0; 1440 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1441 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1442 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1443 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1444 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1445 1446 /* statistics */ 1447 ifp->if_opackets++; 1448 if (cmdsts & TX_STS_ES) 1449 ifp->if_oerrors++; 1450 1451 /* txd->ed_bufptr = 0; */ 1452 1453 ifp->if_timer = 5; 1454 --txq->txq_nactive; 1455 } 1456 if (txq->txq_nactive != 0) 1457 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1458 device_xname(sc->sc_dev), txprio, txq->txq_nactive); 1459 ifp->if_timer = 0; 1460 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1461 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1462 GE_FUNC_EXIT(sc, ""); 1463 return intrmask; 1464 } 1465 1466 int 1467 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1468 { 1469 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1470 int error; 1471 1472 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1473 1474 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1475 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1476 if (error) { 1477 GE_FUNC_EXIT(sc, ""); 1478 return error; 1479 } 1480 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1481 if (error) { 1482 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1483 GE_FUNC_EXIT(sc, ""); 1484 return error; 1485 } 1486 GE_FUNC_EXIT(sc, ""); 1487 return 0; 1488 } 1489 1490 int 1491 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1492 { 1493 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1494 volatile struct gt_eth_desc *txd; 1495 unsigned int i; 1496 bus_addr_t addr; 1497 1498 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1499 1500 sc->sc_intrmask &= 1501 ~(ETH_IR_TxEndHigh | 1502 ETH_IR_TxBufferHigh | 1503 ETH_IR_TxEndLow | 1504 ETH_IR_TxBufferLow); 1505 1506 if (sc->sc_flags & GE_NOFREE) { 1507 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1508 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1509 } else { 1510 int error = gfe_tx_txqalloc(sc, txprio); 1511 if (error) { 1512 GE_FUNC_EXIT(sc, "!"); 1513 return error; 1514 } 1515 } 1516 1517 txq->txq_descs = 1518 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1519 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1520 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1521 1522 txq->txq_pendq.ifq_maxlen = 10; 1523 txq->txq_ei_gapcount = 0; 1524 txq->txq_nactive = 0; 1525 txq->txq_fi = 0; 1526 txq->txq_lo = 0; 1527 txq->txq_inptr = GE_TXBUF_SIZE; 1528 txq->txq_outptr = 0; 1529 for (i = 0, txd = txq->txq_descs, 1530 addr = txq->txq_desc_busaddr + sizeof(*txd); 1531 i < GE_TXDESC_MAX - 1; i++, txd++, addr += sizeof(*txd)) { 1532 /* 1533 * update the nxtptr to point to the next txd. 1534 */ 1535 txd->ed_cmdsts = 0; 1536 txd->ed_nxtptr = htogt32(addr); 1537 } 1538 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1539 htogt32(txq->txq_desc_busaddr); 1540 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1541 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1542 1543 switch (txprio) { 1544 case GE_TXPRIO_HI: 1545 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1546 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1547 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1548 txq->txq_ectdp = ETH_ECTDP1; 1549 GE_WRITE(sc, ETH_ECTDP1, txq->txq_desc_busaddr); 1550 break; 1551 1552 case GE_TXPRIO_LO: 1553 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1554 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1555 txq->txq_epsrbits = ETH_EPSR_TxLow; 1556 txq->txq_ectdp = ETH_ECTDP0; 1557 GE_WRITE(sc, ETH_ECTDP0, txq->txq_desc_busaddr); 1558 break; 1559 1560 case GE_TXPRIO_NONE: 1561 break; 1562 } 1563 #if 0 1564 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1565 GE_WRITE(sc->sc_dev, txq->txq_ectdp, txq->txq_desc_busaddr); 1566 GE_DPRINTF(sc, (")")); 1567 #endif 1568 1569 /* 1570 * If we are restarting, there may be packets in the pending queue 1571 * waiting to be enqueued. Try enqueuing packets from both priority 1572 * queues until the pending queue is empty or there no room for them 1573 * on the device. 1574 */ 1575 while (gfe_tx_enqueue(sc, txprio)) 1576 continue; 1577 1578 GE_FUNC_EXIT(sc, ""); 1579 return 0; 1580 } 1581 1582 void 1583 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1584 { 1585 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1586 1587 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1588 if (txq == NULL) { 1589 GE_FUNC_EXIT(sc, ""); 1590 return; 1591 } 1592 1593 if (!flush) { 1594 GE_FUNC_EXIT(sc, ""); 1595 return; 1596 } 1597 1598 if ((sc->sc_flags & GE_NOFREE) == 0) { 1599 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1600 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1601 } 1602 GE_FUNC_EXIT(sc, "-F"); 1603 } 1604 1605 void 1606 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1607 { 1608 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1609 1610 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1611 1612 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1613 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1614 sc->sc_intrmask &= 1615 ~(ETH_IR_TxEndHigh | 1616 ETH_IR_TxBufferHigh | 1617 ETH_IR_TxEndLow | 1618 ETH_IR_TxBufferLow); 1619 1620 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1621 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1622 1623 sc->sc_ec.ec_if.if_timer = 0; 1624 GE_FUNC_EXIT(sc, ""); 1625 } 1626 1627 int 1628 gfe_intr(void *arg) 1629 { 1630 struct gfe_softc * const sc = arg; 1631 uint32_t cause; 1632 uint32_t intrmask = sc->sc_intrmask; 1633 int claim = 0; 1634 int cnt; 1635 1636 GE_FUNC_ENTER(sc, "gfe_intr"); 1637 1638 for (cnt = 0; cnt < 4; cnt++) { 1639 if (sc->sc_intrmask != intrmask) { 1640 sc->sc_intrmask = intrmask; 1641 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1642 } 1643 cause = GE_READ(sc, ETH_EICR); 1644 cause &= sc->sc_intrmask; 1645 GE_DPRINTF(sc, (".%#x", cause)); 1646 if (cause == 0) 1647 break; 1648 1649 claim = 1; 1650 1651 GE_WRITE(sc, ETH_EICR, ~cause); 1652 #ifndef GE_NORX 1653 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1654 intrmask = gfe_rx_process(sc, cause, intrmask); 1655 #endif 1656 1657 #ifndef GE_NOTX 1658 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1659 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1660 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1661 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1662 #endif 1663 if (cause & ETH_IR_MIIPhySTC) { 1664 sc->sc_flags |= GE_PHYSTSCHG; 1665 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1666 } 1667 } 1668 1669 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1670 continue; 1671 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1672 continue; 1673 1674 GE_FUNC_EXIT(sc, ""); 1675 return claim; 1676 } 1677 1678 int 1679 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1680 { 1681 int error = 0; 1682 GE_FUNC_ENTER(sc, "gfe_whack"); 1683 1684 switch (op) { 1685 case GE_WHACK_RESTART: 1686 #ifndef GE_NOTX 1687 gfe_tx_stop(sc, op); 1688 #endif 1689 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1690 /* FALLTHROUGH */ 1691 case GE_WHACK_START: 1692 #ifndef GE_NOHASH 1693 if (error == 0 && sc->sc_hashtable == NULL) { 1694 error = gfe_hash_alloc(sc); 1695 if (error) 1696 break; 1697 } 1698 if (op != GE_WHACK_RESTART) 1699 gfe_hash_fill(sc); 1700 #endif 1701 #ifndef GE_NORX 1702 if (op != GE_WHACK_RESTART) { 1703 error = gfe_rx_prime(sc); 1704 if (error) 1705 break; 1706 } 1707 #endif 1708 #ifndef GE_NOTX 1709 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1710 if (error) 1711 break; 1712 #endif 1713 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1714 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1715 GE_WRITE(sc, ETH_EPCXR, sc->sc_pcxr); 1716 GE_WRITE(sc, ETH_EICR, 0); 1717 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1718 #ifndef GE_NOHASH 1719 GE_WRITE(sc, ETH_EHTPR, 1720 sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1721 #endif 1722 #ifndef GE_NORX 1723 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_ERD); 1724 sc->sc_flags |= GE_RXACTIVE; 1725 #endif 1726 /* FALLTHROUGH */ 1727 case GE_WHACK_CHANGE: 1728 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1729 GE_READ(sc, ETH_EPCR), GE_READ(sc, ETH_EIMR))); 1730 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1731 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1732 gfe_ifstart(&sc->sc_ec.ec_if); 1733 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1734 GE_READ(sc, ETH_ECTDP0), GE_READ(sc, ETH_ECTDP1))); 1735 GE_FUNC_EXIT(sc, ""); 1736 return error; 1737 case GE_WHACK_STOP: 1738 break; 1739 } 1740 1741 #ifdef GE_DEBUG 1742 if (error) 1743 GE_DPRINTF(sc, (" failed: %d\n", error)); 1744 #endif 1745 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1746 GE_WRITE(sc, ETH_EIMR, 0); 1747 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1748 #ifndef GE_NOTX 1749 gfe_tx_stop(sc, GE_WHACK_STOP); 1750 #endif 1751 #ifndef GE_NORX 1752 gfe_rx_stop(sc, GE_WHACK_STOP); 1753 #endif 1754 #ifndef GE_NOHASH 1755 if ((sc->sc_flags & GE_NOFREE) == 0) { 1756 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1757 sc->sc_hashtable = NULL; 1758 } 1759 #endif 1760 1761 GE_FUNC_EXIT(sc, ""); 1762 return error; 1763 } 1764 1765 int 1766 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1767 { 1768 uint32_t w0, add0, add1; 1769 uint32_t result; 1770 1771 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1772 add0 = ((uint32_t) eaddr[5] << 0) | 1773 ((uint32_t) eaddr[4] << 8) | 1774 ((uint32_t) eaddr[3] << 16); 1775 1776 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1777 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1778 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1779 1780 add1 = ((uint32_t) eaddr[2] << 0) | 1781 ((uint32_t) eaddr[1] << 8) | 1782 ((uint32_t) eaddr[0] << 16); 1783 1784 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1785 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1786 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1787 1788 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1789 /* 1790 * hashResult is the 15 bits Hash entry address. 1791 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1792 * MAC address, by nibble swapping in every byte (i.e MAC address 1793 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1794 */ 1795 1796 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1797 /* 1798 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1799 * 1800 * hashFunc0 calculates the hashResult in the following manner: 1801 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1802 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1803 */ 1804 result = (add0 & 3) | ((add0 >> 6) & ~3); 1805 result ^= (add0 >> 15) ^ (add1 >> 0); 1806 result &= 0x1ff; 1807 /* 1808 * hashResult[14:9] = ethernetADD[7:2] 1809 */ 1810 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1811 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1812 } else { 1813 #define TRIBITFLIP 073516240 /* yes its in octal */ 1814 /* 1815 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1816 * 1817 * hashFunc1 calculates the hashResult in the following manner: 1818 * hashResult[08:00] = ethernetADD[06:14] 1819 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1820 */ 1821 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1822 /* 1823 * Now bitswap those 9 bits 1824 */ 1825 result = 0; 1826 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1827 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1828 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1829 1830 /* 1831 * hashResult[14:09] = ethernetADD[00:05] 1832 */ 1833 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1834 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1835 GE_DPRINTF(sc, ("1(%#x)", result)); 1836 } 1837 GE_FUNC_EXIT(sc, ""); 1838 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1839 } 1840 1841 int 1842 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1843 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1844 { 1845 uint64_t he; 1846 uint64_t *maybe_he_p = NULL; 1847 int limit; 1848 int hash; 1849 int maybe_hash = 0; 1850 1851 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1852 1853 hash = gfe_hash_compute(sc, eaddr); 1854 1855 if (sc->sc_hashtable == NULL) { 1856 panic("%s:%d: hashtable == NULL!", device_xname(sc->sc_dev), 1857 __LINE__); 1858 } 1859 1860 /* 1861 * Assume we are going to insert so create the hash entry we 1862 * are going to insert. We also use it to match entries we 1863 * will be removing. 1864 */ 1865 he = ((uint64_t) eaddr[5] << 43) | 1866 ((uint64_t) eaddr[4] << 35) | 1867 ((uint64_t) eaddr[3] << 27) | 1868 ((uint64_t) eaddr[2] << 19) | 1869 ((uint64_t) eaddr[1] << 11) | 1870 ((uint64_t) eaddr[0] << 3) | 1871 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1872 1873 /* 1874 * The GT will search upto 12 entries for a hit, so we must mimic that. 1875 */ 1876 hash &= sc->sc_hashmask / sizeof(he); 1877 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1878 /* 1879 * Does the GT wrap at the end, stop at the, or overrun the 1880 * end? Assume it wraps for now. Stash a copy of the 1881 * current hash entry. 1882 */ 1883 uint64_t *he_p = &sc->sc_hashtable[hash]; 1884 uint64_t thishe = *he_p; 1885 1886 /* 1887 * If the hash entry isn't valid, that break the chain. And 1888 * this entry a good candidate for reuse. 1889 */ 1890 if ((thishe & HSH_V) == 0) { 1891 maybe_he_p = he_p; 1892 break; 1893 } 1894 1895 /* 1896 * If the hash entry has the same address we are looking for 1897 * then ... if we are removing and the skip bit is set, its 1898 * already been removed. if are adding and the skip bit is 1899 * clear, then its already added. In either return EBUSY 1900 * indicating the op has already been done. Otherwise flip 1901 * the skip bit and return 0. 1902 */ 1903 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1904 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1905 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1906 return EBUSY; 1907 *he_p = thishe ^ HSH_S; 1908 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1909 hash * sizeof(he), sizeof(he), 1910 BUS_DMASYNC_PREWRITE); 1911 GE_FUNC_EXIT(sc, "^"); 1912 return 0; 1913 } 1914 1915 /* 1916 * If we haven't found a slot for the entry and this entry 1917 * is currently being skipped, return this entry. 1918 */ 1919 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1920 maybe_he_p = he_p; 1921 maybe_hash = hash; 1922 } 1923 1924 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1925 } 1926 1927 /* 1928 * If we got here, then there was no entry to remove. 1929 */ 1930 if (op == GE_HASH_REMOVE) { 1931 GE_FUNC_EXIT(sc, "?"); 1932 return ENOENT; 1933 } 1934 1935 /* 1936 * If we couldn't find a slot, return an error. 1937 */ 1938 if (maybe_he_p == NULL) { 1939 GE_FUNC_EXIT(sc, "!"); 1940 return ENOSPC; 1941 } 1942 1943 /* Update the entry. 1944 */ 1945 *maybe_he_p = he; 1946 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1947 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1948 GE_FUNC_EXIT(sc, "+"); 1949 return 0; 1950 } 1951 1952 int 1953 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, 1954 u_long cmd) 1955 { 1956 struct gfe_softc *sc = ec->ec_if.if_softc; 1957 int error; 1958 enum gfe_hash_op op; 1959 enum gfe_rxprio prio; 1960 1961 GE_FUNC_ENTER(sc, "hash_multichg"); 1962 /* 1963 * Is this a wildcard entry? If so and its being removed, recompute. 1964 */ 1965 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1966 if (cmd == SIOCDELMULTI) { 1967 GE_FUNC_EXIT(sc, ""); 1968 return ENETRESET; 1969 } 1970 1971 /* 1972 * Switch in 1973 */ 1974 sc->sc_flags |= GE_ALLMULTI; 1975 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1976 sc->sc_pcr |= ETH_EPCR_PM; 1977 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1978 GE_FUNC_EXIT(sc, ""); 1979 return 0; 1980 } 1981 GE_FUNC_EXIT(sc, ""); 1982 return ENETRESET; 1983 } 1984 1985 prio = GE_RXPRIO_MEDLO; 1986 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1987 1988 if (sc->sc_hashtable == NULL) { 1989 GE_FUNC_EXIT(sc, ""); 1990 return 0; 1991 } 1992 1993 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1994 if (error == EBUSY) { 1995 aprint_error_dev(sc->sc_dev, "multichg: tried to %s %s again\n", 1996 cmd == SIOCDELMULTI ? "remove" : "add", 1997 ether_sprintf(enm->enm_addrlo)); 1998 GE_FUNC_EXIT(sc, ""); 1999 return 0; 2000 } 2001 2002 if (error == ENOENT) { 2003 aprint_error_dev(sc->sc_dev, 2004 "multichg: failed to remove %s: not in table\n", 2005 ether_sprintf(enm->enm_addrlo)); 2006 GE_FUNC_EXIT(sc, ""); 2007 return 0; 2008 } 2009 2010 if (error == ENOSPC) { 2011 aprint_error_dev(sc->sc_dev, "multichg:" 2012 " failed to add %s: no space; regenerating table\n", 2013 ether_sprintf(enm->enm_addrlo)); 2014 GE_FUNC_EXIT(sc, ""); 2015 return ENETRESET; 2016 } 2017 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 2018 device_xname(sc->sc_dev), 2019 cmd == SIOCDELMULTI ? "remove" : "add", 2020 ether_sprintf(enm->enm_addrlo))); 2021 GE_FUNC_EXIT(sc, ""); 2022 return 0; 2023 } 2024 2025 int 2026 gfe_hash_fill(struct gfe_softc *sc) 2027 { 2028 struct ether_multistep step; 2029 struct ether_multi *enm; 2030 int error; 2031 2032 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 2033 2034 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 2035 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 2036 if (error) 2037 GE_FUNC_EXIT(sc, "!"); 2038 return error; 2039 2040 sc->sc_flags &= ~GE_ALLMULTI; 2041 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 2042 sc->sc_pcr &= ~ETH_EPCR_PM; 2043 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 2044 while (enm != NULL) { 2045 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2046 sc->sc_flags |= GE_ALLMULTI; 2047 sc->sc_pcr |= ETH_EPCR_PM; 2048 } else { 2049 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 2050 GE_RXPRIO_MEDLO, enm->enm_addrlo); 2051 if (error == ENOSPC) 2052 break; 2053 } 2054 ETHER_NEXT_MULTI(step, enm); 2055 } 2056 2057 GE_FUNC_EXIT(sc, ""); 2058 return error; 2059 } 2060 2061 int 2062 gfe_hash_alloc(struct gfe_softc *sc) 2063 { 2064 int error; 2065 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 2066 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 2067 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 2068 BUS_DMA_NOCACHE); 2069 if (error) { 2070 aprint_error_dev(sc->sc_dev, 2071 "failed to allocate %d bytes for hash table: %d\n", 2072 sc->sc_hashmask + 1, error); 2073 GE_FUNC_EXIT(sc, ""); 2074 return error; 2075 } 2076 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 2077 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 2078 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 2079 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 2080 GE_FUNC_EXIT(sc, ""); 2081 return 0; 2082 } 2083