1 /* $NetBSD: if_gfe.c,v 1.26 2007/10/19 12:00:33 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.26 2007/10/19 12:00:33 ad Exp $"); 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/inttypes.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <sys/callout.h> 58 #include <sys/device.h> 59 #include <sys/errno.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/socket.h> 63 64 #include <sys/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <dev/mii/miivar.h> 80 81 #include <dev/marvell/gtintrreg.h> 82 #include <dev/marvell/gtethreg.h> 83 84 #include <dev/marvell/gtvar.h> 85 #include <dev/marvell/if_gfevar.h> 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) do \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 while (0) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 STATIC int gfe_match (struct device *, struct cfdata *, void *); 148 STATIC void gfe_attach (struct device *, struct device *, void *); 149 150 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 151 size_t, int); 152 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 153 154 STATIC int gfe_ifioctl (struct ifnet *, u_long, void *); 155 STATIC void gfe_ifstart (struct ifnet *); 156 STATIC void gfe_ifwatchdog (struct ifnet *); 157 158 STATIC int gfe_mii_mediachange (struct ifnet *); 159 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 160 STATIC int gfe_mii_read (struct device *, int, int); 161 STATIC void gfe_mii_write (struct device *, int, int, int); 162 STATIC void gfe_mii_statchg (struct device *); 163 164 STATIC void gfe_tick(void *arg); 165 166 STATIC void gfe_tx_restart(void *); 167 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 168 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 169 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 170 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 171 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 172 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 173 174 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 175 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 176 STATIC int gfe_rx_prime(struct gfe_softc *); 177 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 178 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 179 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 180 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 181 182 STATIC int gfe_intr(void *); 183 184 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 185 186 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 187 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 188 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 189 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 190 u_long); 191 STATIC int gfe_hash_fill(struct gfe_softc *); 192 STATIC int gfe_hash_alloc(struct gfe_softc *); 193 194 /* Linkup to the rest of the kernel */ 195 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 196 gfe_match, gfe_attach, NULL, NULL); 197 198 extern struct cfdriver gfe_cd; 199 200 int 201 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 202 { 203 struct gt_softc *gt = (struct gt_softc *) parent; 204 struct gt_attach_args *ga = aux; 205 uint8_t enaddr[6]; 206 207 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 208 return 0; 209 210 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 211 return 0; 212 213 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 214 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 215 return 0; 216 217 return 1; 218 } 219 220 /* 221 * Attach this instance, and then all the sub-devices 222 */ 223 void 224 gfe_attach(struct device *parent, struct device *self, void *aux) 225 { 226 struct gt_attach_args * const ga = aux; 227 struct gt_softc * const gt = device_private(parent); 228 struct gfe_softc * const sc = device_private(self); 229 struct ifnet * const ifp = &sc->sc_ec.ec_if; 230 uint32_t data; 231 uint8_t enaddr[6]; 232 int phyaddr; 233 uint32_t sdcr; 234 int error; 235 236 GT_ETHERFOUND(gt, ga); 237 238 sc->sc_gt_memt = ga->ga_memt; 239 sc->sc_gt_memh = ga->ga_memh; 240 sc->sc_dmat = ga->ga_dmat; 241 sc->sc_macno = ga->ga_unit; 242 243 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 244 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 245 aprint_error(": failed to map registers\n"); 246 } 247 248 callout_init(&sc->sc_co, 0); 249 250 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 251 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 252 253 gtget_macaddr(gt, sc->sc_macno, enaddr); 254 255 sc->sc_pcr = GE_READ(sc, EPCR); 256 sc->sc_pcxr = GE_READ(sc, EPCXR); 257 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 258 259 aprint_normal(": address %s", ether_sprintf(enaddr)); 260 261 #if defined(DEBUG) 262 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 263 #endif 264 265 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 266 if (device_cfdata(&sc->sc_dev)->cf_flags & 1) { 267 aprint_normal(", phy %d (rmii)", phyaddr); 268 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 269 } else { 270 aprint_normal(", phy %d (mii)", phyaddr); 271 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 272 } 273 if (device_cfdata(&sc->sc_dev)->cf_flags & 2) 274 sc->sc_flags |= GE_NOFREE; 275 sc->sc_pcxr &= ~(3 << 14); 276 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 277 278 if (sc->sc_pcr & ETH_EPCR_EN) { 279 int tries = 1000; 280 /* 281 * Abort transmitter and receiver and wait for them to quiese 282 */ 283 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 284 do { 285 delay(100); 286 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 287 } 288 289 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 290 291 #if defined(DEBUG) 292 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 293 #endif 294 295 /* 296 * Now turn off the GT. If it didn't quiese, too ***ing bad. 297 */ 298 GE_WRITE(sc, EPCR, sc->sc_pcr); 299 GE_WRITE(sc, EIMR, sc->sc_intrmask); 300 sdcr = GE_READ(sc, ESDCR); 301 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 302 sdcr |= ETH_ESDCR_RIFB; 303 GE_WRITE(sc, ESDCR, sdcr); 304 sc->sc_max_frame_length = 1536; 305 306 aprint_normal("\n"); 307 sc->sc_mii.mii_ifp = ifp; 308 sc->sc_mii.mii_readreg = gfe_mii_read; 309 sc->sc_mii.mii_writereg = gfe_mii_write; 310 sc->sc_mii.mii_statchg = gfe_mii_statchg; 311 312 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 313 gfe_mii_mediastatus); 314 315 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 316 MII_OFFSET_ANY, MIIF_NOISOLATE); 317 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 318 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 319 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 320 } else { 321 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 322 } 323 324 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 325 ifp->if_softc = sc; 326 /* ifp->if_mowner = &sc->sc_mowner; */ 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 #if 0 329 ifp->if_flags |= IFF_DEBUG; 330 #endif 331 ifp->if_ioctl = gfe_ifioctl; 332 ifp->if_start = gfe_ifstart; 333 ifp->if_watchdog = gfe_ifwatchdog; 334 335 if (sc->sc_flags & GE_NOFREE) { 336 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 337 if (!error) 338 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 339 if (!error) 340 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 341 if (!error) 342 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 343 if (!error) 344 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 345 if (!error) 346 error = gfe_hash_alloc(sc); 347 if (error) 348 aprint_error( 349 "%s: failed to allocate resources: %d\n", 350 ifp->if_xname, error); 351 } 352 353 if_attach(ifp); 354 ether_ifattach(ifp, enaddr); 355 #if NBPFILTER > 0 356 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 357 #endif 358 #if NRND > 0 359 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 360 #endif 361 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 362 gfe_intr, sc); 363 } 364 365 int 366 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 367 size_t size, int flags) 368 { 369 int error = 0; 370 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 371 372 KASSERT(gdm->gdm_kva == NULL); 373 gdm->gdm_size = size; 374 gdm->gdm_maxsegs = maxsegs; 375 376 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 377 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 378 BUS_DMA_NOWAIT); 379 if (error) 380 goto fail; 381 382 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 383 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 384 if (error) 385 goto fail; 386 387 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 388 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 389 if (error) 390 goto fail; 391 392 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 393 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 394 if (error) 395 goto fail; 396 397 /* invalidate from cache */ 398 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 399 BUS_DMASYNC_PREREAD); 400 fail: 401 if (error) { 402 gfe_dmamem_free(sc, gdm); 403 GE_DPRINTF(sc, (":err=%d", error)); 404 } 405 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 406 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 407 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 408 GE_FUNC_EXIT(sc, ""); 409 return error; 410 } 411 412 void 413 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 414 { 415 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 416 if (gdm->gdm_map) 417 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 418 if (gdm->gdm_kva) 419 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 420 if (gdm->gdm_nsegs > 0) 421 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 422 gdm->gdm_map = NULL; 423 gdm->gdm_kva = NULL; 424 gdm->gdm_nsegs = 0; 425 GE_FUNC_EXIT(sc, ""); 426 } 427 428 int 429 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 430 { 431 struct gfe_softc * const sc = ifp->if_softc; 432 struct ifreq *ifr = (struct ifreq *) data; 433 struct ifaddr *ifa = (struct ifaddr *) data; 434 int s, error = 0; 435 436 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 437 s = splnet(); 438 439 switch (cmd) { 440 case SIOCSIFADDR: 441 ifp->if_flags |= IFF_UP; 442 switch (ifa->ifa_addr->sa_family) { 443 #ifdef INET 444 case AF_INET: 445 error = gfe_whack(sc, GE_WHACK_START); 446 if (error == 0) 447 arp_ifinit(ifp, ifa); 448 break; 449 #endif 450 default: 451 error = gfe_whack(sc, GE_WHACK_START); 452 break; 453 } 454 break; 455 456 case SIOCSIFFLAGS: 457 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 458 case IFF_UP|IFF_RUNNING:/* active->active, update */ 459 error = gfe_whack(sc, GE_WHACK_CHANGE); 460 break; 461 case IFF_RUNNING: /* not up, so we stop */ 462 error = gfe_whack(sc, GE_WHACK_STOP); 463 break; 464 case IFF_UP: /* not running, so we start */ 465 error = gfe_whack(sc, GE_WHACK_START); 466 break; 467 case 0: /* idle->idle: do nothing */ 468 break; 469 } 470 break; 471 472 case SIOCADDMULTI: 473 case SIOCDELMULTI: 474 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 475 if (ifp->if_flags & IFF_RUNNING) 476 error = gfe_whack(sc, GE_WHACK_CHANGE); 477 else 478 error = 0; 479 } 480 break; 481 482 case SIOCSIFMTU: 483 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 484 error = EINVAL; 485 break; 486 } 487 ifp->if_mtu = ifr->ifr_mtu; 488 break; 489 490 case SIOCSIFMEDIA: 491 case SIOCGIFMEDIA: 492 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 493 break; 494 495 default: 496 error = EINVAL; 497 break; 498 } 499 splx(s); 500 GE_FUNC_EXIT(sc, ""); 501 return error; 502 } 503 504 void 505 gfe_ifstart(struct ifnet *ifp) 506 { 507 struct gfe_softc * const sc = ifp->if_softc; 508 struct mbuf *m; 509 510 GE_FUNC_ENTER(sc, "gfe_ifstart"); 511 512 if ((ifp->if_flags & IFF_RUNNING) == 0) { 513 GE_FUNC_EXIT(sc, "$"); 514 return; 515 } 516 517 for (;;) { 518 IF_DEQUEUE(&ifp->if_snd, m); 519 if (m == NULL) { 520 ifp->if_flags &= ~IFF_OACTIVE; 521 GE_FUNC_EXIT(sc, ""); 522 return; 523 } 524 525 /* 526 * No space in the pending queue? try later. 527 */ 528 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 529 break; 530 531 /* 532 * Try to enqueue a mbuf to the device. If that fails, we 533 * can always try to map the next mbuf. 534 */ 535 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 536 GE_DPRINTF(sc, (">")); 537 #ifndef GE_NOTX 538 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 539 #endif 540 } 541 542 /* 543 * Attempt to queue the mbuf for send failed. 544 */ 545 IF_PREPEND(&ifp->if_snd, m); 546 ifp->if_flags |= IFF_OACTIVE; 547 GE_FUNC_EXIT(sc, "%%"); 548 } 549 550 void 551 gfe_ifwatchdog(struct ifnet *ifp) 552 { 553 struct gfe_softc * const sc = ifp->if_softc; 554 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 555 556 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 557 printf("%s: device timeout", sc->sc_dev.dv_xname); 558 if (ifp->if_flags & IFF_RUNNING) { 559 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 560 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 561 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 562 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 563 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 564 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 565 GE_READ(sc, EICR)); 566 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 567 GE_TXDPRESYNC(sc, txq, curtxdnum); 568 } 569 printf("\n"); 570 ifp->if_oerrors++; 571 (void) gfe_whack(sc, GE_WHACK_RESTART); 572 GE_FUNC_EXIT(sc, ""); 573 } 574 575 int 576 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 577 { 578 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 579 int error; 580 581 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 582 GE_DPRINTF(sc, ("(%d)", rxprio)); 583 584 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 585 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 586 if (error) { 587 GE_FUNC_EXIT(sc, "!!"); 588 return error; 589 } 590 591 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 592 GE_RXBUF_MEMSIZE, 0); 593 if (error) { 594 GE_FUNC_EXIT(sc, "!!!"); 595 return error; 596 } 597 GE_FUNC_EXIT(sc, ""); 598 return error; 599 } 600 601 int 602 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 603 { 604 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 605 volatile struct gt_eth_desc *rxd; 606 const bus_dma_segment_t *ds; 607 int idx; 608 bus_addr_t nxtaddr; 609 bus_size_t boff; 610 611 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 612 GE_DPRINTF(sc, ("(%d)", rxprio)); 613 614 if ((sc->sc_flags & GE_NOFREE) == 0) { 615 int error = gfe_rx_rxqalloc(sc, rxprio); 616 if (error) { 617 GE_FUNC_EXIT(sc, "!"); 618 return error; 619 } 620 } else { 621 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 622 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 623 } 624 625 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 626 627 rxq->rxq_descs = 628 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 629 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 630 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 631 rxq->rxq_fi = 0; 632 rxq->rxq_active = GE_RXDESC_MAX; 633 for (idx = 0, rxd = rxq->rxq_descs, 634 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 635 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 636 idx < GE_RXDESC_MAX; 637 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 638 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 639 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 640 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 641 /* 642 * update the nxtptr to point to the next txd. 643 */ 644 if (idx == GE_RXDESC_MAX - 1) 645 nxtaddr = rxq->rxq_desc_busaddr; 646 rxd->ed_nxtptr = htogt32(nxtaddr); 647 boff += GE_RXBUF_SIZE; 648 if (boff == ds->ds_len) { 649 ds++; 650 boff = 0; 651 } 652 } 653 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 654 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 655 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 656 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 657 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 658 BUS_DMASYNC_PREREAD); 659 660 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 661 switch (rxprio) { 662 case GE_RXPRIO_HI: 663 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 664 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 665 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 666 break; 667 case GE_RXPRIO_MEDHI: 668 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 669 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 670 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 671 break; 672 case GE_RXPRIO_MEDLO: 673 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 674 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 675 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 676 break; 677 case GE_RXPRIO_LO: 678 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 679 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 680 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 681 break; 682 } 683 GE_FUNC_EXIT(sc, ""); 684 return 0; 685 } 686 687 void 688 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 689 { 690 struct ifnet * const ifp = &sc->sc_ec.ec_if; 691 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 692 struct mbuf *m = rxq->rxq_curpkt; 693 694 GE_FUNC_ENTER(sc, "gfe_rx_get"); 695 GE_DPRINTF(sc, ("(%d)", rxprio)); 696 697 while (rxq->rxq_active > 0) { 698 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 699 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 700 const struct ether_header *eh; 701 unsigned int cmdsts; 702 size_t buflen; 703 704 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 705 cmdsts = gt32toh(rxd->ed_cmdsts); 706 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 707 rxq->rxq_cmdsts = cmdsts; 708 /* 709 * Sometimes the GE "forgets" to reset the ownership bit. 710 * But if the length has been rewritten, the packet is ours 711 * so pretend the O bit is set. 712 */ 713 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 714 if ((cmdsts & RX_CMD_O) && buflen == 0) { 715 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 716 break; 717 } 718 719 /* 720 * If this is not a single buffer packet with no errors 721 * or for some reason it's bigger than our frame size, 722 * ignore it and go to the next packet. 723 */ 724 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 725 (RX_CMD_F|RX_CMD_L) || 726 buflen > sc->sc_max_frame_length) { 727 GE_DPRINTF(sc, ("!")); 728 --rxq->rxq_active; 729 ifp->if_ipackets++; 730 ifp->if_ierrors++; 731 goto give_it_back; 732 } 733 734 /* CRC is included with the packet; trim it off. */ 735 buflen -= ETHER_CRC_LEN; 736 737 if (m == NULL) { 738 MGETHDR(m, M_DONTWAIT, MT_DATA); 739 if (m == NULL) { 740 GE_DPRINTF(sc, ("?")); 741 break; 742 } 743 } 744 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 745 MCLGET(m, M_DONTWAIT); 746 if ((m->m_flags & M_EXT) == 0) { 747 GE_DPRINTF(sc, ("?")); 748 break; 749 } 750 } 751 m->m_data += 2; 752 m->m_len = 0; 753 m->m_pkthdr.len = 0; 754 m->m_pkthdr.rcvif = ifp; 755 rxq->rxq_cmdsts = cmdsts; 756 --rxq->rxq_active; 757 758 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 759 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 760 761 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 762 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 763 m->m_len = buflen; 764 m->m_pkthdr.len = buflen; 765 766 ifp->if_ipackets++; 767 #if NBPFILTER > 0 768 if (ifp->if_bpf != NULL) 769 bpf_mtap(ifp->if_bpf, m); 770 #endif 771 772 eh = (const struct ether_header *) m->m_data; 773 if ((ifp->if_flags & IFF_PROMISC) || 774 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 775 (rxq->rxq_cmdsts & RX_STS_HE) || 776 (eh->ether_dhost[0] & 1) != 0 || 777 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 778 ETHER_ADDR_LEN) == 0) { 779 (*ifp->if_input)(ifp, m); 780 m = NULL; 781 GE_DPRINTF(sc, (">")); 782 } else { 783 m->m_len = 0; 784 m->m_pkthdr.len = 0; 785 GE_DPRINTF(sc, ("+")); 786 } 787 rxq->rxq_cmdsts = 0; 788 789 give_it_back: 790 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 791 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 792 #if 0 793 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 794 rxq->rxq_fi, 795 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 796 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 797 #endif 798 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 799 if (++rxq->rxq_fi == GE_RXDESC_MAX) 800 rxq->rxq_fi = 0; 801 rxq->rxq_active++; 802 } 803 rxq->rxq_curpkt = m; 804 GE_FUNC_EXIT(sc, ""); 805 } 806 807 uint32_t 808 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 809 { 810 struct ifnet * const ifp = &sc->sc_ec.ec_if; 811 struct gfe_rxqueue *rxq; 812 uint32_t rxbits; 813 #define RXPRIO_DECODER 0xffffaa50 814 GE_FUNC_ENTER(sc, "gfe_rx_process"); 815 816 rxbits = ETH_IR_RxBuffer_GET(cause); 817 while (rxbits) { 818 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 819 GE_DPRINTF(sc, ("%1x", rxbits)); 820 rxbits &= ~(1 << rxprio); 821 gfe_rx_get(sc, rxprio); 822 } 823 824 rxbits = ETH_IR_RxError_GET(cause); 825 while (rxbits) { 826 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 827 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 828 int idx; 829 rxbits &= ~(1 << rxprio); 830 rxq = &sc->sc_rxq[rxprio]; 831 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 832 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 833 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 834 sc->sc_tickflags |= GE_TICK_RX_RESTART; 835 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 836 } 837 ifp->if_ierrors++; 838 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 839 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 840 memset(masks, 0, sizeof(masks)); 841 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 842 0, rxq->rxq_desc_mem.gdm_size, 843 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 844 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 845 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 846 847 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 848 masks[idx/32] |= 1 << (idx & 31); 849 } 850 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 851 0, rxq->rxq_desc_mem.gdm_size, 852 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 853 #if defined(DEBUG) 854 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 855 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 856 rxq->rxq_cmdsts, masks[0], masks[1]); 857 #endif 858 } 859 if ((intrmask & ETH_IR_RxBits) == 0) 860 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 861 862 GE_FUNC_EXIT(sc, ""); 863 return intrmask; 864 } 865 866 int 867 gfe_rx_prime(struct gfe_softc *sc) 868 { 869 struct gfe_rxqueue *rxq; 870 int error; 871 872 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 873 874 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 875 if (error) 876 goto bail; 877 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 878 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 879 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 880 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 881 } 882 sc->sc_intrmask |= rxq->rxq_intrbits; 883 884 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 885 if (error) 886 goto bail; 887 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 888 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 889 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 890 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 891 sc->sc_intrmask |= rxq->rxq_intrbits; 892 } 893 894 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 895 if (error) 896 goto bail; 897 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 898 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 899 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 900 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 901 sc->sc_intrmask |= rxq->rxq_intrbits; 902 } 903 904 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 905 if (error) 906 goto bail; 907 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 908 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 909 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 910 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 911 sc->sc_intrmask |= rxq->rxq_intrbits; 912 } 913 914 bail: 915 GE_FUNC_EXIT(sc, ""); 916 return error; 917 } 918 919 void 920 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 921 { 922 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 923 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 924 if (rxq == NULL) { 925 GE_FUNC_EXIT(sc, ""); 926 return; 927 } 928 929 if (rxq->rxq_curpkt) 930 m_freem(rxq->rxq_curpkt); 931 if ((sc->sc_flags & GE_NOFREE) == 0) { 932 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 933 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 934 } 935 GE_FUNC_EXIT(sc, ""); 936 } 937 938 void 939 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 940 { 941 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 942 sc->sc_flags &= ~GE_RXACTIVE; 943 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 944 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 945 GE_WRITE(sc, EIMR, sc->sc_intrmask); 946 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 947 do { 948 delay(10); 949 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 950 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 951 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 952 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 953 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 954 GE_FUNC_EXIT(sc, ""); 955 } 956 957 void 958 gfe_tick(void *arg) 959 { 960 struct gfe_softc * const sc = arg; 961 uint32_t intrmask; 962 unsigned int tickflags; 963 int s; 964 965 GE_FUNC_ENTER(sc, "gfe_tick"); 966 967 s = splnet(); 968 969 tickflags = sc->sc_tickflags; 970 sc->sc_tickflags = 0; 971 intrmask = sc->sc_intrmask; 972 if (tickflags & GE_TICK_TX_IFSTART) 973 gfe_ifstart(&sc->sc_ec.ec_if); 974 if (tickflags & GE_TICK_RX_RESTART) { 975 intrmask |= sc->sc_idlemask; 976 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 977 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 978 rxq->rxq_fi = 0; 979 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 980 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 981 } 982 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 983 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 984 rxq->rxq_fi = 0; 985 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 986 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 987 } 988 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 989 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 990 rxq->rxq_fi = 0; 991 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 992 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 993 } 994 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 995 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 996 rxq->rxq_fi = 0; 997 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 998 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 999 } 1000 sc->sc_idlemask = 0; 1001 } 1002 if (intrmask != sc->sc_intrmask) { 1003 sc->sc_intrmask = intrmask; 1004 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1005 } 1006 gfe_intr(sc); 1007 splx(s); 1008 1009 GE_FUNC_EXIT(sc, ""); 1010 } 1011 1012 int 1013 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1014 { 1015 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1016 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1017 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1018 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1019 uint32_t intrmask = sc->sc_intrmask; 1020 size_t buflen; 1021 struct mbuf *m; 1022 1023 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1024 1025 /* 1026 * Anything in the pending queue to enqueue? if not, punt. Likewise 1027 * if the txq is not yet created. 1028 * otherwise grab its dmamap. 1029 */ 1030 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1031 GE_FUNC_EXIT(sc, "-"); 1032 return 0; 1033 } 1034 1035 /* 1036 * Have we [over]consumed our limit of descriptors? 1037 * Do we have enough free descriptors? 1038 */ 1039 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1040 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1041 uint32_t cmdsts; 1042 size_t pktlen; 1043 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1044 cmdsts = gt32toh(txd2->ed_cmdsts); 1045 if (cmdsts & TX_CMD_O) { 1046 int nextin; 1047 /* 1048 * Sometime the Discovery forgets to update the 1049 * last descriptor. See if we own the descriptor 1050 * after it (since we know we've turned that to 1051 * the discovery and if we owned it, the Discovery 1052 * gave it back). If we do, we know the Discovery 1053 * gave back this one but forgot to mark it as ours. 1054 */ 1055 nextin = txq->txq_fi + 1; 1056 if (nextin == GE_TXDESC_MAX) 1057 nextin = 0; 1058 GE_TXDPOSTSYNC(sc, txq, nextin); 1059 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1060 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1061 GE_TXDPRESYNC(sc, txq, nextin); 1062 GE_FUNC_EXIT(sc, "@"); 1063 return 0; 1064 } 1065 #ifdef DEBUG 1066 printf("%s: txenqueue: transmitter resynced at %d\n", 1067 sc->sc_dev.dv_xname, txq->txq_fi); 1068 #endif 1069 } 1070 if (++txq->txq_fi == GE_TXDESC_MAX) 1071 txq->txq_fi = 0; 1072 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1073 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1074 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1075 txq->txq_nactive--; 1076 1077 /* statistics */ 1078 ifp->if_opackets++; 1079 if (cmdsts & TX_STS_ES) 1080 ifp->if_oerrors++; 1081 GE_DPRINTF(sc, ("%%")); 1082 } 1083 1084 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1085 1086 /* 1087 * If this packet would wrap around the end of the buffer, reset back 1088 * to the beginning. 1089 */ 1090 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1091 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1092 txq->txq_outptr = 0; 1093 } 1094 1095 /* 1096 * Make sure the output packet doesn't run over the beginning of 1097 * what we've already given the GT. 1098 */ 1099 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1100 txq->txq_outptr + buflen > txq->txq_inptr) { 1101 intrmask |= txq->txq_intrbits & 1102 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1103 if (sc->sc_intrmask != intrmask) { 1104 sc->sc_intrmask = intrmask; 1105 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1106 } 1107 GE_FUNC_EXIT(sc, "#"); 1108 return 0; 1109 } 1110 1111 /* 1112 * The end-of-list descriptor we put on last time is the starting point 1113 * for this packet. The GT is supposed to terminate list processing on 1114 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1115 * must terminate the list. 1116 */ 1117 intrmask = sc->sc_intrmask; 1118 1119 m_copydata(m, 0, m->m_pkthdr.len, 1120 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1121 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1122 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1123 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1124 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1125 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1126 1127 /* 1128 * Request a buffer interrupt every 2/3 of the way thru the transmit 1129 * buffer. 1130 */ 1131 txq->txq_ei_gapcount += buflen; 1132 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1133 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1134 txq->txq_ei_gapcount = 0; 1135 } else { 1136 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1137 } 1138 #if 0 1139 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1140 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1141 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1142 #endif 1143 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1144 1145 txq->txq_outptr += buflen; 1146 /* 1147 * Tell the SDMA engine to "Fetch!" 1148 */ 1149 GE_WRITE(sc, ESDCMR, 1150 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1151 1152 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1153 1154 /* 1155 * Update the last out appropriately. 1156 */ 1157 txq->txq_nactive++; 1158 if (++txq->txq_lo == GE_TXDESC_MAX) 1159 txq->txq_lo = 0; 1160 1161 /* 1162 * Move mbuf from the pending queue to the snd queue. 1163 */ 1164 IF_DEQUEUE(&txq->txq_pendq, m); 1165 #if NBPFILTER > 0 1166 if (ifp->if_bpf != NULL) 1167 bpf_mtap(ifp->if_bpf, m); 1168 #endif 1169 m_freem(m); 1170 ifp->if_flags &= ~IFF_OACTIVE; 1171 1172 /* 1173 * Since we have put an item into the packet queue, we now want 1174 * an interrupt when the transmit queue finishes processing the 1175 * list. But only update the mask if needs changing. 1176 */ 1177 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1178 if (sc->sc_intrmask != intrmask) { 1179 sc->sc_intrmask = intrmask; 1180 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1181 } 1182 if (ifp->if_timer == 0) 1183 ifp->if_timer = 5; 1184 GE_FUNC_EXIT(sc, "*"); 1185 return 1; 1186 } 1187 1188 uint32_t 1189 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1190 { 1191 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1192 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1193 1194 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1195 1196 if (txq == NULL) { 1197 GE_FUNC_EXIT(sc, ""); 1198 return intrmask; 1199 } 1200 1201 while (txq->txq_nactive > 0) { 1202 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1203 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1204 uint32_t cmdsts; 1205 size_t pktlen; 1206 1207 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1208 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1209 int nextin; 1210 1211 if (txq->txq_nactive == 1) { 1212 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1213 GE_FUNC_EXIT(sc, ""); 1214 return intrmask; 1215 } 1216 /* 1217 * Sometimes the Discovery forgets to update the 1218 * ownership bit in the descriptor. See if we own the 1219 * descriptor after it (since we know we've turned 1220 * that to the Discovery and if we own it now then the 1221 * Discovery gave it back). If we do, we know the 1222 * Discovery gave back this one but forgot to mark it 1223 * as ours. 1224 */ 1225 nextin = txq->txq_fi + 1; 1226 if (nextin == GE_TXDESC_MAX) 1227 nextin = 0; 1228 GE_TXDPOSTSYNC(sc, txq, nextin); 1229 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1230 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1231 GE_TXDPRESYNC(sc, txq, nextin); 1232 GE_FUNC_EXIT(sc, ""); 1233 return intrmask; 1234 } 1235 #ifdef DEBUG 1236 printf("%s: txdone: transmitter resynced at %d\n", 1237 sc->sc_dev.dv_xname, txq->txq_fi); 1238 #endif 1239 } 1240 #if 0 1241 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1242 txq->txq_lo, 1243 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1244 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1245 #endif 1246 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1247 if (++txq->txq_fi == GE_TXDESC_MAX) 1248 txq->txq_fi = 0; 1249 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1250 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1251 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1252 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1253 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1254 1255 /* statistics */ 1256 ifp->if_opackets++; 1257 if (cmdsts & TX_STS_ES) 1258 ifp->if_oerrors++; 1259 1260 /* txd->ed_bufptr = 0; */ 1261 1262 ifp->if_timer = 5; 1263 --txq->txq_nactive; 1264 } 1265 if (txq->txq_nactive != 0) 1266 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1267 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1268 ifp->if_timer = 0; 1269 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1270 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1271 GE_FUNC_EXIT(sc, ""); 1272 return intrmask; 1273 } 1274 1275 int 1276 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1277 { 1278 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1279 int error; 1280 1281 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1282 1283 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1284 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1285 if (error) { 1286 GE_FUNC_EXIT(sc, ""); 1287 return error; 1288 } 1289 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1290 if (error) { 1291 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1292 GE_FUNC_EXIT(sc, ""); 1293 return error; 1294 } 1295 GE_FUNC_EXIT(sc, ""); 1296 return 0; 1297 } 1298 1299 int 1300 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1301 { 1302 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1303 volatile struct gt_eth_desc *txd; 1304 unsigned int i; 1305 bus_addr_t addr; 1306 1307 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1308 1309 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1310 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1311 1312 if (sc->sc_flags & GE_NOFREE) { 1313 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1314 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1315 } else { 1316 int error = gfe_tx_txqalloc(sc, txprio); 1317 if (error) { 1318 GE_FUNC_EXIT(sc, "!"); 1319 return error; 1320 } 1321 } 1322 1323 txq->txq_descs = 1324 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1325 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1326 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1327 1328 txq->txq_pendq.ifq_maxlen = 10; 1329 txq->txq_ei_gapcount = 0; 1330 txq->txq_nactive = 0; 1331 txq->txq_fi = 0; 1332 txq->txq_lo = 0; 1333 txq->txq_inptr = GE_TXBUF_SIZE; 1334 txq->txq_outptr = 0; 1335 for (i = 0, txd = txq->txq_descs, 1336 addr = txq->txq_desc_busaddr + sizeof(*txd); 1337 i < GE_TXDESC_MAX - 1; 1338 i++, txd++, addr += sizeof(*txd)) { 1339 /* 1340 * update the nxtptr to point to the next txd. 1341 */ 1342 txd->ed_cmdsts = 0; 1343 txd->ed_nxtptr = htogt32(addr); 1344 } 1345 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1346 htogt32(txq->txq_desc_busaddr); 1347 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1348 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1349 1350 switch (txprio) { 1351 case GE_TXPRIO_HI: 1352 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1353 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1354 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1355 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1356 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1357 break; 1358 1359 case GE_TXPRIO_LO: 1360 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1361 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1362 txq->txq_epsrbits = ETH_EPSR_TxLow; 1363 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1364 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1365 break; 1366 1367 case GE_TXPRIO_NONE: 1368 break; 1369 } 1370 #if 0 1371 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1372 gt_write(device_parent(&sc->sc_dev), txq->txq_ectdp, 1373 txq->txq_desc_busaddr); 1374 GE_DPRINTF(sc, (")")); 1375 #endif 1376 1377 /* 1378 * If we are restarting, there may be packets in the pending queue 1379 * waiting to be enqueued. Try enqueuing packets from both priority 1380 * queues until the pending queue is empty or there no room for them 1381 * on the device. 1382 */ 1383 while (gfe_tx_enqueue(sc, txprio)) 1384 continue; 1385 1386 GE_FUNC_EXIT(sc, ""); 1387 return 0; 1388 } 1389 1390 void 1391 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1392 { 1393 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1394 1395 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1396 if (txq == NULL) { 1397 GE_FUNC_EXIT(sc, ""); 1398 return; 1399 } 1400 1401 if (!flush) { 1402 GE_FUNC_EXIT(sc, ""); 1403 return; 1404 } 1405 1406 if ((sc->sc_flags & GE_NOFREE) == 0) { 1407 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1408 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1409 } 1410 GE_FUNC_EXIT(sc, "-F"); 1411 } 1412 1413 void 1414 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1415 { 1416 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1417 1418 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1419 1420 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1421 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1422 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1423 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1424 1425 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1426 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1427 1428 sc->sc_ec.ec_if.if_timer = 0; 1429 GE_FUNC_EXIT(sc, ""); 1430 } 1431 1432 int 1433 gfe_intr(void *arg) 1434 { 1435 struct gfe_softc * const sc = arg; 1436 uint32_t cause; 1437 uint32_t intrmask = sc->sc_intrmask; 1438 int claim = 0; 1439 int cnt; 1440 1441 GE_FUNC_ENTER(sc, "gfe_intr"); 1442 1443 for (cnt = 0; cnt < 4; cnt++) { 1444 if (sc->sc_intrmask != intrmask) { 1445 sc->sc_intrmask = intrmask; 1446 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1447 } 1448 cause = GE_READ(sc, EICR); 1449 cause &= sc->sc_intrmask; 1450 GE_DPRINTF(sc, (".%#x", cause)); 1451 if (cause == 0) 1452 break; 1453 1454 claim = 1; 1455 1456 GE_WRITE(sc, EICR, ~cause); 1457 #ifndef GE_NORX 1458 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1459 intrmask = gfe_rx_process(sc, cause, intrmask); 1460 #endif 1461 1462 #ifndef GE_NOTX 1463 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1464 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1465 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1466 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1467 #endif 1468 if (cause & ETH_IR_MIIPhySTC) { 1469 sc->sc_flags |= GE_PHYSTSCHG; 1470 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1471 } 1472 } 1473 1474 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1475 continue; 1476 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1477 continue; 1478 1479 GE_FUNC_EXIT(sc, ""); 1480 return claim; 1481 } 1482 1483 int 1484 gfe_mii_mediachange (struct ifnet *ifp) 1485 { 1486 struct gfe_softc *sc = ifp->if_softc; 1487 1488 if (ifp->if_flags & IFF_UP) 1489 mii_mediachg(&sc->sc_mii); 1490 1491 return (0); 1492 } 1493 void 1494 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1495 { 1496 struct gfe_softc *sc = ifp->if_softc; 1497 1498 if (sc->sc_flags & GE_PHYSTSCHG) { 1499 sc->sc_flags &= ~GE_PHYSTSCHG; 1500 mii_pollstat(&sc->sc_mii); 1501 } 1502 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1503 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1504 } 1505 1506 int 1507 gfe_mii_read (struct device *self, int phy, int reg) 1508 { 1509 return gt_mii_read(self, device_parent(self), phy, reg); 1510 } 1511 1512 void 1513 gfe_mii_write (struct device *self, int phy, int reg, int value) 1514 { 1515 gt_mii_write(self, device_parent(self), phy, reg, value); 1516 } 1517 1518 void 1519 gfe_mii_statchg (struct device *self) 1520 { 1521 /* struct gfe_softc *sc = device_private(self); */ 1522 /* do nothing? */ 1523 } 1524 1525 int 1526 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1527 { 1528 int error = 0; 1529 GE_FUNC_ENTER(sc, "gfe_whack"); 1530 1531 switch (op) { 1532 case GE_WHACK_RESTART: 1533 #ifndef GE_NOTX 1534 gfe_tx_stop(sc, op); 1535 #endif 1536 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1537 /* FALLTHROUGH */ 1538 case GE_WHACK_START: 1539 #ifndef GE_NOHASH 1540 if (error == 0 && sc->sc_hashtable == NULL) { 1541 error = gfe_hash_alloc(sc); 1542 if (error) 1543 break; 1544 } 1545 if (op != GE_WHACK_RESTART) 1546 gfe_hash_fill(sc); 1547 #endif 1548 #ifndef GE_NORX 1549 if (op != GE_WHACK_RESTART) { 1550 error = gfe_rx_prime(sc); 1551 if (error) 1552 break; 1553 } 1554 #endif 1555 #ifndef GE_NOTX 1556 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1557 if (error) 1558 break; 1559 #endif 1560 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1561 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1562 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1563 GE_WRITE(sc, EICR, 0); 1564 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1565 #ifndef GE_NOHASH 1566 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1567 #endif 1568 #ifndef GE_NORX 1569 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1570 sc->sc_flags |= GE_RXACTIVE; 1571 #endif 1572 /* FALLTHROUGH */ 1573 case GE_WHACK_CHANGE: 1574 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1575 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1576 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1577 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1578 gfe_ifstart(&sc->sc_ec.ec_if); 1579 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1580 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1581 GE_FUNC_EXIT(sc, ""); 1582 return error; 1583 case GE_WHACK_STOP: 1584 break; 1585 } 1586 1587 #ifdef GE_DEBUG 1588 if (error) 1589 GE_DPRINTF(sc, (" failed: %d\n", error)); 1590 #endif 1591 GE_WRITE(sc, EPCR, sc->sc_pcr); 1592 GE_WRITE(sc, EIMR, 0); 1593 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1594 #ifndef GE_NOTX 1595 gfe_tx_stop(sc, GE_WHACK_STOP); 1596 #endif 1597 #ifndef GE_NORX 1598 gfe_rx_stop(sc, GE_WHACK_STOP); 1599 #endif 1600 #ifndef GE_NOHASH 1601 if ((sc->sc_flags & GE_NOFREE) == 0) { 1602 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1603 sc->sc_hashtable = NULL; 1604 } 1605 #endif 1606 1607 GE_FUNC_EXIT(sc, ""); 1608 return error; 1609 } 1610 1611 int 1612 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1613 { 1614 uint32_t w0, add0, add1; 1615 uint32_t result; 1616 1617 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1618 add0 = ((uint32_t) eaddr[5] << 0) | 1619 ((uint32_t) eaddr[4] << 8) | 1620 ((uint32_t) eaddr[3] << 16); 1621 1622 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1623 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1624 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1625 1626 add1 = ((uint32_t) eaddr[2] << 0) | 1627 ((uint32_t) eaddr[1] << 8) | 1628 ((uint32_t) eaddr[0] << 16); 1629 1630 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1631 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1632 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1633 1634 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1635 /* 1636 * hashResult is the 15 bits Hash entry address. 1637 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1638 * MAC address, by nibble swapping in every byte (i.e MAC address 1639 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1640 */ 1641 1642 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1643 /* 1644 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1645 * 1646 * hashFunc0 calculates the hashResult in the following manner: 1647 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1648 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1649 */ 1650 result = (add0 & 3) | ((add0 >> 6) & ~3); 1651 result ^= (add0 >> 15) ^ (add1 >> 0); 1652 result &= 0x1ff; 1653 /* 1654 * hashResult[14:9] = ethernetADD[7:2] 1655 */ 1656 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1657 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1658 } else { 1659 #define TRIBITFLIP 073516240 /* yes its in octal */ 1660 /* 1661 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1662 * 1663 * hashFunc1 calculates the hashResult in the following manner: 1664 * hashResult[08:00] = ethernetADD[06:14] 1665 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1666 */ 1667 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1668 /* 1669 * Now bitswap those 9 bits 1670 */ 1671 result = 0; 1672 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1673 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1674 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1675 1676 /* 1677 * hashResult[14:09] = ethernetADD[00:05] 1678 */ 1679 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1680 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1681 GE_DPRINTF(sc, ("1(%#x)", result)); 1682 } 1683 GE_FUNC_EXIT(sc, ""); 1684 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1685 } 1686 1687 int 1688 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1689 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1690 { 1691 uint64_t he; 1692 uint64_t *maybe_he_p = NULL; 1693 int limit; 1694 int hash; 1695 int maybe_hash = 0; 1696 1697 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1698 1699 hash = gfe_hash_compute(sc, eaddr); 1700 1701 if (sc->sc_hashtable == NULL) { 1702 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1703 __LINE__); 1704 } 1705 1706 /* 1707 * Assume we are going to insert so create the hash entry we 1708 * are going to insert. We also use it to match entries we 1709 * will be removing. 1710 */ 1711 he = ((uint64_t) eaddr[5] << 43) | 1712 ((uint64_t) eaddr[4] << 35) | 1713 ((uint64_t) eaddr[3] << 27) | 1714 ((uint64_t) eaddr[2] << 19) | 1715 ((uint64_t) eaddr[1] << 11) | 1716 ((uint64_t) eaddr[0] << 3) | 1717 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1718 1719 /* 1720 * The GT will search upto 12 entries for a hit, so we must mimic that. 1721 */ 1722 hash &= sc->sc_hashmask / sizeof(he); 1723 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1724 /* 1725 * Does the GT wrap at the end, stop at the, or overrun the 1726 * end? Assume it wraps for now. Stash a copy of the 1727 * current hash entry. 1728 */ 1729 uint64_t *he_p = &sc->sc_hashtable[hash]; 1730 uint64_t thishe = *he_p; 1731 1732 /* 1733 * If the hash entry isn't valid, that break the chain. And 1734 * this entry a good candidate for reuse. 1735 */ 1736 if ((thishe & HSH_V) == 0) { 1737 maybe_he_p = he_p; 1738 break; 1739 } 1740 1741 /* 1742 * If the hash entry has the same address we are looking for 1743 * then ... if we are removing and the skip bit is set, its 1744 * already been removed. if are adding and the skip bit is 1745 * clear, then its already added. In either return EBUSY 1746 * indicating the op has already been done. Otherwise flip 1747 * the skip bit and return 0. 1748 */ 1749 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1750 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1751 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1752 return EBUSY; 1753 *he_p = thishe ^ HSH_S; 1754 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1755 hash * sizeof(he), sizeof(he), 1756 BUS_DMASYNC_PREWRITE); 1757 GE_FUNC_EXIT(sc, "^"); 1758 return 0; 1759 } 1760 1761 /* 1762 * If we haven't found a slot for the entry and this entry 1763 * is currently being skipped, return this entry. 1764 */ 1765 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1766 maybe_he_p = he_p; 1767 maybe_hash = hash; 1768 } 1769 1770 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1771 } 1772 1773 /* 1774 * If we got here, then there was no entry to remove. 1775 */ 1776 if (op == GE_HASH_REMOVE) { 1777 GE_FUNC_EXIT(sc, "?"); 1778 return ENOENT; 1779 } 1780 1781 /* 1782 * If we couldn't find a slot, return an error. 1783 */ 1784 if (maybe_he_p == NULL) { 1785 GE_FUNC_EXIT(sc, "!"); 1786 return ENOSPC; 1787 } 1788 1789 /* Update the entry. 1790 */ 1791 *maybe_he_p = he; 1792 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1793 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1794 GE_FUNC_EXIT(sc, "+"); 1795 return 0; 1796 } 1797 1798 int 1799 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1800 { 1801 struct gfe_softc * const sc = ec->ec_if.if_softc; 1802 int error; 1803 enum gfe_hash_op op; 1804 enum gfe_rxprio prio; 1805 1806 GE_FUNC_ENTER(sc, "hash_multichg"); 1807 /* 1808 * Is this a wildcard entry? If so and its being removed, recompute. 1809 */ 1810 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1811 if (cmd == SIOCDELMULTI) { 1812 GE_FUNC_EXIT(sc, ""); 1813 return ENETRESET; 1814 } 1815 1816 /* 1817 * Switch in 1818 */ 1819 sc->sc_flags |= GE_ALLMULTI; 1820 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1821 sc->sc_pcr |= ETH_EPCR_PM; 1822 GE_WRITE(sc, EPCR, sc->sc_pcr); 1823 GE_FUNC_EXIT(sc, ""); 1824 return 0; 1825 } 1826 GE_FUNC_EXIT(sc, ""); 1827 return ENETRESET; 1828 } 1829 1830 prio = GE_RXPRIO_MEDLO; 1831 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1832 1833 if (sc->sc_hashtable == NULL) { 1834 GE_FUNC_EXIT(sc, ""); 1835 return 0; 1836 } 1837 1838 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1839 if (error == EBUSY) { 1840 printf("%s: multichg: tried to %s %s again\n", 1841 sc->sc_dev.dv_xname, 1842 cmd == SIOCDELMULTI ? "remove" : "add", 1843 ether_sprintf(enm->enm_addrlo)); 1844 GE_FUNC_EXIT(sc, ""); 1845 return 0; 1846 } 1847 1848 if (error == ENOENT) { 1849 printf("%s: multichg: failed to remove %s: not in table\n", 1850 sc->sc_dev.dv_xname, 1851 ether_sprintf(enm->enm_addrlo)); 1852 GE_FUNC_EXIT(sc, ""); 1853 return 0; 1854 } 1855 1856 if (error == ENOSPC) { 1857 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1858 sc->sc_dev.dv_xname, 1859 ether_sprintf(enm->enm_addrlo)); 1860 GE_FUNC_EXIT(sc, ""); 1861 return ENETRESET; 1862 } 1863 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1864 sc->sc_dev.dv_xname, 1865 cmd == SIOCDELMULTI ? "remove" : "add", 1866 ether_sprintf(enm->enm_addrlo))); 1867 GE_FUNC_EXIT(sc, ""); 1868 return 0; 1869 } 1870 1871 int 1872 gfe_hash_fill(struct gfe_softc *sc) 1873 { 1874 struct ether_multistep step; 1875 struct ether_multi *enm; 1876 int error; 1877 1878 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1879 1880 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1881 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 1882 if (error) 1883 GE_FUNC_EXIT(sc, "!"); 1884 return error; 1885 1886 sc->sc_flags &= ~GE_ALLMULTI; 1887 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1888 sc->sc_pcr &= ~ETH_EPCR_PM; 1889 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1890 while (enm != NULL) { 1891 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1892 sc->sc_flags |= GE_ALLMULTI; 1893 sc->sc_pcr |= ETH_EPCR_PM; 1894 } else { 1895 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1896 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1897 if (error == ENOSPC) 1898 break; 1899 } 1900 ETHER_NEXT_MULTI(step, enm); 1901 } 1902 1903 GE_FUNC_EXIT(sc, ""); 1904 return error; 1905 } 1906 1907 int 1908 gfe_hash_alloc(struct gfe_softc *sc) 1909 { 1910 int error; 1911 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1912 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1913 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1914 BUS_DMA_NOCACHE); 1915 if (error) { 1916 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1917 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1918 GE_FUNC_EXIT(sc, ""); 1919 return error; 1920 } 1921 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1922 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1923 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1924 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1925 GE_FUNC_EXIT(sc, ""); 1926 return 0; 1927 } 1928