1 /* $NetBSD: if_gfe.c,v 1.58 2021/04/24 23:36:56 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.58 2021/04/24 23:36:56 thorpej Exp $"); 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/bus.h> 51 #include <sys/callout.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/ioctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/mutex.h> 57 #include <sys/socket.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_ether.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/if_inarp.h> 67 #endif 68 #include <net/bpf.h> 69 #include <sys/rndsource.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/marvell/gtreg.h> 75 #include <dev/marvell/gtvar.h> 76 #include <dev/marvell/gtethreg.h> 77 #include <dev/marvell/if_gfevar.h> 78 #include <dev/marvell/marvellreg.h> 79 #include <dev/marvell/marvellvar.h> 80 81 #include <prop/proplib.h> 82 83 #include "locators.h" 84 85 86 #define GE_READ(sc, reg) \ 87 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)) 88 #define GE_WRITE(sc, reg, v) \ 89 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (v)) 90 91 #define GE_DEBUG 92 #if 0 93 #define GE_NOHASH 94 #define GE_NORX 95 #endif 96 97 #ifdef GE_DEBUG 98 #define GE_DPRINTF(sc, a) \ 99 do { \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 } while (0 /* CONSTCOND */) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 148 STATIC int gfec_match(device_t, cfdata_t, void *); 149 STATIC void gfec_attach(device_t, device_t, void *); 150 151 STATIC int gfec_print(void *, const char *); 152 STATIC int gfec_search(device_t, cfdata_t, const int *, void *); 153 154 STATIC int gfec_enet_phy(device_t, int); 155 STATIC int gfec_mii_read(device_t, int, int, uint16_t *); 156 STATIC int gfec_mii_write(device_t, int, int, uint16_t); 157 STATIC void gfec_mii_statchg(struct ifnet *); 158 159 STATIC int gfe_match(device_t, cfdata_t, void *); 160 STATIC void gfe_attach(device_t, device_t, void *); 161 162 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 163 size_t, int); 164 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 165 166 STATIC int gfe_ifioctl(struct ifnet *, u_long, void *); 167 STATIC void gfe_ifstart(struct ifnet *); 168 STATIC void gfe_ifwatchdog(struct ifnet *); 169 170 STATIC void gfe_tick(void *arg); 171 172 STATIC void gfe_tx_restart(void *); 173 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 174 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 175 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 176 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 177 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 178 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 179 180 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 181 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 182 STATIC int gfe_rx_prime(struct gfe_softc *); 183 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 184 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 185 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 186 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 187 188 STATIC int gfe_intr(void *); 189 190 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 191 192 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 193 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 194 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 195 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 196 u_long); 197 STATIC int gfe_hash_fill(struct gfe_softc *); 198 STATIC int gfe_hash_alloc(struct gfe_softc *); 199 200 201 CFATTACH_DECL_NEW(gfec, sizeof(struct gfec_softc), 202 gfec_match, gfec_attach, NULL, NULL); 203 CFATTACH_DECL_NEW(gfe, sizeof(struct gfe_softc), 204 gfe_match, gfe_attach, NULL, NULL); 205 206 207 /* ARGSUSED */ 208 int 209 gfec_match(device_t parent, cfdata_t cf, void *aux) 210 { 211 struct marvell_attach_args *mva = aux; 212 213 if (strcmp(mva->mva_name, cf->cf_name) != 0) 214 return 0; 215 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 216 return 0; 217 218 mva->mva_size = ETHC_SIZE; 219 return 1; 220 } 221 222 /* ARGSUSED */ 223 void 224 gfec_attach(device_t parent, device_t self, void *aux) 225 { 226 struct gfec_softc *sc = device_private(self); 227 struct marvell_attach_args *mva = aux, gfea; 228 static int gfe_irqs[] = { 32, 33, 34 }; 229 int i; 230 231 aprint_naive("\n"); 232 aprint_normal(": Ethernet Controller\n"); 233 234 sc->sc_dev = self; 235 sc->sc_iot = mva->mva_iot; 236 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 237 mva->mva_size, &sc->sc_ioh)) { 238 aprint_error_dev(self, "Cannot map registers\n"); 239 return; 240 } 241 242 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 243 244 for (i = 0; i < ETH_NUM; i++) { 245 gfea.mva_name = "gfe"; 246 gfea.mva_model = mva->mva_model; 247 gfea.mva_iot = sc->sc_iot; 248 gfea.mva_ioh = sc->sc_ioh; 249 gfea.mva_unit = i; 250 gfea.mva_dmat = mva->mva_dmat; 251 gfea.mva_irq = gfe_irqs[i]; 252 config_found(sc->sc_dev, &gfea, gfec_print, 253 CFARG_SUBMATCH, gfec_search, 254 CFARG_EOL); 255 } 256 } 257 258 int 259 gfec_print(void *aux, const char *pnp) 260 { 261 struct marvell_attach_args *gfea = aux; 262 263 if (pnp) 264 aprint_normal("%s at %s port %d", 265 gfea->mva_name, pnp, gfea->mva_unit); 266 else { 267 if (gfea->mva_unit != GFECCF_PORT_DEFAULT) 268 aprint_normal(" port %d", gfea->mva_unit); 269 if (gfea->mva_irq != GFECCF_IRQ_DEFAULT) 270 aprint_normal(" irq %d", gfea->mva_irq); 271 } 272 return UNCONF; 273 } 274 275 /* ARGSUSED */ 276 int 277 gfec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 278 { 279 struct marvell_attach_args *gfea = aux; 280 281 if (cf->cf_loc[GFECCF_PORT] == gfea->mva_unit && 282 cf->cf_loc[GFECCF_IRQ] != GFECCF_IRQ_DEFAULT) 283 gfea->mva_irq = cf->cf_loc[GFECCF_IRQ]; 284 285 return config_match(parent, cf, aux); 286 } 287 288 int 289 gfec_enet_phy(device_t dev, int unit) 290 { 291 struct gfec_softc *sc = device_private(dev); 292 uint32_t epar; 293 294 epar = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ETH_EPAR); 295 return ETH_EPAR_PhyAD_GET(epar, unit); 296 } 297 298 int 299 gfec_mii_read(device_t dev, int phy, int reg, uint16_t *val) 300 { 301 struct gfec_softc *csc = device_private(device_parent(dev)); 302 uint32_t data; 303 int count = 10000; 304 305 mutex_enter(&csc->sc_mtx); 306 307 do { 308 DELAY(10); 309 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 310 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 311 312 if (count == 0) { 313 aprint_error_dev(dev, 314 "mii read for phy %d reg %d busied out\n", phy, reg); 315 mutex_exit(&csc->sc_mtx); 316 return ETIMEDOUT; 317 } 318 319 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 320 ETH_ESMIR_READ(phy, reg)); 321 322 count = 10000; 323 do { 324 DELAY(10); 325 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 326 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 327 328 mutex_exit(&csc->sc_mtx); 329 330 if (count == 0) { 331 aprint_error_dev(dev, 332 "mii read for phy %d reg %d timed out\n", phy, reg); 333 return ETIMEDOUT; 334 } 335 #if defined(GTMIIDEBUG) 336 aprint_normal_dev(dev, "mii_read(%d, %d): %#x data %#x\n", 337 phy, reg, data, ETH_ESMIR_Value_GET(data)); 338 #endif 339 *val = ETH_ESMIR_Value_GET(data); 340 return 0; 341 } 342 343 int 344 gfec_mii_write(device_t dev, int phy, int reg, uint16_t value) 345 { 346 struct gfec_softc *csc = device_private(device_parent(dev)); 347 uint32_t data; 348 int count = 10000; 349 350 mutex_enter(&csc->sc_mtx); 351 352 do { 353 DELAY(10); 354 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 355 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 356 357 if (count == 0) { 358 aprint_error_dev(dev, 359 "mii write for phy %d reg %d busied out (busy)\n", 360 phy, reg); 361 mutex_exit(&csc->sc_mtx); 362 return ETIMEDOUT; 363 } 364 365 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 366 ETH_ESMIR_WRITE(phy, reg, value)); 367 368 count = 10000; 369 do { 370 DELAY(10); 371 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 372 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 373 374 mutex_exit(&csc->sc_mtx); 375 376 if (count == 0) { 377 aprint_error_dev(dev, 378 "mii write for phy %d reg %d timed out\n", phy, reg); 379 return ETIMEDOUT; 380 } 381 #if defined(GTMIIDEBUG) 382 aprint_normal_dev(dev, "mii_write(%d, %d, %#hx)\n", phy, reg, value); 383 #endif 384 return 0; 385 } 386 387 void 388 gfec_mii_statchg(struct ifnet *ifp) 389 { 390 /* struct gfe_softc *sc = ifp->if_softc; */ 391 /* do nothing? */ 392 } 393 394 /* ARGSUSED */ 395 int 396 gfe_match(device_t parent, cfdata_t cf, void *aux) 397 { 398 399 return 1; 400 } 401 402 /* ARGSUSED */ 403 void 404 gfe_attach(device_t parent, device_t self, void *aux) 405 { 406 struct marvell_attach_args *mva = aux; 407 struct gfe_softc * const sc = device_private(self); 408 struct ifnet * const ifp = &sc->sc_ec.ec_if; 409 struct mii_data * const mii = &sc->sc_mii; 410 uint32_t sdcr; 411 int phyaddr, error; 412 prop_data_t ea; 413 uint8_t enaddr[6]; 414 415 aprint_naive("\n"); 416 aprint_normal(": Ethernet Controller\n"); 417 418 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 419 mva->mva_offset, mva->mva_size, &sc->sc_memh)) { 420 aprint_error_dev(self, "failed to map registers\n"); 421 return; 422 } 423 sc->sc_dev = self; 424 sc->sc_memt = mva->mva_iot; 425 sc->sc_dmat = mva->mva_dmat; 426 sc->sc_macno = (mva->mva_offset == ETH_BASE(0)) ? 0 : 427 ((mva->mva_offset == ETH_BASE(1)) ? 1 : 2); 428 429 callout_init(&sc->sc_co, 0); 430 431 phyaddr = gfec_enet_phy(parent, sc->sc_macno); 432 433 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-addr"); 434 if (ea != NULL) { 435 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 436 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 437 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 438 } 439 440 sc->sc_pcr = GE_READ(sc, ETH_EPCR); 441 sc->sc_pcxr = GE_READ(sc, ETH_EPCXR); 442 sc->sc_intrmask = GE_READ(sc, ETH_EIMR) | ETH_IR_MIIPhySTC; 443 444 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 445 446 #if defined(DEBUG) 447 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 448 #endif 449 450 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 451 if (device_cfdata(self)->cf_flags & 1) { 452 aprint_normal_dev(self, "phy %d (rmii)\n", phyaddr); 453 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 454 } else { 455 aprint_normal_dev(self, "phy %d (mii)\n", phyaddr); 456 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 457 } 458 if (device_cfdata(self)->cf_flags & 2) 459 sc->sc_flags |= GE_NOFREE; 460 /* Set Max Frame Length is 1536 */ 461 sc->sc_pcxr &= ~ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_MASK); 462 sc->sc_pcxr |= ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_1536); 463 sc->sc_max_frame_length = 1536; 464 465 if (sc->sc_pcr & ETH_EPCR_EN) { 466 int tries = 1000; 467 /* 468 * Abort transmitter and receiver and wait for them to quiese 469 */ 470 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR | ETH_ESDCMR_AT); 471 do { 472 delay(100); 473 if (tries-- <= 0) { 474 aprint_error_dev(self, "Abort TX/RX failed\n"); 475 break; 476 } 477 } while (GE_READ(sc, ETH_ESDCMR) & 478 (ETH_ESDCMR_AR | ETH_ESDCMR_AT)); 479 } 480 481 sc->sc_pcr &= 482 ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 483 484 #if defined(DEBUG) 485 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 486 #endif 487 488 /* 489 * Now turn off the GT. If it didn't quiese, too ***ing bad. 490 */ 491 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 492 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 493 sdcr = GE_READ(sc, ETH_ESDCR); 494 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 495 sdcr |= ETH_ESDCR_RIFB; 496 GE_WRITE(sc, ETH_ESDCR, sdcr); 497 498 mii->mii_ifp = ifp; 499 mii->mii_readreg = gfec_mii_read; 500 mii->mii_writereg = gfec_mii_write; 501 mii->mii_statchg = gfec_mii_statchg; 502 503 sc->sc_ec.ec_mii = mii; 504 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 505 506 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 507 MII_OFFSET_ANY, MIIF_NOISOLATE); 508 if (LIST_FIRST(&mii->mii_phys) == NULL) { 509 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 510 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 511 } else 512 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 513 514 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 515 ifp->if_softc = sc; 516 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 517 #if 0 518 ifp->if_flags |= IFF_DEBUG; 519 #endif 520 ifp->if_ioctl = gfe_ifioctl; 521 ifp->if_start = gfe_ifstart; 522 ifp->if_watchdog = gfe_ifwatchdog; 523 524 if (sc->sc_flags & GE_NOFREE) { 525 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 526 if (!error) 527 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 528 if (!error) 529 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 530 if (!error) 531 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 532 if (!error) 533 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 534 if (!error) 535 error = gfe_hash_alloc(sc); 536 if (error) 537 aprint_error_dev(self, 538 "failed to allocate resources: %d\n", error); 539 } 540 541 if_attach(ifp); 542 ether_ifattach(ifp, enaddr); 543 bpf_attach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 544 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 545 RND_FLAG_DEFAULT); 546 marvell_intr_establish(mva->mva_irq, IPL_NET, gfe_intr, sc); 547 } 548 549 int 550 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 551 size_t size, int flags) 552 { 553 int error = 0; 554 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 555 556 KASSERT(gdm->gdm_kva == NULL); 557 gdm->gdm_size = size; 558 gdm->gdm_maxsegs = maxsegs; 559 560 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 561 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 562 BUS_DMA_NOWAIT); 563 if (error) 564 goto fail; 565 566 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 567 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 568 if (error) 569 goto fail; 570 571 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 572 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW |BUS_DMA_NOWAIT, &gdm->gdm_map); 573 if (error) 574 goto fail; 575 576 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 577 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 578 if (error) 579 goto fail; 580 581 /* invalidate from cache */ 582 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 583 BUS_DMASYNC_PREREAD); 584 fail: 585 if (error) { 586 gfe_dmamem_free(sc, gdm); 587 GE_DPRINTF(sc, (":err=%d", error)); 588 } 589 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 590 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 591 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 592 GE_FUNC_EXIT(sc, ""); 593 return error; 594 } 595 596 void 597 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 598 { 599 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 600 if (gdm->gdm_map) 601 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 602 if (gdm->gdm_kva) 603 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 604 if (gdm->gdm_nsegs > 0) 605 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 606 gdm->gdm_map = NULL; 607 gdm->gdm_kva = NULL; 608 gdm->gdm_nsegs = 0; 609 GE_FUNC_EXIT(sc, ""); 610 } 611 612 int 613 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 614 { 615 struct gfe_softc * const sc = ifp->if_softc; 616 struct ifreq *ifr = (struct ifreq *) data; 617 struct ifaddr *ifa = (struct ifaddr *) data; 618 int s, error = 0; 619 620 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 621 s = splnet(); 622 623 switch (cmd) { 624 case SIOCINITIFADDR: 625 ifp->if_flags |= IFF_UP; 626 error = gfe_whack(sc, GE_WHACK_START); 627 switch (ifa->ifa_addr->sa_family) { 628 #ifdef INET 629 case AF_INET: 630 if (error == 0) 631 arp_ifinit(ifp, ifa); 632 break; 633 #endif 634 default: 635 break; 636 } 637 break; 638 639 case SIOCSIFFLAGS: 640 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 641 break; 642 /* XXX re-use ether_ioctl() */ 643 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 644 case IFF_UP | IFF_RUNNING:/* active->active, update */ 645 error = gfe_whack(sc, GE_WHACK_CHANGE); 646 break; 647 case IFF_RUNNING: /* not up, so we stop */ 648 error = gfe_whack(sc, GE_WHACK_STOP); 649 break; 650 case IFF_UP: /* not running, so we start */ 651 error = gfe_whack(sc, GE_WHACK_START); 652 break; 653 case 0: /* idle->idle: do nothing */ 654 break; 655 } 656 break; 657 658 case SIOCSIFMTU: 659 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 660 error = EINVAL; 661 break; 662 } 663 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 664 error = 0; 665 break; 666 667 default: 668 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 669 if (ifp->if_flags & IFF_RUNNING) 670 error = gfe_whack(sc, GE_WHACK_CHANGE); 671 else 672 error = 0; 673 } 674 break; 675 } 676 splx(s); 677 GE_FUNC_EXIT(sc, ""); 678 return error; 679 } 680 681 void 682 gfe_ifstart(struct ifnet *ifp) 683 { 684 struct gfe_softc * const sc = ifp->if_softc; 685 struct mbuf *m; 686 687 GE_FUNC_ENTER(sc, "gfe_ifstart"); 688 689 if ((ifp->if_flags & IFF_RUNNING) == 0) { 690 GE_FUNC_EXIT(sc, "$"); 691 return; 692 } 693 694 for (;;) { 695 IF_DEQUEUE(&ifp->if_snd, m); 696 if (m == NULL) { 697 ifp->if_flags &= ~IFF_OACTIVE; 698 GE_FUNC_EXIT(sc, ""); 699 return; 700 } 701 702 /* 703 * No space in the pending queue? try later. 704 */ 705 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 706 break; 707 708 /* 709 * Try to enqueue a mbuf to the device. If that fails, we 710 * can always try to map the next mbuf. 711 */ 712 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 713 GE_DPRINTF(sc, (">")); 714 #ifndef GE_NOTX 715 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 716 #endif 717 } 718 719 /* 720 * Attempt to queue the mbuf for send failed. 721 */ 722 IF_PREPEND(&ifp->if_snd, m); 723 ifp->if_flags |= IFF_OACTIVE; 724 GE_FUNC_EXIT(sc, "%%"); 725 } 726 727 void 728 gfe_ifwatchdog(struct ifnet *ifp) 729 { 730 struct gfe_softc * const sc = ifp->if_softc; 731 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 732 733 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 734 aprint_error_dev(sc->sc_dev, "device timeout"); 735 if (ifp->if_flags & IFF_RUNNING) { 736 uint32_t curtxdnum; 737 738 curtxdnum = (GE_READ(sc, txq->txq_ectdp) - 739 txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 740 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 741 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 742 aprint_error(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 743 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 744 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 745 GE_READ(sc, ETH_EICR)); 746 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 747 GE_TXDPRESYNC(sc, txq, curtxdnum); 748 } 749 aprint_error("\n"); 750 if_statinc(ifp, if_oerrors); 751 (void) gfe_whack(sc, GE_WHACK_RESTART); 752 GE_FUNC_EXIT(sc, ""); 753 } 754 755 int 756 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 757 { 758 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 759 int error; 760 761 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 762 GE_DPRINTF(sc, ("(%d)", rxprio)); 763 764 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 765 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 766 if (error) { 767 GE_FUNC_EXIT(sc, "!!"); 768 return error; 769 } 770 771 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 772 GE_RXBUF_MEMSIZE, 0); 773 if (error) { 774 GE_FUNC_EXIT(sc, "!!!"); 775 return error; 776 } 777 GE_FUNC_EXIT(sc, ""); 778 return error; 779 } 780 781 int 782 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 783 { 784 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 785 volatile struct gt_eth_desc *rxd; 786 const bus_dma_segment_t *ds; 787 int idx; 788 bus_addr_t nxtaddr; 789 bus_size_t boff; 790 791 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 792 GE_DPRINTF(sc, ("(%d)", rxprio)); 793 794 if ((sc->sc_flags & GE_NOFREE) == 0) { 795 int error = gfe_rx_rxqalloc(sc, rxprio); 796 if (error) { 797 GE_FUNC_EXIT(sc, "!"); 798 return error; 799 } 800 } else { 801 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 802 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 803 } 804 805 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 806 807 rxq->rxq_descs = 808 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 809 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 810 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 811 rxq->rxq_fi = 0; 812 rxq->rxq_active = GE_RXDESC_MAX; 813 boff = 0; 814 ds = rxq->rxq_buf_mem.gdm_map->dm_segs; 815 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 816 for (idx = 0, rxd = rxq->rxq_descs; idx < GE_RXDESC_MAX; 817 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 818 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 819 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 820 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 821 /* 822 * update the nxtptr to point to the next txd. 823 */ 824 if (idx == GE_RXDESC_MAX - 1) 825 nxtaddr = rxq->rxq_desc_busaddr; 826 rxd->ed_nxtptr = htogt32(nxtaddr); 827 boff += GE_RXBUF_SIZE; 828 if (boff == ds->ds_len) { 829 ds++; 830 boff = 0; 831 } 832 } 833 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 834 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 835 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 836 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 837 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 838 BUS_DMASYNC_PREREAD); 839 840 rxq->rxq_intrbits = ETH_IR_RxBuffer | ETH_IR_RxError; 841 switch (rxprio) { 842 case GE_RXPRIO_HI: 843 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3 | ETH_IR_RxError_3; 844 rxq->rxq_efrdp = ETH_EFRDP3; 845 rxq->rxq_ecrdp = ETH_ECRDP3; 846 break; 847 case GE_RXPRIO_MEDHI: 848 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2 | ETH_IR_RxError_2; 849 rxq->rxq_efrdp = ETH_EFRDP2; 850 rxq->rxq_ecrdp = ETH_ECRDP2; 851 break; 852 case GE_RXPRIO_MEDLO: 853 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1 | ETH_IR_RxError_1; 854 rxq->rxq_efrdp = ETH_EFRDP1; 855 rxq->rxq_ecrdp = ETH_ECRDP1; 856 break; 857 case GE_RXPRIO_LO: 858 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0 | ETH_IR_RxError_0; 859 rxq->rxq_efrdp = ETH_EFRDP0; 860 rxq->rxq_ecrdp = ETH_ECRDP0; 861 break; 862 } 863 GE_FUNC_EXIT(sc, ""); 864 return 0; 865 } 866 867 void 868 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 869 { 870 struct ifnet * const ifp = &sc->sc_ec.ec_if; 871 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 872 struct mbuf *m = rxq->rxq_curpkt; 873 874 GE_FUNC_ENTER(sc, "gfe_rx_get"); 875 GE_DPRINTF(sc, ("(%d)", rxprio)); 876 877 while (rxq->rxq_active > 0) { 878 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 879 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 880 const struct ether_header *eh; 881 unsigned int cmdsts; 882 size_t buflen; 883 884 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 885 cmdsts = gt32toh(rxd->ed_cmdsts); 886 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 887 rxq->rxq_cmdsts = cmdsts; 888 /* 889 * Sometimes the GE "forgets" to reset the ownership bit. 890 * But if the length has been rewritten, the packet is ours 891 * so pretend the O bit is set. 892 */ 893 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 894 if ((cmdsts & RX_CMD_O) && buflen == 0) { 895 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 896 break; 897 } 898 899 /* 900 * If this is not a single buffer packet with no errors 901 * or for some reason it's bigger than our frame size, 902 * ignore it and go to the next packet. 903 */ 904 if ((cmdsts & (RX_CMD_F | RX_CMD_L | RX_STS_ES)) != 905 (RX_CMD_F | RX_CMD_L) || 906 (buflen > sc->sc_max_frame_length)) { 907 GE_DPRINTF(sc, ("!")); 908 --rxq->rxq_active; 909 if_statinc(ifp, if_ipackets); 910 if_statinc(ifp, if_ierrors); 911 goto give_it_back; 912 } 913 914 /* CRC is included with the packet; trim it off. */ 915 buflen -= ETHER_CRC_LEN; 916 917 if (m == NULL) { 918 MGETHDR(m, M_DONTWAIT, MT_DATA); 919 if (m == NULL) { 920 GE_DPRINTF(sc, ("?")); 921 break; 922 } 923 } 924 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 925 MCLGET(m, M_DONTWAIT); 926 if ((m->m_flags & M_EXT) == 0) { 927 GE_DPRINTF(sc, ("?")); 928 break; 929 } 930 } 931 m->m_data += 2; 932 m->m_len = 0; 933 m->m_pkthdr.len = 0; 934 m_set_rcvif(m, ifp); 935 rxq->rxq_cmdsts = cmdsts; 936 --rxq->rxq_active; 937 938 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 939 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 940 941 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 942 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 943 m->m_len = buflen; 944 m->m_pkthdr.len = buflen; 945 946 eh = (const struct ether_header *) m->m_data; 947 if ((ifp->if_flags & IFF_PROMISC) || 948 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 949 (rxq->rxq_cmdsts & RX_STS_HE) || 950 (eh->ether_dhost[0] & 1) != 0 || 951 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 952 ETHER_ADDR_LEN) == 0) { 953 if_percpuq_enqueue(ifp->if_percpuq, m); 954 m = NULL; 955 GE_DPRINTF(sc, (">")); 956 } else { 957 m->m_len = 0; 958 m->m_pkthdr.len = 0; 959 GE_DPRINTF(sc, ("+")); 960 } 961 rxq->rxq_cmdsts = 0; 962 963 give_it_back: 964 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 965 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 966 #if 0 967 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 968 rxq->rxq_fi, 969 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 970 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 971 #endif 972 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 973 if (++rxq->rxq_fi == GE_RXDESC_MAX) 974 rxq->rxq_fi = 0; 975 rxq->rxq_active++; 976 } 977 rxq->rxq_curpkt = m; 978 GE_FUNC_EXIT(sc, ""); 979 } 980 981 uint32_t 982 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 983 { 984 struct ifnet * const ifp = &sc->sc_ec.ec_if; 985 struct gfe_rxqueue *rxq; 986 uint32_t rxbits; 987 #define RXPRIO_DECODER 0xffffaa50 988 GE_FUNC_ENTER(sc, "gfe_rx_process"); 989 990 rxbits = ETH_IR_RxBuffer_GET(cause); 991 while (rxbits) { 992 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 993 GE_DPRINTF(sc, ("%1x", rxbits)); 994 rxbits &= ~(1 << rxprio); 995 gfe_rx_get(sc, rxprio); 996 } 997 998 rxbits = ETH_IR_RxError_GET(cause); 999 while (rxbits) { 1000 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 1001 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 1002 int idx; 1003 rxbits &= ~(1 << rxprio); 1004 rxq = &sc->sc_rxq[rxprio]; 1005 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 1006 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 1007 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 1008 sc->sc_tickflags |= GE_TICK_RX_RESTART; 1009 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 1010 } 1011 if_statinc(ifp, if_ierrors); 1012 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 1013 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi)); 1014 memset(masks, 0, sizeof(masks)); 1015 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1016 0, rxq->rxq_desc_mem.gdm_size, 1017 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1018 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 1019 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 1020 1021 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 1022 masks[idx/32] |= 1 << (idx & 31); 1023 } 1024 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1025 0, rxq->rxq_desc_mem.gdm_size, 1026 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1027 #if defined(DEBUG) 1028 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 1029 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi, 1030 rxq->rxq_cmdsts, masks[0], masks[1]); 1031 #endif 1032 } 1033 if ((intrmask & ETH_IR_RxBits) == 0) 1034 intrmask &= ~(ETH_IR_RxBuffer | ETH_IR_RxError); 1035 1036 GE_FUNC_EXIT(sc, ""); 1037 return intrmask; 1038 } 1039 1040 int 1041 gfe_rx_prime(struct gfe_softc *sc) 1042 { 1043 struct gfe_rxqueue *rxq; 1044 int error; 1045 1046 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 1047 1048 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 1049 if (error) 1050 goto bail; 1051 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1052 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1053 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1054 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1055 } 1056 sc->sc_intrmask |= rxq->rxq_intrbits; 1057 1058 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 1059 if (error) 1060 goto bail; 1061 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1062 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1063 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1064 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1065 sc->sc_intrmask |= rxq->rxq_intrbits; 1066 } 1067 1068 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 1069 if (error) 1070 goto bail; 1071 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1072 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1073 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1074 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1075 sc->sc_intrmask |= rxq->rxq_intrbits; 1076 } 1077 1078 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 1079 if (error) 1080 goto bail; 1081 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1082 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1083 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1084 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1085 sc->sc_intrmask |= rxq->rxq_intrbits; 1086 } 1087 1088 bail: 1089 GE_FUNC_EXIT(sc, ""); 1090 return error; 1091 } 1092 1093 void 1094 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 1095 { 1096 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 1097 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 1098 if (rxq == NULL) { 1099 GE_FUNC_EXIT(sc, ""); 1100 return; 1101 } 1102 1103 if (rxq->rxq_curpkt) 1104 m_freem(rxq->rxq_curpkt); 1105 if ((sc->sc_flags & GE_NOFREE) == 0) { 1106 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 1107 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 1108 } 1109 GE_FUNC_EXIT(sc, ""); 1110 } 1111 1112 void 1113 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1114 { 1115 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 1116 sc->sc_flags &= ~GE_RXACTIVE; 1117 sc->sc_idlemask &= ~(ETH_IR_RxBits | ETH_IR_RxBuffer | ETH_IR_RxError); 1118 sc->sc_intrmask &= ~(ETH_IR_RxBits | ETH_IR_RxBuffer | ETH_IR_RxError); 1119 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1120 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR); 1121 do { 1122 delay(10); 1123 } while (GE_READ(sc, ETH_ESDCMR) & ETH_ESDCMR_AR); 1124 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 1125 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 1126 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 1127 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 1128 GE_FUNC_EXIT(sc, ""); 1129 } 1130 1131 void 1132 gfe_tick(void *arg) 1133 { 1134 struct gfe_softc * const sc = arg; 1135 uint32_t intrmask; 1136 unsigned int tickflags; 1137 int s; 1138 1139 GE_FUNC_ENTER(sc, "gfe_tick"); 1140 1141 s = splnet(); 1142 1143 tickflags = sc->sc_tickflags; 1144 sc->sc_tickflags = 0; 1145 intrmask = sc->sc_intrmask; 1146 if (tickflags & GE_TICK_TX_IFSTART) 1147 gfe_ifstart(&sc->sc_ec.ec_if); 1148 if (tickflags & GE_TICK_RX_RESTART) { 1149 intrmask |= sc->sc_idlemask; 1150 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3 | ETH_IR_RxError_3)) { 1151 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1152 rxq->rxq_fi = 0; 1153 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1154 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1155 } 1156 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2 | ETH_IR_RxError_2)) { 1157 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1158 rxq->rxq_fi = 0; 1159 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1160 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1161 } 1162 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1 | ETH_IR_RxError_1)) { 1163 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1164 rxq->rxq_fi = 0; 1165 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1166 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1167 } 1168 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0 | ETH_IR_RxError_0)) { 1169 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1170 rxq->rxq_fi = 0; 1171 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1172 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1173 } 1174 sc->sc_idlemask = 0; 1175 } 1176 if (intrmask != sc->sc_intrmask) { 1177 sc->sc_intrmask = intrmask; 1178 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1179 } 1180 gfe_intr(sc); 1181 splx(s); 1182 1183 GE_FUNC_EXIT(sc, ""); 1184 } 1185 1186 int 1187 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1188 { 1189 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1190 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1191 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1192 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1193 uint32_t intrmask = sc->sc_intrmask; 1194 size_t buflen; 1195 struct mbuf *m; 1196 1197 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1198 1199 /* 1200 * Anything in the pending queue to enqueue? if not, punt. Likewise 1201 * if the txq is not yet created. 1202 * otherwise grab its dmamap. 1203 */ 1204 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1205 GE_FUNC_EXIT(sc, "-"); 1206 return 0; 1207 } 1208 1209 /* 1210 * Have we [over]consumed our limit of descriptors? 1211 * Do we have enough free descriptors? 1212 */ 1213 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1214 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1215 uint32_t cmdsts; 1216 size_t pktlen; 1217 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1218 cmdsts = gt32toh(txd2->ed_cmdsts); 1219 if (cmdsts & TX_CMD_O) { 1220 int nextin; 1221 /* 1222 * Sometime the Discovery forgets to update the 1223 * last descriptor. See if we own the descriptor 1224 * after it (since we know we've turned that to 1225 * the discovery and if we owned it, the Discovery 1226 * gave it back). If we do, we know the Discovery 1227 * gave back this one but forgot to mark it as ours. 1228 */ 1229 nextin = txq->txq_fi + 1; 1230 if (nextin == GE_TXDESC_MAX) 1231 nextin = 0; 1232 GE_TXDPOSTSYNC(sc, txq, nextin); 1233 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1234 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1235 GE_TXDPRESYNC(sc, txq, nextin); 1236 GE_FUNC_EXIT(sc, "@"); 1237 return 0; 1238 } 1239 #ifdef DEBUG 1240 printf("%s: txenqueue: transmitter resynced at %d\n", 1241 device_xname(sc->sc_dev), txq->txq_fi); 1242 #endif 1243 } 1244 if (++txq->txq_fi == GE_TXDESC_MAX) 1245 txq->txq_fi = 0; 1246 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1247 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1248 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1249 txq->txq_nactive--; 1250 1251 /* statistics */ 1252 if_statinc(ifp, if_opackets); 1253 if (cmdsts & TX_STS_ES) 1254 if_statinc(ifp, if_oerrors); 1255 GE_DPRINTF(sc, ("%%")); 1256 } 1257 1258 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1259 1260 /* 1261 * If this packet would wrap around the end of the buffer, reset back 1262 * to the beginning. 1263 */ 1264 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1265 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1266 txq->txq_outptr = 0; 1267 } 1268 1269 /* 1270 * Make sure the output packet doesn't run over the beginning of 1271 * what we've already given the GT. 1272 */ 1273 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1274 txq->txq_outptr + buflen > txq->txq_inptr) { 1275 intrmask |= txq->txq_intrbits & 1276 (ETH_IR_TxBufferHigh | ETH_IR_TxBufferLow); 1277 if (sc->sc_intrmask != intrmask) { 1278 sc->sc_intrmask = intrmask; 1279 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1280 } 1281 GE_FUNC_EXIT(sc, "#"); 1282 return 0; 1283 } 1284 1285 /* 1286 * The end-of-list descriptor we put on last time is the starting point 1287 * for this packet. The GT is supposed to terminate list processing on 1288 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1289 * must terminate the list. 1290 */ 1291 intrmask = sc->sc_intrmask; 1292 1293 m_copydata(m, 0, m->m_pkthdr.len, 1294 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1295 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1296 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1297 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1298 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1299 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1300 1301 /* 1302 * Request a buffer interrupt every 2/3 of the way thru the transmit 1303 * buffer. 1304 */ 1305 txq->txq_ei_gapcount += buflen; 1306 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1307 txd->ed_cmdsts = htogt32(TX_CMD_FIRST |TX_CMD_LAST |TX_CMD_EI); 1308 txq->txq_ei_gapcount = 0; 1309 } else { 1310 txd->ed_cmdsts = htogt32(TX_CMD_FIRST | TX_CMD_LAST); 1311 } 1312 #if 0 1313 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1314 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1315 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1316 #endif 1317 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1318 1319 txq->txq_outptr += buflen; 1320 /* 1321 * Tell the SDMA engine to "Fetch!" 1322 */ 1323 GE_WRITE(sc, ETH_ESDCMR, 1324 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH | ETH_ESDCMR_TXDL)); 1325 1326 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1327 1328 /* 1329 * Update the last out appropriately. 1330 */ 1331 txq->txq_nactive++; 1332 if (++txq->txq_lo == GE_TXDESC_MAX) 1333 txq->txq_lo = 0; 1334 1335 /* 1336 * Move mbuf from the pending queue to the snd queue. 1337 */ 1338 IF_DEQUEUE(&txq->txq_pendq, m); 1339 bpf_mtap(ifp, m, BPF_D_OUT); 1340 m_freem(m); 1341 ifp->if_flags &= ~IFF_OACTIVE; 1342 1343 /* 1344 * Since we have put an item into the packet queue, we now want 1345 * an interrupt when the transmit queue finishes processing the 1346 * list. But only update the mask if needs changing. 1347 */ 1348 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh | ETH_IR_TxEndLow); 1349 if (sc->sc_intrmask != intrmask) { 1350 sc->sc_intrmask = intrmask; 1351 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1352 } 1353 if (ifp->if_timer == 0) 1354 ifp->if_timer = 5; 1355 GE_FUNC_EXIT(sc, "*"); 1356 return 1; 1357 } 1358 1359 uint32_t 1360 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1361 { 1362 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1363 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1364 1365 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1366 1367 if (txq == NULL) { 1368 GE_FUNC_EXIT(sc, ""); 1369 return intrmask; 1370 } 1371 1372 while (txq->txq_nactive > 0) { 1373 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1374 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1375 uint32_t cmdsts; 1376 size_t pktlen; 1377 1378 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1379 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1380 int nextin; 1381 1382 if (txq->txq_nactive == 1) { 1383 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1384 GE_FUNC_EXIT(sc, ""); 1385 return intrmask; 1386 } 1387 /* 1388 * Sometimes the Discovery forgets to update the 1389 * ownership bit in the descriptor. See if we own the 1390 * descriptor after it (since we know we've turned 1391 * that to the Discovery and if we own it now then the 1392 * Discovery gave it back). If we do, we know the 1393 * Discovery gave back this one but forgot to mark it 1394 * as ours. 1395 */ 1396 nextin = txq->txq_fi + 1; 1397 if (nextin == GE_TXDESC_MAX) 1398 nextin = 0; 1399 GE_TXDPOSTSYNC(sc, txq, nextin); 1400 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1401 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1402 GE_TXDPRESYNC(sc, txq, nextin); 1403 GE_FUNC_EXIT(sc, ""); 1404 return intrmask; 1405 } 1406 #ifdef DEBUG 1407 printf("%s: txdone: transmitter resynced at %d\n", 1408 device_xname(sc->sc_dev), txq->txq_fi); 1409 #endif 1410 } 1411 #if 0 1412 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1413 txq->txq_lo, 1414 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1415 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1416 #endif 1417 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1418 if (++txq->txq_fi == GE_TXDESC_MAX) 1419 txq->txq_fi = 0; 1420 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1421 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1422 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1423 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1424 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1425 1426 /* statistics */ 1427 if_statinc(ifp, if_opackets); 1428 if (cmdsts & TX_STS_ES) 1429 if_statinc(ifp, if_oerrors); 1430 1431 /* txd->ed_bufptr = 0; */ 1432 1433 ifp->if_timer = 5; 1434 --txq->txq_nactive; 1435 } 1436 if (txq->txq_nactive != 0) 1437 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1438 device_xname(sc->sc_dev), txprio, txq->txq_nactive); 1439 ifp->if_timer = 0; 1440 intrmask &= 1441 ~(txq->txq_intrbits & (ETH_IR_TxEndHigh | ETH_IR_TxEndLow)); 1442 intrmask &= 1443 ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh | ETH_IR_TxBufferLow)); 1444 GE_FUNC_EXIT(sc, ""); 1445 return intrmask; 1446 } 1447 1448 int 1449 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1450 { 1451 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1452 int error; 1453 1454 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1455 1456 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1457 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1458 if (error) { 1459 GE_FUNC_EXIT(sc, ""); 1460 return error; 1461 } 1462 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1463 if (error) { 1464 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1465 GE_FUNC_EXIT(sc, ""); 1466 return error; 1467 } 1468 GE_FUNC_EXIT(sc, ""); 1469 return 0; 1470 } 1471 1472 int 1473 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1474 { 1475 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1476 volatile struct gt_eth_desc *txd; 1477 unsigned int i; 1478 bus_addr_t addr; 1479 1480 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1481 1482 sc->sc_intrmask &= 1483 ~(ETH_IR_TxEndHigh | 1484 ETH_IR_TxBufferHigh | 1485 ETH_IR_TxEndLow | 1486 ETH_IR_TxBufferLow); 1487 1488 if (sc->sc_flags & GE_NOFREE) { 1489 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1490 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1491 } else { 1492 int error = gfe_tx_txqalloc(sc, txprio); 1493 if (error) { 1494 GE_FUNC_EXIT(sc, "!"); 1495 return error; 1496 } 1497 } 1498 1499 txq->txq_descs = 1500 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1501 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1502 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1503 1504 txq->txq_pendq.ifq_maxlen = 10; 1505 txq->txq_ei_gapcount = 0; 1506 txq->txq_nactive = 0; 1507 txq->txq_fi = 0; 1508 txq->txq_lo = 0; 1509 txq->txq_inptr = GE_TXBUF_SIZE; 1510 txq->txq_outptr = 0; 1511 for (i = 0, txd = txq->txq_descs, 1512 addr = txq->txq_desc_busaddr + sizeof(*txd); 1513 i < GE_TXDESC_MAX - 1; i++, txd++, addr += sizeof(*txd)) { 1514 /* 1515 * update the nxtptr to point to the next txd. 1516 */ 1517 txd->ed_cmdsts = 0; 1518 txd->ed_nxtptr = htogt32(addr); 1519 } 1520 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1521 htogt32(txq->txq_desc_busaddr); 1522 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1523 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1524 1525 switch (txprio) { 1526 case GE_TXPRIO_HI: 1527 txq->txq_intrbits = ETH_IR_TxEndHigh | ETH_IR_TxBufferHigh; 1528 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1529 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1530 txq->txq_ectdp = ETH_ECTDP1; 1531 GE_WRITE(sc, ETH_ECTDP1, txq->txq_desc_busaddr); 1532 break; 1533 1534 case GE_TXPRIO_LO: 1535 txq->txq_intrbits = ETH_IR_TxEndLow | ETH_IR_TxBufferLow; 1536 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1537 txq->txq_epsrbits = ETH_EPSR_TxLow; 1538 txq->txq_ectdp = ETH_ECTDP0; 1539 GE_WRITE(sc, ETH_ECTDP0, txq->txq_desc_busaddr); 1540 break; 1541 1542 case GE_TXPRIO_NONE: 1543 break; 1544 } 1545 #if 0 1546 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1547 GE_WRITE(sc->sc_dev, txq->txq_ectdp, txq->txq_desc_busaddr); 1548 GE_DPRINTF(sc, (")")); 1549 #endif 1550 1551 /* 1552 * If we are restarting, there may be packets in the pending queue 1553 * waiting to be enqueued. Try enqueuing packets from both priority 1554 * queues until the pending queue is empty or there no room for them 1555 * on the device. 1556 */ 1557 while (gfe_tx_enqueue(sc, txprio)) 1558 continue; 1559 1560 GE_FUNC_EXIT(sc, ""); 1561 return 0; 1562 } 1563 1564 void 1565 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1566 { 1567 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1568 1569 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1570 if (txq == NULL) { 1571 GE_FUNC_EXIT(sc, ""); 1572 return; 1573 } 1574 1575 if (!flush) { 1576 GE_FUNC_EXIT(sc, ""); 1577 return; 1578 } 1579 1580 if ((sc->sc_flags & GE_NOFREE) == 0) { 1581 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1582 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1583 } 1584 GE_FUNC_EXIT(sc, "-F"); 1585 } 1586 1587 void 1588 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1589 { 1590 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1591 1592 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_STDH | ETH_ESDCMR_STDL); 1593 1594 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1595 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1596 sc->sc_intrmask &= 1597 ~(ETH_IR_TxEndHigh | 1598 ETH_IR_TxBufferHigh | 1599 ETH_IR_TxEndLow | 1600 ETH_IR_TxBufferLow); 1601 1602 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1603 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1604 1605 sc->sc_ec.ec_if.if_timer = 0; 1606 GE_FUNC_EXIT(sc, ""); 1607 } 1608 1609 int 1610 gfe_intr(void *arg) 1611 { 1612 struct gfe_softc * const sc = arg; 1613 uint32_t cause; 1614 uint32_t intrmask = sc->sc_intrmask; 1615 int claim = 0; 1616 int cnt; 1617 1618 GE_FUNC_ENTER(sc, "gfe_intr"); 1619 1620 for (cnt = 0; cnt < 4; cnt++) { 1621 if (sc->sc_intrmask != intrmask) { 1622 sc->sc_intrmask = intrmask; 1623 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1624 } 1625 cause = GE_READ(sc, ETH_EICR); 1626 cause &= sc->sc_intrmask; 1627 GE_DPRINTF(sc, (".%#x", cause)); 1628 if (cause == 0) 1629 break; 1630 1631 claim = 1; 1632 1633 GE_WRITE(sc, ETH_EICR, ~cause); 1634 #ifndef GE_NORX 1635 if (cause & (ETH_IR_RxBuffer | ETH_IR_RxError)) 1636 intrmask = gfe_rx_process(sc, cause, intrmask); 1637 #endif 1638 1639 #ifndef GE_NOTX 1640 if (cause & (ETH_IR_TxBufferHigh | ETH_IR_TxEndHigh)) 1641 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1642 if (cause & (ETH_IR_TxBufferLow | ETH_IR_TxEndLow)) 1643 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1644 #endif 1645 if (cause & ETH_IR_MIIPhySTC) { 1646 sc->sc_flags |= GE_PHYSTSCHG; 1647 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1648 } 1649 } 1650 1651 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1652 continue; 1653 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1654 continue; 1655 1656 GE_FUNC_EXIT(sc, ""); 1657 return claim; 1658 } 1659 1660 int 1661 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1662 { 1663 int error = 0; 1664 GE_FUNC_ENTER(sc, "gfe_whack"); 1665 1666 switch (op) { 1667 case GE_WHACK_RESTART: 1668 #ifndef GE_NOTX 1669 gfe_tx_stop(sc, op); 1670 #endif 1671 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1672 /* FALLTHROUGH */ 1673 case GE_WHACK_START: 1674 #ifndef GE_NOHASH 1675 if (error == 0 && sc->sc_hashtable == NULL) { 1676 error = gfe_hash_alloc(sc); 1677 if (error) 1678 break; 1679 } 1680 if (op != GE_WHACK_RESTART) 1681 gfe_hash_fill(sc); 1682 #endif 1683 #ifndef GE_NORX 1684 if (op != GE_WHACK_RESTART) { 1685 error = gfe_rx_prime(sc); 1686 if (error) 1687 break; 1688 } 1689 #endif 1690 #ifndef GE_NOTX 1691 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1692 if (error) 1693 break; 1694 #endif 1695 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1696 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1697 GE_WRITE(sc, ETH_EPCXR, sc->sc_pcxr); 1698 GE_WRITE(sc, ETH_EICR, 0); 1699 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1700 #ifndef GE_NOHASH 1701 GE_WRITE(sc, ETH_EHTPR, 1702 sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1703 #endif 1704 #ifndef GE_NORX 1705 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_ERD); 1706 sc->sc_flags |= GE_RXACTIVE; 1707 #endif 1708 /* FALLTHROUGH */ 1709 case GE_WHACK_CHANGE: 1710 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1711 GE_READ(sc, ETH_EPCR), GE_READ(sc, ETH_EIMR))); 1712 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1713 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1714 gfe_ifstart(&sc->sc_ec.ec_if); 1715 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1716 GE_READ(sc, ETH_ECTDP0), GE_READ(sc, ETH_ECTDP1))); 1717 GE_FUNC_EXIT(sc, ""); 1718 return error; 1719 case GE_WHACK_STOP: 1720 break; 1721 } 1722 1723 #ifdef GE_DEBUG 1724 if (error) 1725 GE_DPRINTF(sc, (" failed: %d\n", error)); 1726 #endif 1727 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1728 GE_WRITE(sc, ETH_EIMR, 0); 1729 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1730 #ifndef GE_NOTX 1731 gfe_tx_stop(sc, GE_WHACK_STOP); 1732 #endif 1733 #ifndef GE_NORX 1734 gfe_rx_stop(sc, GE_WHACK_STOP); 1735 #endif 1736 #ifndef GE_NOHASH 1737 if ((sc->sc_flags & GE_NOFREE) == 0) { 1738 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1739 sc->sc_hashtable = NULL; 1740 } 1741 #endif 1742 1743 GE_FUNC_EXIT(sc, ""); 1744 return error; 1745 } 1746 1747 int 1748 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1749 { 1750 uint32_t w0, add0, add1; 1751 uint32_t result; 1752 1753 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1754 add0 = ((uint32_t) eaddr[5] << 0) | 1755 ((uint32_t) eaddr[4] << 8) | 1756 ((uint32_t) eaddr[3] << 16); 1757 1758 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1759 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1760 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1761 1762 add1 = ((uint32_t) eaddr[2] << 0) | 1763 ((uint32_t) eaddr[1] << 8) | 1764 ((uint32_t) eaddr[0] << 16); 1765 1766 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1767 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1768 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1769 1770 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1771 /* 1772 * hashResult is the 15 bits Hash entry address. 1773 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1774 * MAC address, by nibble swapping in every byte (i.e MAC address 1775 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1776 */ 1777 1778 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1779 /* 1780 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1781 * 1782 * hashFunc0 calculates the hashResult in the following manner: 1783 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1784 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1785 */ 1786 result = (add0 & 3) | ((add0 >> 6) & ~3); 1787 result ^= (add0 >> 15) ^ (add1 >> 0); 1788 result &= 0x1ff; 1789 /* 1790 * hashResult[14:9] = ethernetADD[7:2] 1791 */ 1792 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1793 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1794 } else { 1795 #define TRIBITFLIP 073516240 /* yes its in octal */ 1796 /* 1797 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1798 * 1799 * hashFunc1 calculates the hashResult in the following manner: 1800 * hashResult[08:00] = ethernetADD[06:14] 1801 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1802 */ 1803 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1804 /* 1805 * Now bitswap those 9 bits 1806 */ 1807 result = 0; 1808 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1809 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1810 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1811 1812 /* 1813 * hashResult[14:09] = ethernetADD[00:05] 1814 */ 1815 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1816 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1817 GE_DPRINTF(sc, ("1(%#x)", result)); 1818 } 1819 GE_FUNC_EXIT(sc, ""); 1820 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1821 } 1822 1823 int 1824 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1825 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1826 { 1827 uint64_t he; 1828 uint64_t *maybe_he_p = NULL; 1829 int limit; 1830 int hash; 1831 int maybe_hash = 0; 1832 1833 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1834 1835 hash = gfe_hash_compute(sc, eaddr); 1836 1837 if (sc->sc_hashtable == NULL) { 1838 panic("%s:%d: hashtable == NULL!", device_xname(sc->sc_dev), 1839 __LINE__); 1840 } 1841 1842 /* 1843 * Assume we are going to insert so create the hash entry we 1844 * are going to insert. We also use it to match entries we 1845 * will be removing. 1846 */ 1847 he = ((uint64_t) eaddr[5] << 43) | 1848 ((uint64_t) eaddr[4] << 35) | 1849 ((uint64_t) eaddr[3] << 27) | 1850 ((uint64_t) eaddr[2] << 19) | 1851 ((uint64_t) eaddr[1] << 11) | 1852 ((uint64_t) eaddr[0] << 3) | 1853 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1854 1855 /* 1856 * The GT will search upto 12 entries for a hit, so we must mimic that. 1857 */ 1858 hash &= sc->sc_hashmask / sizeof(he); 1859 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1860 /* 1861 * Does the GT wrap at the end, stop at the, or overrun the 1862 * end? Assume it wraps for now. Stash a copy of the 1863 * current hash entry. 1864 */ 1865 uint64_t *he_p = &sc->sc_hashtable[hash]; 1866 uint64_t thishe = *he_p; 1867 1868 /* 1869 * If the hash entry isn't valid, that break the chain. And 1870 * this entry a good candidate for reuse. 1871 */ 1872 if ((thishe & HSH_V) == 0) { 1873 maybe_he_p = he_p; 1874 break; 1875 } 1876 1877 /* 1878 * If the hash entry has the same address we are looking for 1879 * then ... if we are removing and the skip bit is set, its 1880 * already been removed. if are adding and the skip bit is 1881 * clear, then its already added. In either return EBUSY 1882 * indicating the op has already been done. Otherwise flip 1883 * the skip bit and return 0. 1884 */ 1885 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1886 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1887 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1888 return EBUSY; 1889 *he_p = thishe ^ HSH_S; 1890 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1891 hash * sizeof(he), sizeof(he), 1892 BUS_DMASYNC_PREWRITE); 1893 GE_FUNC_EXIT(sc, "^"); 1894 return 0; 1895 } 1896 1897 /* 1898 * If we haven't found a slot for the entry and this entry 1899 * is currently being skipped, return this entry. 1900 */ 1901 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1902 maybe_he_p = he_p; 1903 maybe_hash = hash; 1904 } 1905 1906 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1907 } 1908 1909 /* 1910 * If we got here, then there was no entry to remove. 1911 */ 1912 if (op == GE_HASH_REMOVE) { 1913 GE_FUNC_EXIT(sc, "?"); 1914 return ENOENT; 1915 } 1916 1917 /* 1918 * If we couldn't find a slot, return an error. 1919 */ 1920 if (maybe_he_p == NULL) { 1921 GE_FUNC_EXIT(sc, "!"); 1922 return ENOSPC; 1923 } 1924 1925 /* Update the entry. 1926 */ 1927 *maybe_he_p = he; 1928 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1929 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1930 GE_FUNC_EXIT(sc, "+"); 1931 return 0; 1932 } 1933 1934 int 1935 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, 1936 u_long cmd) 1937 { 1938 struct gfe_softc *sc = ec->ec_if.if_softc; 1939 int error; 1940 enum gfe_hash_op op; 1941 enum gfe_rxprio prio; 1942 1943 GE_FUNC_ENTER(sc, "hash_multichg"); 1944 /* 1945 * Is this a wildcard entry? If so and its being removed, recompute. 1946 */ 1947 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1948 if (cmd == SIOCDELMULTI) { 1949 GE_FUNC_EXIT(sc, ""); 1950 return ENETRESET; 1951 } 1952 1953 /* 1954 * Switch in 1955 */ 1956 sc->sc_flags |= GE_ALLMULTI; 1957 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1958 sc->sc_pcr |= ETH_EPCR_PM; 1959 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1960 GE_FUNC_EXIT(sc, ""); 1961 return 0; 1962 } 1963 GE_FUNC_EXIT(sc, ""); 1964 return ENETRESET; 1965 } 1966 1967 prio = GE_RXPRIO_MEDLO; 1968 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1969 1970 if (sc->sc_hashtable == NULL) { 1971 GE_FUNC_EXIT(sc, ""); 1972 return 0; 1973 } 1974 1975 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1976 if (error == EBUSY) { 1977 aprint_error_dev(sc->sc_dev, "multichg: tried to %s %s again\n", 1978 cmd == SIOCDELMULTI ? "remove" : "add", 1979 ether_sprintf(enm->enm_addrlo)); 1980 GE_FUNC_EXIT(sc, ""); 1981 return 0; 1982 } 1983 1984 if (error == ENOENT) { 1985 aprint_error_dev(sc->sc_dev, 1986 "multichg: failed to remove %s: not in table\n", 1987 ether_sprintf(enm->enm_addrlo)); 1988 GE_FUNC_EXIT(sc, ""); 1989 return 0; 1990 } 1991 1992 if (error == ENOSPC) { 1993 aprint_error_dev(sc->sc_dev, "multichg:" 1994 " failed to add %s: no space; regenerating table\n", 1995 ether_sprintf(enm->enm_addrlo)); 1996 GE_FUNC_EXIT(sc, ""); 1997 return ENETRESET; 1998 } 1999 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 2000 device_xname(sc->sc_dev), 2001 cmd == SIOCDELMULTI ? "remove" : "add", 2002 ether_sprintf(enm->enm_addrlo))); 2003 GE_FUNC_EXIT(sc, ""); 2004 return 0; 2005 } 2006 2007 int 2008 gfe_hash_fill(struct gfe_softc *sc) 2009 { 2010 struct ethercom *ec = &sc->sc_ec; 2011 struct ether_multistep step; 2012 struct ether_multi *enm; 2013 int error; 2014 2015 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 2016 2017 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 2018 CLLADDR(ec->ec_if.if_sadl)); 2019 if (error) { 2020 GE_FUNC_EXIT(sc, "!"); 2021 return error; 2022 } 2023 2024 sc->sc_flags &= ~GE_ALLMULTI; 2025 if ((ec->ec_if.if_flags & IFF_PROMISC) == 0) 2026 sc->sc_pcr &= ~ETH_EPCR_PM; 2027 ETHER_LOCK(ec); 2028 ETHER_FIRST_MULTI(step, ec, enm); 2029 while (enm != NULL) { 2030 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2031 sc->sc_flags |= GE_ALLMULTI; 2032 sc->sc_pcr |= ETH_EPCR_PM; 2033 } else { 2034 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 2035 GE_RXPRIO_MEDLO, enm->enm_addrlo); 2036 if (error == ENOSPC) 2037 break; 2038 } 2039 ETHER_NEXT_MULTI(step, enm); 2040 } 2041 ETHER_UNLOCK(ec); 2042 2043 GE_FUNC_EXIT(sc, ""); 2044 return error; 2045 } 2046 2047 int 2048 gfe_hash_alloc(struct gfe_softc *sc) 2049 { 2050 int error; 2051 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 2052 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 2053 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 2054 BUS_DMA_NOCACHE); 2055 if (error) { 2056 aprint_error_dev(sc->sc_dev, 2057 "failed to allocate %d bytes for hash table: %d\n", 2058 sc->sc_hashmask + 1, error); 2059 GE_FUNC_EXIT(sc, ""); 2060 return error; 2061 } 2062 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 2063 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 2064 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 2065 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 2066 GE_FUNC_EXIT(sc, ""); 2067 return 0; 2068 } 2069