1 /* $NetBSD: if_gfe.c,v 1.41 2012/07/22 14:32:59 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.41 2012/07/22 14:32:59 matt Exp $"); 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/bus.h> 51 #include <sys/callout.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/ioctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/mutex.h> 57 #include <sys/socket.h> 58 59 #include <uvm/uvm.h> 60 #include <net/if.h> 61 #include <net/if_dl.h> 62 #include <net/if_ether.h> 63 #include <net/if_media.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/if_inarp.h> 68 #endif 69 #include <net/bpf.h> 70 #include <sys/rnd.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/marvell/gtreg.h> 76 #include <dev/marvell/gtvar.h> 77 #include <dev/marvell/gtethreg.h> 78 #include <dev/marvell/if_gfevar.h> 79 #include <dev/marvell/marvellreg.h> 80 #include <dev/marvell/marvellvar.h> 81 82 #include <prop/proplib.h> 83 84 #include "locators.h" 85 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) \ 100 do { \ 101 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 102 printf a; \ 103 } while (0 /* CONSTCOND */) 104 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 105 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 106 #else 107 #define GE_DPRINTF(sc, a) do { } while (0) 108 #define GE_FUNC_ENTER(sc, func) do { } while (0) 109 #define GE_FUNC_EXIT(sc, str) do { } while (0) 110 #endif 111 enum gfe_whack_op { 112 GE_WHACK_START, GE_WHACK_RESTART, 113 GE_WHACK_CHANGE, GE_WHACK_STOP 114 }; 115 116 enum gfe_hash_op { 117 GE_HASH_ADD, GE_HASH_REMOVE, 118 }; 119 120 #if 1 121 #define htogt32(a) htobe32(a) 122 #define gt32toh(a) be32toh(a) 123 #else 124 #define htogt32(a) htole32(a) 125 #define gt32toh(a) le32toh(a) 126 #endif 127 128 #define GE_RXDSYNC(sc, rxq, n, ops) \ 129 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 130 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 131 (ops)) 132 #define GE_RXDPRESYNC(sc, rxq, n) \ 133 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 134 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 135 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 136 137 #define GE_TXDSYNC(sc, txq, n, ops) \ 138 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 139 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 140 (ops)) 141 #define GE_TXDPRESYNC(sc, txq, n) \ 142 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 143 #define GE_TXDPOSTSYNC(sc, txq, n) \ 144 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 145 146 #define STATIC 147 148 149 STATIC int gfec_match(device_t, cfdata_t, void *); 150 STATIC void gfec_attach(device_t, device_t, void *); 151 152 STATIC int gfec_print(void *, const char *); 153 STATIC int gfec_search(device_t, cfdata_t, const int *, void *); 154 155 STATIC int gfec_enet_phy(device_t, int); 156 STATIC int gfec_mii_read(device_t, int, int); 157 STATIC void gfec_mii_write(device_t, int, int, int); 158 STATIC void gfec_mii_statchg(struct ifnet *); 159 160 STATIC int gfe_match(device_t, cfdata_t, void *); 161 STATIC void gfe_attach(device_t, device_t, void *); 162 163 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 164 size_t, int); 165 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 166 167 STATIC int gfe_ifioctl(struct ifnet *, u_long, void *); 168 STATIC void gfe_ifstart(struct ifnet *); 169 STATIC void gfe_ifwatchdog(struct ifnet *); 170 171 STATIC void gfe_tick(void *arg); 172 173 STATIC void gfe_tx_restart(void *); 174 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 175 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 176 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 177 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 178 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 179 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 180 181 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 182 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 183 STATIC int gfe_rx_prime(struct gfe_softc *); 184 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 185 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 186 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 187 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 188 189 STATIC int gfe_intr(void *); 190 191 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 192 193 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 194 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 195 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 196 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 197 u_long); 198 STATIC int gfe_hash_fill(struct gfe_softc *); 199 STATIC int gfe_hash_alloc(struct gfe_softc *); 200 201 202 CFATTACH_DECL_NEW(gfec, sizeof(struct gfec_softc), 203 gfec_match, gfec_attach, NULL, NULL); 204 CFATTACH_DECL_NEW(gfe, sizeof(struct gfe_softc), 205 gfe_match, gfe_attach, NULL, NULL); 206 207 208 /* ARGSUSED */ 209 int 210 gfec_match(device_t parent, cfdata_t cf, void *aux) 211 { 212 struct marvell_attach_args *mva = aux; 213 214 if (strcmp(mva->mva_name, cf->cf_name) != 0) 215 return 0; 216 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 217 return 0; 218 219 mva->mva_size = ETHC_SIZE; 220 return 1; 221 } 222 223 /* ARGSUSED */ 224 void 225 gfec_attach(device_t parent, device_t self, void *aux) 226 { 227 struct gfec_softc *sc = device_private(self); 228 struct marvell_attach_args *mva = aux, gfea; 229 static int gfe_irqs[] = { 32, 33, 34 }; 230 int i; 231 232 aprint_naive("\n"); 233 aprint_normal(": Ethernet Controller\n"); 234 235 sc->sc_dev = self; 236 sc->sc_iot = mva->mva_iot; 237 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 238 mva->mva_size, &sc->sc_ioh)) { 239 aprint_error_dev(self, "Cannot map registers\n"); 240 return; 241 } 242 243 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 244 245 for (i = 0; i < ETH_NUM; i++) { 246 gfea.mva_name = "gfe"; 247 gfea.mva_model = mva->mva_model; 248 gfea.mva_iot = sc->sc_iot; 249 gfea.mva_ioh = sc->sc_ioh; 250 gfea.mva_unit = i; 251 gfea.mva_dmat = mva->mva_dmat; 252 gfea.mva_irq = gfe_irqs[i]; 253 config_found_sm_loc(sc->sc_dev, "gfec", NULL, &gfea, 254 gfec_print, gfec_search); 255 } 256 } 257 258 int 259 gfec_print(void *aux, const char *pnp) 260 { 261 struct marvell_attach_args *gfea = aux; 262 263 if (pnp) 264 aprint_normal("%s at %s port %d", 265 gfea->mva_name, pnp, gfea->mva_unit); 266 else { 267 if (gfea->mva_unit != GFECCF_PORT_DEFAULT) 268 aprint_normal(" port %d", gfea->mva_unit); 269 if (gfea->mva_irq != GFECCF_IRQ_DEFAULT) 270 aprint_normal(" irq %d", gfea->mva_irq); 271 } 272 return UNCONF; 273 } 274 275 /* ARGSUSED */ 276 int 277 gfec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 278 { 279 struct marvell_attach_args *gfea = aux; 280 281 if (cf->cf_loc[GFECCF_PORT] == gfea->mva_unit && 282 cf->cf_loc[GFECCF_IRQ] != GFECCF_IRQ_DEFAULT) 283 gfea->mva_irq = cf->cf_loc[GFECCF_IRQ]; 284 285 return config_match(parent, cf, aux); 286 } 287 288 int 289 gfec_enet_phy(device_t dev, int unit) 290 { 291 struct gfec_softc *sc = device_private(dev); 292 uint32_t epar; 293 294 epar = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ETH_EPAR); 295 return ETH_EPAR_PhyAD_GET(epar, unit); 296 } 297 298 int 299 gfec_mii_read(device_t dev, int phy, int reg) 300 { 301 struct gfec_softc *csc = device_private(device_parent(dev)); 302 uint32_t data; 303 int count = 10000; 304 305 mutex_enter(&csc->sc_mtx); 306 307 do { 308 DELAY(10); 309 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 310 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 311 312 if (count == 0) { 313 aprint_error_dev(dev, 314 "mii read for phy %d reg %d busied out\n", phy, reg); 315 mutex_exit(&csc->sc_mtx); 316 return ETH_ESMIR_Value_GET(data); 317 } 318 319 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 320 ETH_ESMIR_READ(phy, reg)); 321 322 count = 10000; 323 do { 324 DELAY(10); 325 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 326 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 327 328 mutex_exit(&csc->sc_mtx); 329 330 if (count == 0) 331 aprint_error_dev(dev, 332 "mii read for phy %d reg %d timed out\n", phy, reg); 333 #if defined(GTMIIDEBUG) 334 aprint_normal_dev(dev, "mii_read(%d, %d): %#x data %#x\n", 335 phy, reg, data, ETH_ESMIR_Value_GET(data)); 336 #endif 337 return ETH_ESMIR_Value_GET(data); 338 } 339 340 void 341 gfec_mii_write (device_t dev, int phy, int reg, int value) 342 { 343 struct gfec_softc *csc = device_private(device_parent(dev)); 344 uint32_t data; 345 int count = 10000; 346 347 mutex_enter(&csc->sc_mtx); 348 349 do { 350 DELAY(10); 351 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 352 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 353 354 if (count == 0) { 355 aprint_error_dev(dev, 356 "mii write for phy %d reg %d busied out (busy)\n", 357 phy, reg); 358 mutex_exit(&csc->sc_mtx); 359 return; 360 } 361 362 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 363 ETH_ESMIR_WRITE(phy, reg, value)); 364 365 count = 10000; 366 do { 367 DELAY(10); 368 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 369 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 370 371 mutex_exit(&csc->sc_mtx); 372 373 if (count == 0) 374 aprint_error_dev(dev, 375 "mii write for phy %d reg %d timed out\n", phy, reg); 376 #if defined(GTMIIDEBUG) 377 aprint_normal_dev(dev, "mii_write(%d, %d, %#x)\n", phy, reg, value); 378 #endif 379 } 380 381 void 382 gfec_mii_statchg(struct ifnet *ifp) 383 { 384 /* struct gfe_softc *sc = ifp->if_softc; */ 385 /* do nothing? */ 386 } 387 388 /* ARGSUSED */ 389 int 390 gfe_match(device_t parent, cfdata_t cf, void *aux) 391 { 392 393 return 1; 394 } 395 396 /* ARGSUSED */ 397 void 398 gfe_attach(device_t parent, device_t self, void *aux) 399 { 400 struct marvell_attach_args *mva = aux; 401 struct gfe_softc * const sc = device_private(self); 402 struct ifnet * const ifp = &sc->sc_ec.ec_if; 403 uint32_t sdcr; 404 int phyaddr, error; 405 prop_data_t ea; 406 uint8_t enaddr[6]; 407 408 aprint_naive("\n"); 409 aprint_normal(": Ethernet Controller\n"); 410 411 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 412 mva->mva_offset, mva->mva_size, &sc->sc_memh)) { 413 aprint_error_dev(self, "failed to map registers\n"); 414 return; 415 } 416 sc->sc_dev = self; 417 sc->sc_memt = mva->mva_iot; 418 sc->sc_dmat = mva->mva_dmat; 419 sc->sc_macno = (mva->mva_offset == ETH_BASE(0)) ? 0 : 420 ((mva->mva_offset == ETH_BASE(1)) ? 1 : 2); 421 422 callout_init(&sc->sc_co, 0); 423 424 phyaddr = gfec_enet_phy(parent, sc->sc_macno); 425 426 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-addr"); 427 if (ea != NULL) { 428 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 429 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 430 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 431 } 432 433 sc->sc_pcr = GE_READ(sc, ETH_EPCR); 434 sc->sc_pcxr = GE_READ(sc, ETH_EPCXR); 435 sc->sc_intrmask = GE_READ(sc, ETH_EIMR) | ETH_IR_MIIPhySTC; 436 437 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 438 439 #if defined(DEBUG) 440 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 441 #endif 442 443 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 444 if (device_cfdata(self)->cf_flags & 1) { 445 aprint_normal_dev(self, "phy %d (rmii)\n", phyaddr); 446 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 447 } else { 448 aprint_normal_dev(self, "phy %d (mii)\n", phyaddr); 449 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 450 } 451 if (device_cfdata(self)->cf_flags & 2) 452 sc->sc_flags |= GE_NOFREE; 453 /* Set Max Frame Length is 1536 */ 454 sc->sc_pcxr &= ~ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_MASK); 455 sc->sc_pcxr |= ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_1536); 456 sc->sc_max_frame_length = 1536; 457 458 if (sc->sc_pcr & ETH_EPCR_EN) { 459 int tries = 1000; 460 /* 461 * Abort transmitter and receiver and wait for them to quiese 462 */ 463 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR | ETH_ESDCMR_AT); 464 do { 465 delay(100); 466 if (tries-- <= 0) { 467 aprint_error_dev(self, "Abort TX/RX failed\n"); 468 break; 469 } 470 } while (GE_READ(sc, ETH_ESDCMR) & 471 (ETH_ESDCMR_AR | ETH_ESDCMR_AT)); 472 } 473 474 sc->sc_pcr &= 475 ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 476 477 #if defined(DEBUG) 478 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 479 #endif 480 481 /* 482 * Now turn off the GT. If it didn't quiese, too ***ing bad. 483 */ 484 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 485 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 486 sdcr = GE_READ(sc, ETH_ESDCR); 487 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 488 sdcr |= ETH_ESDCR_RIFB; 489 GE_WRITE(sc, ETH_ESDCR, sdcr); 490 491 sc->sc_mii.mii_ifp = ifp; 492 sc->sc_mii.mii_readreg = gfec_mii_read; 493 sc->sc_mii.mii_writereg = gfec_mii_write; 494 sc->sc_mii.mii_statchg = gfec_mii_statchg; 495 496 sc->sc_ec.ec_mii = &sc->sc_mii; 497 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 498 ether_mediastatus); 499 500 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 501 MII_OFFSET_ANY, MIIF_NOISOLATE); 502 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 503 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 504 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 505 } else { 506 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 507 } 508 509 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 510 ifp->if_softc = sc; 511 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 512 #if 0 513 ifp->if_flags |= IFF_DEBUG; 514 #endif 515 ifp->if_ioctl = gfe_ifioctl; 516 ifp->if_start = gfe_ifstart; 517 ifp->if_watchdog = gfe_ifwatchdog; 518 519 if (sc->sc_flags & GE_NOFREE) { 520 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 521 if (!error) 522 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 523 if (!error) 524 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 525 if (!error) 526 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 527 if (!error) 528 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 529 if (!error) 530 error = gfe_hash_alloc(sc); 531 if (error) 532 aprint_error_dev(self, 533 "failed to allocate resources: %d\n", error); 534 } 535 536 if_attach(ifp); 537 ether_ifattach(ifp, enaddr); 538 bpf_attach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 539 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 540 0); 541 marvell_intr_establish(mva->mva_irq, IPL_NET, gfe_intr, sc); 542 } 543 544 int 545 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 546 size_t size, int flags) 547 { 548 int error = 0; 549 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 550 551 KASSERT(gdm->gdm_kva == NULL); 552 gdm->gdm_size = size; 553 gdm->gdm_maxsegs = maxsegs; 554 555 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 556 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 557 BUS_DMA_NOWAIT); 558 if (error) 559 goto fail; 560 561 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 562 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 563 if (error) 564 goto fail; 565 566 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 567 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 568 if (error) 569 goto fail; 570 571 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 572 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 573 if (error) 574 goto fail; 575 576 /* invalidate from cache */ 577 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 578 BUS_DMASYNC_PREREAD); 579 fail: 580 if (error) { 581 gfe_dmamem_free(sc, gdm); 582 GE_DPRINTF(sc, (":err=%d", error)); 583 } 584 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 585 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 586 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 587 GE_FUNC_EXIT(sc, ""); 588 return error; 589 } 590 591 void 592 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 593 { 594 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 595 if (gdm->gdm_map) 596 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 597 if (gdm->gdm_kva) 598 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 599 if (gdm->gdm_nsegs > 0) 600 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 601 gdm->gdm_map = NULL; 602 gdm->gdm_kva = NULL; 603 gdm->gdm_nsegs = 0; 604 GE_FUNC_EXIT(sc, ""); 605 } 606 607 int 608 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 609 { 610 struct gfe_softc * const sc = ifp->if_softc; 611 struct ifreq *ifr = (struct ifreq *) data; 612 struct ifaddr *ifa = (struct ifaddr *) data; 613 int s, error = 0; 614 615 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 616 s = splnet(); 617 618 switch (cmd) { 619 case SIOCINITIFADDR: 620 ifp->if_flags |= IFF_UP; 621 error = gfe_whack(sc, GE_WHACK_START); 622 switch (ifa->ifa_addr->sa_family) { 623 #ifdef INET 624 case AF_INET: 625 if (error == 0) 626 arp_ifinit(ifp, ifa); 627 break; 628 #endif 629 default: 630 break; 631 } 632 break; 633 634 case SIOCSIFFLAGS: 635 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 636 break; 637 /* XXX re-use ether_ioctl() */ 638 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 639 case IFF_UP|IFF_RUNNING:/* active->active, update */ 640 error = gfe_whack(sc, GE_WHACK_CHANGE); 641 break; 642 case IFF_RUNNING: /* not up, so we stop */ 643 error = gfe_whack(sc, GE_WHACK_STOP); 644 break; 645 case IFF_UP: /* not running, so we start */ 646 error = gfe_whack(sc, GE_WHACK_START); 647 break; 648 case 0: /* idle->idle: do nothing */ 649 break; 650 } 651 break; 652 653 case SIOCSIFMEDIA: 654 case SIOCGIFMEDIA: 655 case SIOCADDMULTI: 656 case SIOCDELMULTI: 657 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 658 if (ifp->if_flags & IFF_RUNNING) 659 error = gfe_whack(sc, GE_WHACK_CHANGE); 660 else 661 error = 0; 662 } 663 break; 664 665 case SIOCSIFMTU: 666 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 667 error = EINVAL; 668 break; 669 } 670 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 671 error = 0; 672 break; 673 674 default: 675 error = ether_ioctl(ifp, cmd, data); 676 break; 677 } 678 splx(s); 679 GE_FUNC_EXIT(sc, ""); 680 return error; 681 } 682 683 void 684 gfe_ifstart(struct ifnet *ifp) 685 { 686 struct gfe_softc * const sc = ifp->if_softc; 687 struct mbuf *m; 688 689 GE_FUNC_ENTER(sc, "gfe_ifstart"); 690 691 if ((ifp->if_flags & IFF_RUNNING) == 0) { 692 GE_FUNC_EXIT(sc, "$"); 693 return; 694 } 695 696 for (;;) { 697 IF_DEQUEUE(&ifp->if_snd, m); 698 if (m == NULL) { 699 ifp->if_flags &= ~IFF_OACTIVE; 700 GE_FUNC_EXIT(sc, ""); 701 return; 702 } 703 704 /* 705 * No space in the pending queue? try later. 706 */ 707 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 708 break; 709 710 /* 711 * Try to enqueue a mbuf to the device. If that fails, we 712 * can always try to map the next mbuf. 713 */ 714 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 715 GE_DPRINTF(sc, (">")); 716 #ifndef GE_NOTX 717 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 718 #endif 719 } 720 721 /* 722 * Attempt to queue the mbuf for send failed. 723 */ 724 IF_PREPEND(&ifp->if_snd, m); 725 ifp->if_flags |= IFF_OACTIVE; 726 GE_FUNC_EXIT(sc, "%%"); 727 } 728 729 void 730 gfe_ifwatchdog(struct ifnet *ifp) 731 { 732 struct gfe_softc * const sc = ifp->if_softc; 733 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 734 735 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 736 aprint_error_dev(sc->sc_dev, "device timeout"); 737 if (ifp->if_flags & IFF_RUNNING) { 738 uint32_t curtxdnum; 739 740 curtxdnum = (GE_READ(sc, txq->txq_ectdp) - 741 txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 742 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 743 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 744 aprint_error(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 745 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 746 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 747 GE_READ(sc, ETH_EICR)); 748 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 749 GE_TXDPRESYNC(sc, txq, curtxdnum); 750 } 751 aprint_error("\n"); 752 ifp->if_oerrors++; 753 (void) gfe_whack(sc, GE_WHACK_RESTART); 754 GE_FUNC_EXIT(sc, ""); 755 } 756 757 int 758 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 759 { 760 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 761 int error; 762 763 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 764 GE_DPRINTF(sc, ("(%d)", rxprio)); 765 766 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 767 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 768 if (error) { 769 GE_FUNC_EXIT(sc, "!!"); 770 return error; 771 } 772 773 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 774 GE_RXBUF_MEMSIZE, 0); 775 if (error) { 776 GE_FUNC_EXIT(sc, "!!!"); 777 return error; 778 } 779 GE_FUNC_EXIT(sc, ""); 780 return error; 781 } 782 783 int 784 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 785 { 786 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 787 volatile struct gt_eth_desc *rxd; 788 const bus_dma_segment_t *ds; 789 int idx; 790 bus_addr_t nxtaddr; 791 bus_size_t boff; 792 793 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 794 GE_DPRINTF(sc, ("(%d)", rxprio)); 795 796 if ((sc->sc_flags & GE_NOFREE) == 0) { 797 int error = gfe_rx_rxqalloc(sc, rxprio); 798 if (error) { 799 GE_FUNC_EXIT(sc, "!"); 800 return error; 801 } 802 } else { 803 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 804 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 805 } 806 807 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 808 809 rxq->rxq_descs = 810 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 811 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 812 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 813 rxq->rxq_fi = 0; 814 rxq->rxq_active = GE_RXDESC_MAX; 815 boff = 0; 816 ds = rxq->rxq_buf_mem.gdm_map->dm_segs; 817 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 818 for (idx = 0, rxd = rxq->rxq_descs; idx < GE_RXDESC_MAX; 819 idx++, nxtaddr += sizeof(*(++rxd))) { 820 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 821 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 822 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 823 /* 824 * update the nxtptr to point to the next txd. 825 */ 826 if (idx == GE_RXDESC_MAX - 1) 827 nxtaddr = rxq->rxq_desc_busaddr; 828 rxd->ed_nxtptr = htogt32(nxtaddr); 829 boff += GE_RXBUF_SIZE; 830 if (boff == ds->ds_len) { 831 ds++; 832 boff = 0; 833 } 834 } 835 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 836 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 837 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 838 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 839 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 840 BUS_DMASYNC_PREREAD); 841 842 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 843 switch (rxprio) { 844 case GE_RXPRIO_HI: 845 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 846 rxq->rxq_efrdp = ETH_EFRDP3; 847 rxq->rxq_ecrdp = ETH_ECRDP3; 848 break; 849 case GE_RXPRIO_MEDHI: 850 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 851 rxq->rxq_efrdp = ETH_EFRDP2; 852 rxq->rxq_ecrdp = ETH_ECRDP2; 853 break; 854 case GE_RXPRIO_MEDLO: 855 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 856 rxq->rxq_efrdp = ETH_EFRDP1; 857 rxq->rxq_ecrdp = ETH_ECRDP1; 858 break; 859 case GE_RXPRIO_LO: 860 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 861 rxq->rxq_efrdp = ETH_EFRDP0; 862 rxq->rxq_ecrdp = ETH_ECRDP0; 863 break; 864 } 865 GE_FUNC_EXIT(sc, ""); 866 return 0; 867 } 868 869 void 870 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 871 { 872 struct ifnet * const ifp = &sc->sc_ec.ec_if; 873 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 874 struct mbuf *m = rxq->rxq_curpkt; 875 876 GE_FUNC_ENTER(sc, "gfe_rx_get"); 877 GE_DPRINTF(sc, ("(%d)", rxprio)); 878 879 while (rxq->rxq_active > 0) { 880 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 881 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 882 const struct ether_header *eh; 883 unsigned int cmdsts; 884 size_t buflen; 885 886 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 887 cmdsts = gt32toh(rxd->ed_cmdsts); 888 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 889 rxq->rxq_cmdsts = cmdsts; 890 /* 891 * Sometimes the GE "forgets" to reset the ownership bit. 892 * But if the length has been rewritten, the packet is ours 893 * so pretend the O bit is set. 894 */ 895 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 896 if ((cmdsts & RX_CMD_O) && buflen == 0) { 897 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 898 break; 899 } 900 901 /* 902 * If this is not a single buffer packet with no errors 903 * or for some reason it's bigger than our frame size, 904 * ignore it and go to the next packet. 905 */ 906 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 907 (RX_CMD_F|RX_CMD_L) || 908 buflen > sc->sc_max_frame_length) { 909 GE_DPRINTF(sc, ("!")); 910 --rxq->rxq_active; 911 ifp->if_ipackets++; 912 ifp->if_ierrors++; 913 goto give_it_back; 914 } 915 916 /* CRC is included with the packet; trim it off. */ 917 buflen -= ETHER_CRC_LEN; 918 919 if (m == NULL) { 920 MGETHDR(m, M_DONTWAIT, MT_DATA); 921 if (m == NULL) { 922 GE_DPRINTF(sc, ("?")); 923 break; 924 } 925 } 926 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 927 MCLGET(m, M_DONTWAIT); 928 if ((m->m_flags & M_EXT) == 0) { 929 GE_DPRINTF(sc, ("?")); 930 break; 931 } 932 } 933 m->m_data += 2; 934 m->m_len = 0; 935 m->m_pkthdr.len = 0; 936 m->m_pkthdr.rcvif = ifp; 937 rxq->rxq_cmdsts = cmdsts; 938 --rxq->rxq_active; 939 940 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 941 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 942 943 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 944 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 945 m->m_len = buflen; 946 m->m_pkthdr.len = buflen; 947 948 ifp->if_ipackets++; 949 bpf_mtap(ifp, m); 950 951 eh = (const struct ether_header *) m->m_data; 952 if ((ifp->if_flags & IFF_PROMISC) || 953 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 954 (rxq->rxq_cmdsts & RX_STS_HE) || 955 (eh->ether_dhost[0] & 1) != 0 || 956 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 957 ETHER_ADDR_LEN) == 0) { 958 (*ifp->if_input)(ifp, m); 959 m = NULL; 960 GE_DPRINTF(sc, (">")); 961 } else { 962 m->m_len = 0; 963 m->m_pkthdr.len = 0; 964 GE_DPRINTF(sc, ("+")); 965 } 966 rxq->rxq_cmdsts = 0; 967 968 give_it_back: 969 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 970 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 971 #if 0 972 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 973 rxq->rxq_fi, 974 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 975 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 976 #endif 977 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 978 if (++rxq->rxq_fi == GE_RXDESC_MAX) 979 rxq->rxq_fi = 0; 980 rxq->rxq_active++; 981 } 982 rxq->rxq_curpkt = m; 983 GE_FUNC_EXIT(sc, ""); 984 } 985 986 uint32_t 987 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 988 { 989 struct ifnet * const ifp = &sc->sc_ec.ec_if; 990 struct gfe_rxqueue *rxq; 991 uint32_t rxbits; 992 #define RXPRIO_DECODER 0xffffaa50 993 GE_FUNC_ENTER(sc, "gfe_rx_process"); 994 995 rxbits = ETH_IR_RxBuffer_GET(cause); 996 while (rxbits) { 997 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 998 GE_DPRINTF(sc, ("%1x", rxbits)); 999 rxbits &= ~(1 << rxprio); 1000 gfe_rx_get(sc, rxprio); 1001 } 1002 1003 rxbits = ETH_IR_RxError_GET(cause); 1004 while (rxbits) { 1005 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 1006 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 1007 int idx; 1008 rxbits &= ~(1 << rxprio); 1009 rxq = &sc->sc_rxq[rxprio]; 1010 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 1011 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 1012 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 1013 sc->sc_tickflags |= GE_TICK_RX_RESTART; 1014 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 1015 } 1016 ifp->if_ierrors++; 1017 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 1018 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi)); 1019 memset(masks, 0, sizeof(masks)); 1020 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1021 0, rxq->rxq_desc_mem.gdm_size, 1022 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1023 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 1024 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 1025 1026 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 1027 masks[idx/32] |= 1 << (idx & 31); 1028 } 1029 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1030 0, rxq->rxq_desc_mem.gdm_size, 1031 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1032 #if defined(DEBUG) 1033 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 1034 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi, 1035 rxq->rxq_cmdsts, masks[0], masks[1]); 1036 #endif 1037 } 1038 if ((intrmask & ETH_IR_RxBits) == 0) 1039 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 1040 1041 GE_FUNC_EXIT(sc, ""); 1042 return intrmask; 1043 } 1044 1045 int 1046 gfe_rx_prime(struct gfe_softc *sc) 1047 { 1048 struct gfe_rxqueue *rxq; 1049 int error; 1050 1051 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 1052 1053 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 1054 if (error) 1055 goto bail; 1056 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1057 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1058 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1059 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1060 } 1061 sc->sc_intrmask |= rxq->rxq_intrbits; 1062 1063 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 1064 if (error) 1065 goto bail; 1066 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1067 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1068 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1069 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1070 sc->sc_intrmask |= rxq->rxq_intrbits; 1071 } 1072 1073 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 1074 if (error) 1075 goto bail; 1076 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1077 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1078 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1079 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1080 sc->sc_intrmask |= rxq->rxq_intrbits; 1081 } 1082 1083 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 1084 if (error) 1085 goto bail; 1086 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1087 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1088 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1089 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1090 sc->sc_intrmask |= rxq->rxq_intrbits; 1091 } 1092 1093 bail: 1094 GE_FUNC_EXIT(sc, ""); 1095 return error; 1096 } 1097 1098 void 1099 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 1100 { 1101 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 1102 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 1103 if (rxq == NULL) { 1104 GE_FUNC_EXIT(sc, ""); 1105 return; 1106 } 1107 1108 if (rxq->rxq_curpkt) 1109 m_freem(rxq->rxq_curpkt); 1110 if ((sc->sc_flags & GE_NOFREE) == 0) { 1111 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 1112 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 1113 } 1114 GE_FUNC_EXIT(sc, ""); 1115 } 1116 1117 void 1118 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1119 { 1120 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 1121 sc->sc_flags &= ~GE_RXACTIVE; 1122 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 1123 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 1124 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1125 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR); 1126 do { 1127 delay(10); 1128 } while (GE_READ(sc, ETH_ESDCMR) & ETH_ESDCMR_AR); 1129 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 1130 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 1131 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 1132 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 1133 GE_FUNC_EXIT(sc, ""); 1134 } 1135 1136 void 1137 gfe_tick(void *arg) 1138 { 1139 struct gfe_softc * const sc = arg; 1140 uint32_t intrmask; 1141 unsigned int tickflags; 1142 int s; 1143 1144 GE_FUNC_ENTER(sc, "gfe_tick"); 1145 1146 s = splnet(); 1147 1148 tickflags = sc->sc_tickflags; 1149 sc->sc_tickflags = 0; 1150 intrmask = sc->sc_intrmask; 1151 if (tickflags & GE_TICK_TX_IFSTART) 1152 gfe_ifstart(&sc->sc_ec.ec_if); 1153 if (tickflags & GE_TICK_RX_RESTART) { 1154 intrmask |= sc->sc_idlemask; 1155 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 1156 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1157 rxq->rxq_fi = 0; 1158 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1159 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1160 } 1161 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 1162 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1163 rxq->rxq_fi = 0; 1164 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1165 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1166 } 1167 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 1168 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1169 rxq->rxq_fi = 0; 1170 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1171 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1172 } 1173 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 1174 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1175 rxq->rxq_fi = 0; 1176 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1177 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1178 } 1179 sc->sc_idlemask = 0; 1180 } 1181 if (intrmask != sc->sc_intrmask) { 1182 sc->sc_intrmask = intrmask; 1183 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1184 } 1185 gfe_intr(sc); 1186 splx(s); 1187 1188 GE_FUNC_EXIT(sc, ""); 1189 } 1190 1191 int 1192 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1193 { 1194 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1195 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1196 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1197 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1198 uint32_t intrmask = sc->sc_intrmask; 1199 size_t buflen; 1200 struct mbuf *m; 1201 1202 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1203 1204 /* 1205 * Anything in the pending queue to enqueue? if not, punt. Likewise 1206 * if the txq is not yet created. 1207 * otherwise grab its dmamap. 1208 */ 1209 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1210 GE_FUNC_EXIT(sc, "-"); 1211 return 0; 1212 } 1213 1214 /* 1215 * Have we [over]consumed our limit of descriptors? 1216 * Do we have enough free descriptors? 1217 */ 1218 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1219 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1220 uint32_t cmdsts; 1221 size_t pktlen; 1222 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1223 cmdsts = gt32toh(txd2->ed_cmdsts); 1224 if (cmdsts & TX_CMD_O) { 1225 int nextin; 1226 /* 1227 * Sometime the Discovery forgets to update the 1228 * last descriptor. See if we own the descriptor 1229 * after it (since we know we've turned that to 1230 * the discovery and if we owned it, the Discovery 1231 * gave it back). If we do, we know the Discovery 1232 * gave back this one but forgot to mark it as ours. 1233 */ 1234 nextin = txq->txq_fi + 1; 1235 if (nextin == GE_TXDESC_MAX) 1236 nextin = 0; 1237 GE_TXDPOSTSYNC(sc, txq, nextin); 1238 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1239 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1240 GE_TXDPRESYNC(sc, txq, nextin); 1241 GE_FUNC_EXIT(sc, "@"); 1242 return 0; 1243 } 1244 #ifdef DEBUG 1245 printf("%s: txenqueue: transmitter resynced at %d\n", 1246 device_xname(sc->sc_dev), txq->txq_fi); 1247 #endif 1248 } 1249 if (++txq->txq_fi == GE_TXDESC_MAX) 1250 txq->txq_fi = 0; 1251 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1252 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1253 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1254 txq->txq_nactive--; 1255 1256 /* statistics */ 1257 ifp->if_opackets++; 1258 if (cmdsts & TX_STS_ES) 1259 ifp->if_oerrors++; 1260 GE_DPRINTF(sc, ("%%")); 1261 } 1262 1263 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1264 1265 /* 1266 * If this packet would wrap around the end of the buffer, reset back 1267 * to the beginning. 1268 */ 1269 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1270 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1271 txq->txq_outptr = 0; 1272 } 1273 1274 /* 1275 * Make sure the output packet doesn't run over the beginning of 1276 * what we've already given the GT. 1277 */ 1278 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1279 txq->txq_outptr + buflen > txq->txq_inptr) { 1280 intrmask |= txq->txq_intrbits & 1281 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1282 if (sc->sc_intrmask != intrmask) { 1283 sc->sc_intrmask = intrmask; 1284 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1285 } 1286 GE_FUNC_EXIT(sc, "#"); 1287 return 0; 1288 } 1289 1290 /* 1291 * The end-of-list descriptor we put on last time is the starting point 1292 * for this packet. The GT is supposed to terminate list processing on 1293 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1294 * must terminate the list. 1295 */ 1296 intrmask = sc->sc_intrmask; 1297 1298 m_copydata(m, 0, m->m_pkthdr.len, 1299 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1300 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1301 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1302 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1303 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1304 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1305 1306 /* 1307 * Request a buffer interrupt every 2/3 of the way thru the transmit 1308 * buffer. 1309 */ 1310 txq->txq_ei_gapcount += buflen; 1311 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1312 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1313 txq->txq_ei_gapcount = 0; 1314 } else { 1315 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1316 } 1317 #if 0 1318 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1319 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1320 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1321 #endif 1322 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1323 1324 txq->txq_outptr += buflen; 1325 /* 1326 * Tell the SDMA engine to "Fetch!" 1327 */ 1328 GE_WRITE(sc, ETH_ESDCMR, 1329 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1330 1331 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1332 1333 /* 1334 * Update the last out appropriately. 1335 */ 1336 txq->txq_nactive++; 1337 if (++txq->txq_lo == GE_TXDESC_MAX) 1338 txq->txq_lo = 0; 1339 1340 /* 1341 * Move mbuf from the pending queue to the snd queue. 1342 */ 1343 IF_DEQUEUE(&txq->txq_pendq, m); 1344 bpf_mtap(ifp, m); 1345 m_freem(m); 1346 ifp->if_flags &= ~IFF_OACTIVE; 1347 1348 /* 1349 * Since we have put an item into the packet queue, we now want 1350 * an interrupt when the transmit queue finishes processing the 1351 * list. But only update the mask if needs changing. 1352 */ 1353 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1354 if (sc->sc_intrmask != intrmask) { 1355 sc->sc_intrmask = intrmask; 1356 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1357 } 1358 if (ifp->if_timer == 0) 1359 ifp->if_timer = 5; 1360 GE_FUNC_EXIT(sc, "*"); 1361 return 1; 1362 } 1363 1364 uint32_t 1365 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1366 { 1367 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1368 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1369 1370 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1371 1372 if (txq == NULL) { 1373 GE_FUNC_EXIT(sc, ""); 1374 return intrmask; 1375 } 1376 1377 while (txq->txq_nactive > 0) { 1378 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1379 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1380 uint32_t cmdsts; 1381 size_t pktlen; 1382 1383 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1384 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1385 int nextin; 1386 1387 if (txq->txq_nactive == 1) { 1388 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1389 GE_FUNC_EXIT(sc, ""); 1390 return intrmask; 1391 } 1392 /* 1393 * Sometimes the Discovery forgets to update the 1394 * ownership bit in the descriptor. See if we own the 1395 * descriptor after it (since we know we've turned 1396 * that to the Discovery and if we own it now then the 1397 * Discovery gave it back). If we do, we know the 1398 * Discovery gave back this one but forgot to mark it 1399 * as ours. 1400 */ 1401 nextin = txq->txq_fi + 1; 1402 if (nextin == GE_TXDESC_MAX) 1403 nextin = 0; 1404 GE_TXDPOSTSYNC(sc, txq, nextin); 1405 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1406 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1407 GE_TXDPRESYNC(sc, txq, nextin); 1408 GE_FUNC_EXIT(sc, ""); 1409 return intrmask; 1410 } 1411 #ifdef DEBUG 1412 printf("%s: txdone: transmitter resynced at %d\n", 1413 device_xname(sc->sc_dev), txq->txq_fi); 1414 #endif 1415 } 1416 #if 0 1417 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1418 txq->txq_lo, 1419 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1420 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1421 #endif 1422 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1423 if (++txq->txq_fi == GE_TXDESC_MAX) 1424 txq->txq_fi = 0; 1425 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1426 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1427 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1428 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1429 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1430 1431 /* statistics */ 1432 ifp->if_opackets++; 1433 if (cmdsts & TX_STS_ES) 1434 ifp->if_oerrors++; 1435 1436 /* txd->ed_bufptr = 0; */ 1437 1438 ifp->if_timer = 5; 1439 --txq->txq_nactive; 1440 } 1441 if (txq->txq_nactive != 0) 1442 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1443 device_xname(sc->sc_dev), txprio, txq->txq_nactive); 1444 ifp->if_timer = 0; 1445 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1446 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1447 GE_FUNC_EXIT(sc, ""); 1448 return intrmask; 1449 } 1450 1451 int 1452 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1453 { 1454 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1455 int error; 1456 1457 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1458 1459 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1460 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1461 if (error) { 1462 GE_FUNC_EXIT(sc, ""); 1463 return error; 1464 } 1465 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1466 if (error) { 1467 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1468 GE_FUNC_EXIT(sc, ""); 1469 return error; 1470 } 1471 GE_FUNC_EXIT(sc, ""); 1472 return 0; 1473 } 1474 1475 int 1476 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1477 { 1478 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1479 volatile struct gt_eth_desc *txd; 1480 unsigned int i; 1481 bus_addr_t addr; 1482 1483 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1484 1485 sc->sc_intrmask &= 1486 ~(ETH_IR_TxEndHigh | 1487 ETH_IR_TxBufferHigh | 1488 ETH_IR_TxEndLow | 1489 ETH_IR_TxBufferLow); 1490 1491 if (sc->sc_flags & GE_NOFREE) { 1492 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1493 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1494 } else { 1495 int error = gfe_tx_txqalloc(sc, txprio); 1496 if (error) { 1497 GE_FUNC_EXIT(sc, "!"); 1498 return error; 1499 } 1500 } 1501 1502 txq->txq_descs = 1503 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1504 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1505 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1506 1507 txq->txq_pendq.ifq_maxlen = 10; 1508 txq->txq_ei_gapcount = 0; 1509 txq->txq_nactive = 0; 1510 txq->txq_fi = 0; 1511 txq->txq_lo = 0; 1512 txq->txq_inptr = GE_TXBUF_SIZE; 1513 txq->txq_outptr = 0; 1514 for (i = 0, txd = txq->txq_descs, 1515 addr = txq->txq_desc_busaddr + sizeof(*txd); 1516 i < GE_TXDESC_MAX - 1; i++, txd++, addr += sizeof(*txd)) { 1517 /* 1518 * update the nxtptr to point to the next txd. 1519 */ 1520 txd->ed_cmdsts = 0; 1521 txd->ed_nxtptr = htogt32(addr); 1522 } 1523 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1524 htogt32(txq->txq_desc_busaddr); 1525 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1526 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1527 1528 switch (txprio) { 1529 case GE_TXPRIO_HI: 1530 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1531 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1532 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1533 txq->txq_ectdp = ETH_ECTDP1; 1534 GE_WRITE(sc, ETH_ECTDP1, txq->txq_desc_busaddr); 1535 break; 1536 1537 case GE_TXPRIO_LO: 1538 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1539 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1540 txq->txq_epsrbits = ETH_EPSR_TxLow; 1541 txq->txq_ectdp = ETH_ECTDP0; 1542 GE_WRITE(sc, ETH_ECTDP0, txq->txq_desc_busaddr); 1543 break; 1544 1545 case GE_TXPRIO_NONE: 1546 break; 1547 } 1548 #if 0 1549 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1550 GE_WRITE(sc->sc_dev, txq->txq_ectdp, txq->txq_desc_busaddr); 1551 GE_DPRINTF(sc, (")")); 1552 #endif 1553 1554 /* 1555 * If we are restarting, there may be packets in the pending queue 1556 * waiting to be enqueued. Try enqueuing packets from both priority 1557 * queues until the pending queue is empty or there no room for them 1558 * on the device. 1559 */ 1560 while (gfe_tx_enqueue(sc, txprio)) 1561 continue; 1562 1563 GE_FUNC_EXIT(sc, ""); 1564 return 0; 1565 } 1566 1567 void 1568 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1569 { 1570 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1571 1572 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1573 if (txq == NULL) { 1574 GE_FUNC_EXIT(sc, ""); 1575 return; 1576 } 1577 1578 if (!flush) { 1579 GE_FUNC_EXIT(sc, ""); 1580 return; 1581 } 1582 1583 if ((sc->sc_flags & GE_NOFREE) == 0) { 1584 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1585 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1586 } 1587 GE_FUNC_EXIT(sc, "-F"); 1588 } 1589 1590 void 1591 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1592 { 1593 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1594 1595 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1596 1597 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1598 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1599 sc->sc_intrmask &= 1600 ~(ETH_IR_TxEndHigh | 1601 ETH_IR_TxBufferHigh | 1602 ETH_IR_TxEndLow | 1603 ETH_IR_TxBufferLow); 1604 1605 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1606 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1607 1608 sc->sc_ec.ec_if.if_timer = 0; 1609 GE_FUNC_EXIT(sc, ""); 1610 } 1611 1612 int 1613 gfe_intr(void *arg) 1614 { 1615 struct gfe_softc * const sc = arg; 1616 uint32_t cause; 1617 uint32_t intrmask = sc->sc_intrmask; 1618 int claim = 0; 1619 int cnt; 1620 1621 GE_FUNC_ENTER(sc, "gfe_intr"); 1622 1623 for (cnt = 0; cnt < 4; cnt++) { 1624 if (sc->sc_intrmask != intrmask) { 1625 sc->sc_intrmask = intrmask; 1626 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1627 } 1628 cause = GE_READ(sc, ETH_EICR); 1629 cause &= sc->sc_intrmask; 1630 GE_DPRINTF(sc, (".%#x", cause)); 1631 if (cause == 0) 1632 break; 1633 1634 claim = 1; 1635 1636 GE_WRITE(sc, ETH_EICR, ~cause); 1637 #ifndef GE_NORX 1638 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1639 intrmask = gfe_rx_process(sc, cause, intrmask); 1640 #endif 1641 1642 #ifndef GE_NOTX 1643 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1644 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1645 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1646 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1647 #endif 1648 if (cause & ETH_IR_MIIPhySTC) { 1649 sc->sc_flags |= GE_PHYSTSCHG; 1650 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1651 } 1652 } 1653 1654 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1655 continue; 1656 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1657 continue; 1658 1659 GE_FUNC_EXIT(sc, ""); 1660 return claim; 1661 } 1662 1663 int 1664 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1665 { 1666 int error = 0; 1667 GE_FUNC_ENTER(sc, "gfe_whack"); 1668 1669 switch (op) { 1670 case GE_WHACK_RESTART: 1671 #ifndef GE_NOTX 1672 gfe_tx_stop(sc, op); 1673 #endif 1674 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1675 /* FALLTHROUGH */ 1676 case GE_WHACK_START: 1677 #ifndef GE_NOHASH 1678 if (error == 0 && sc->sc_hashtable == NULL) { 1679 error = gfe_hash_alloc(sc); 1680 if (error) 1681 break; 1682 } 1683 if (op != GE_WHACK_RESTART) 1684 gfe_hash_fill(sc); 1685 #endif 1686 #ifndef GE_NORX 1687 if (op != GE_WHACK_RESTART) { 1688 error = gfe_rx_prime(sc); 1689 if (error) 1690 break; 1691 } 1692 #endif 1693 #ifndef GE_NOTX 1694 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1695 if (error) 1696 break; 1697 #endif 1698 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1699 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1700 GE_WRITE(sc, ETH_EPCXR, sc->sc_pcxr); 1701 GE_WRITE(sc, ETH_EICR, 0); 1702 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1703 #ifndef GE_NOHASH 1704 GE_WRITE(sc, ETH_EHTPR, 1705 sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1706 #endif 1707 #ifndef GE_NORX 1708 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_ERD); 1709 sc->sc_flags |= GE_RXACTIVE; 1710 #endif 1711 /* FALLTHROUGH */ 1712 case GE_WHACK_CHANGE: 1713 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1714 GE_READ(sc, ETH_EPCR), GE_READ(sc, ETH_EIMR))); 1715 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1716 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1717 gfe_ifstart(&sc->sc_ec.ec_if); 1718 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1719 GE_READ(sc, ETH_ECTDP0), GE_READ(sc, ETH_ECTDP1))); 1720 GE_FUNC_EXIT(sc, ""); 1721 return error; 1722 case GE_WHACK_STOP: 1723 break; 1724 } 1725 1726 #ifdef GE_DEBUG 1727 if (error) 1728 GE_DPRINTF(sc, (" failed: %d\n", error)); 1729 #endif 1730 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1731 GE_WRITE(sc, ETH_EIMR, 0); 1732 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1733 #ifndef GE_NOTX 1734 gfe_tx_stop(sc, GE_WHACK_STOP); 1735 #endif 1736 #ifndef GE_NORX 1737 gfe_rx_stop(sc, GE_WHACK_STOP); 1738 #endif 1739 #ifndef GE_NOHASH 1740 if ((sc->sc_flags & GE_NOFREE) == 0) { 1741 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1742 sc->sc_hashtable = NULL; 1743 } 1744 #endif 1745 1746 GE_FUNC_EXIT(sc, ""); 1747 return error; 1748 } 1749 1750 int 1751 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1752 { 1753 uint32_t w0, add0, add1; 1754 uint32_t result; 1755 1756 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1757 add0 = ((uint32_t) eaddr[5] << 0) | 1758 ((uint32_t) eaddr[4] << 8) | 1759 ((uint32_t) eaddr[3] << 16); 1760 1761 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1762 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1763 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1764 1765 add1 = ((uint32_t) eaddr[2] << 0) | 1766 ((uint32_t) eaddr[1] << 8) | 1767 ((uint32_t) eaddr[0] << 16); 1768 1769 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1770 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1771 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1772 1773 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1774 /* 1775 * hashResult is the 15 bits Hash entry address. 1776 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1777 * MAC address, by nibble swapping in every byte (i.e MAC address 1778 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1779 */ 1780 1781 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1782 /* 1783 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1784 * 1785 * hashFunc0 calculates the hashResult in the following manner: 1786 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1787 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1788 */ 1789 result = (add0 & 3) | ((add0 >> 6) & ~3); 1790 result ^= (add0 >> 15) ^ (add1 >> 0); 1791 result &= 0x1ff; 1792 /* 1793 * hashResult[14:9] = ethernetADD[7:2] 1794 */ 1795 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1796 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1797 } else { 1798 #define TRIBITFLIP 073516240 /* yes its in octal */ 1799 /* 1800 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1801 * 1802 * hashFunc1 calculates the hashResult in the following manner: 1803 * hashResult[08:00] = ethernetADD[06:14] 1804 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1805 */ 1806 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1807 /* 1808 * Now bitswap those 9 bits 1809 */ 1810 result = 0; 1811 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1812 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1813 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1814 1815 /* 1816 * hashResult[14:09] = ethernetADD[00:05] 1817 */ 1818 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1819 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1820 GE_DPRINTF(sc, ("1(%#x)", result)); 1821 } 1822 GE_FUNC_EXIT(sc, ""); 1823 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1824 } 1825 1826 int 1827 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1828 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1829 { 1830 uint64_t he; 1831 uint64_t *maybe_he_p = NULL; 1832 int limit; 1833 int hash; 1834 int maybe_hash = 0; 1835 1836 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1837 1838 hash = gfe_hash_compute(sc, eaddr); 1839 1840 if (sc->sc_hashtable == NULL) { 1841 panic("%s:%d: hashtable == NULL!", device_xname(sc->sc_dev), 1842 __LINE__); 1843 } 1844 1845 /* 1846 * Assume we are going to insert so create the hash entry we 1847 * are going to insert. We also use it to match entries we 1848 * will be removing. 1849 */ 1850 he = ((uint64_t) eaddr[5] << 43) | 1851 ((uint64_t) eaddr[4] << 35) | 1852 ((uint64_t) eaddr[3] << 27) | 1853 ((uint64_t) eaddr[2] << 19) | 1854 ((uint64_t) eaddr[1] << 11) | 1855 ((uint64_t) eaddr[0] << 3) | 1856 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1857 1858 /* 1859 * The GT will search upto 12 entries for a hit, so we must mimic that. 1860 */ 1861 hash &= sc->sc_hashmask / sizeof(he); 1862 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1863 /* 1864 * Does the GT wrap at the end, stop at the, or overrun the 1865 * end? Assume it wraps for now. Stash a copy of the 1866 * current hash entry. 1867 */ 1868 uint64_t *he_p = &sc->sc_hashtable[hash]; 1869 uint64_t thishe = *he_p; 1870 1871 /* 1872 * If the hash entry isn't valid, that break the chain. And 1873 * this entry a good candidate for reuse. 1874 */ 1875 if ((thishe & HSH_V) == 0) { 1876 maybe_he_p = he_p; 1877 break; 1878 } 1879 1880 /* 1881 * If the hash entry has the same address we are looking for 1882 * then ... if we are removing and the skip bit is set, its 1883 * already been removed. if are adding and the skip bit is 1884 * clear, then its already added. In either return EBUSY 1885 * indicating the op has already been done. Otherwise flip 1886 * the skip bit and return 0. 1887 */ 1888 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1889 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1890 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1891 return EBUSY; 1892 *he_p = thishe ^ HSH_S; 1893 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1894 hash * sizeof(he), sizeof(he), 1895 BUS_DMASYNC_PREWRITE); 1896 GE_FUNC_EXIT(sc, "^"); 1897 return 0; 1898 } 1899 1900 /* 1901 * If we haven't found a slot for the entry and this entry 1902 * is currently being skipped, return this entry. 1903 */ 1904 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1905 maybe_he_p = he_p; 1906 maybe_hash = hash; 1907 } 1908 1909 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1910 } 1911 1912 /* 1913 * If we got here, then there was no entry to remove. 1914 */ 1915 if (op == GE_HASH_REMOVE) { 1916 GE_FUNC_EXIT(sc, "?"); 1917 return ENOENT; 1918 } 1919 1920 /* 1921 * If we couldn't find a slot, return an error. 1922 */ 1923 if (maybe_he_p == NULL) { 1924 GE_FUNC_EXIT(sc, "!"); 1925 return ENOSPC; 1926 } 1927 1928 /* Update the entry. 1929 */ 1930 *maybe_he_p = he; 1931 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1932 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1933 GE_FUNC_EXIT(sc, "+"); 1934 return 0; 1935 } 1936 1937 int 1938 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, 1939 u_long cmd) 1940 { 1941 struct gfe_softc *sc = ec->ec_if.if_softc; 1942 int error; 1943 enum gfe_hash_op op; 1944 enum gfe_rxprio prio; 1945 1946 GE_FUNC_ENTER(sc, "hash_multichg"); 1947 /* 1948 * Is this a wildcard entry? If so and its being removed, recompute. 1949 */ 1950 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1951 if (cmd == SIOCDELMULTI) { 1952 GE_FUNC_EXIT(sc, ""); 1953 return ENETRESET; 1954 } 1955 1956 /* 1957 * Switch in 1958 */ 1959 sc->sc_flags |= GE_ALLMULTI; 1960 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1961 sc->sc_pcr |= ETH_EPCR_PM; 1962 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1963 GE_FUNC_EXIT(sc, ""); 1964 return 0; 1965 } 1966 GE_FUNC_EXIT(sc, ""); 1967 return ENETRESET; 1968 } 1969 1970 prio = GE_RXPRIO_MEDLO; 1971 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1972 1973 if (sc->sc_hashtable == NULL) { 1974 GE_FUNC_EXIT(sc, ""); 1975 return 0; 1976 } 1977 1978 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1979 if (error == EBUSY) { 1980 aprint_error_dev(sc->sc_dev, "multichg: tried to %s %s again\n", 1981 cmd == SIOCDELMULTI ? "remove" : "add", 1982 ether_sprintf(enm->enm_addrlo)); 1983 GE_FUNC_EXIT(sc, ""); 1984 return 0; 1985 } 1986 1987 if (error == ENOENT) { 1988 aprint_error_dev(sc->sc_dev, 1989 "multichg: failed to remove %s: not in table\n", 1990 ether_sprintf(enm->enm_addrlo)); 1991 GE_FUNC_EXIT(sc, ""); 1992 return 0; 1993 } 1994 1995 if (error == ENOSPC) { 1996 aprint_error_dev(sc->sc_dev, "multichg:" 1997 " failed to add %s: no space; regenerating table\n", 1998 ether_sprintf(enm->enm_addrlo)); 1999 GE_FUNC_EXIT(sc, ""); 2000 return ENETRESET; 2001 } 2002 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 2003 device_xname(sc->sc_dev), 2004 cmd == SIOCDELMULTI ? "remove" : "add", 2005 ether_sprintf(enm->enm_addrlo))); 2006 GE_FUNC_EXIT(sc, ""); 2007 return 0; 2008 } 2009 2010 int 2011 gfe_hash_fill(struct gfe_softc *sc) 2012 { 2013 struct ether_multistep step; 2014 struct ether_multi *enm; 2015 int error; 2016 2017 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 2018 2019 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 2020 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 2021 if (error) 2022 GE_FUNC_EXIT(sc, "!"); 2023 return error; 2024 2025 sc->sc_flags &= ~GE_ALLMULTI; 2026 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 2027 sc->sc_pcr &= ~ETH_EPCR_PM; 2028 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 2029 while (enm != NULL) { 2030 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2031 sc->sc_flags |= GE_ALLMULTI; 2032 sc->sc_pcr |= ETH_EPCR_PM; 2033 } else { 2034 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 2035 GE_RXPRIO_MEDLO, enm->enm_addrlo); 2036 if (error == ENOSPC) 2037 break; 2038 } 2039 ETHER_NEXT_MULTI(step, enm); 2040 } 2041 2042 GE_FUNC_EXIT(sc, ""); 2043 return error; 2044 } 2045 2046 int 2047 gfe_hash_alloc(struct gfe_softc *sc) 2048 { 2049 int error; 2050 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 2051 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 2052 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 2053 BUS_DMA_NOCACHE); 2054 if (error) { 2055 aprint_error_dev(sc->sc_dev, 2056 "failed to allocate %d bytes for hash table: %d\n", 2057 sc->sc_hashmask + 1, error); 2058 GE_FUNC_EXIT(sc, ""); 2059 return error; 2060 } 2061 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 2062 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 2063 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 2064 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 2065 GE_FUNC_EXIT(sc, ""); 2066 return 0; 2067 } 2068