1 /* $NetBSD: gtpci.c,v 1.7 2003/04/04 20:09:07 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include "opt_marvell.h" 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/extent.h> 44 #include <sys/malloc.h> 45 #include <lib/libkern/libkern.h> 46 47 #define _BUS_SPACE_PRIVATE 48 #define _BUS_DMA_PRIVATE 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pciconf.h> 55 #include <dev/marvell/gtreg.h> 56 #include <dev/marvell/gtvar.h> 57 #include <dev/marvell/gtintrreg.h> 58 #include <dev/marvell/gtpcireg.h> 59 #include <dev/marvell/gtpcivar.h> 60 #include <dev/marvell/gtvar.h> 61 62 static int gtpci_error_intr(void *); 63 64 static void gtpci_bus_init(struct gtpci_chipset *); 65 66 static void gtpci_bus_attach_hook(struct device *, struct device *, 67 struct pcibus_attach_args *); 68 static int gtpci_bus_maxdevs(pci_chipset_tag_t, int); 69 70 static const char * 71 gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); 72 static const struct evcnt * 73 gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t); 74 static void *gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 75 int, int (*)(void *), void *); 76 static void gtpci_intr_disestablish(pci_chipset_tag_t, void *); 77 78 #ifdef DEBUG 79 int gtpci_debug = 0; 80 #endif 81 82 struct gtpci_softc { 83 struct device gtpci_dev; 84 struct gtpci_chipset gtpci_gtpc; 85 }; 86 87 static int gtpci_cfprint(void *, const char *); 88 static int gtpci_match(struct device *, struct cfdata *, void *); 89 static void gtpci_attach(struct device *, struct device *, void *); 90 91 CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc), 92 gtpci_match, gtpci_attach, NULL, NULL); 93 94 extern struct cfdriver gtpci_cd; 95 96 const struct pci_chipset_functions gtpci_functions = { 97 gtpci_bus_attach_hook, 98 gtpci_bus_maxdevs, 99 gtpci_md_bus_devorder, 100 101 gtpci_make_tag, 102 gtpci_decompose_tag, 103 104 gtpci_conf_read, 105 gtpci_conf_write, 106 gtpci_md_conf_hook, 107 gtpci_md_conf_interrupt, 108 109 gtpci_md_intr_map, 110 gtpci_intr_string, 111 gtpci_intr_evcnt, 112 gtpci_intr_establish, 113 gtpci_intr_disestablish 114 }; 115 116 static const int pci_irqs[2][3] = { 117 { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 }, 118 { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 }, 119 }; 120 121 static const struct pci_init { 122 int bar_regno; 123 u_int32_t bar_enable; 124 bus_addr_t low_decode; 125 bus_addr_t high_decode; 126 bus_addr_t barsize; 127 bus_addr_t accctl_high; 128 bus_addr_t accctl_low; 129 bus_addr_t accctl_top; 130 } pci_initinfo[2][4] = { 131 { 132 { 133 0x10, PCI_BARE_SCS0En, 134 GT_SCS0_Low_Decode, GT_SCS0_High_Decode, 135 PCI_SCS0_BAR_SIZE(0), 136 PCI_ACCESS_CONTROL_BASE_HIGH(0, 0), 137 PCI_ACCESS_CONTROL_BASE_LOW(0, 0), 138 PCI_ACCESS_CONTROL_TOP(0, 0), 139 }, { 140 0x14, PCI_BARE_SCS1En, 141 GT_SCS1_Low_Decode, GT_SCS1_High_Decode, 142 PCI_SCS1_BAR_SIZE(0), 143 PCI_ACCESS_CONTROL_BASE_HIGH(0, 1), 144 PCI_ACCESS_CONTROL_BASE_LOW(0, 1), 145 PCI_ACCESS_CONTROL_TOP(0, 1), 146 }, { 147 0x18, PCI_BARE_SCS2En, 148 GT_SCS2_Low_Decode, GT_SCS2_High_Decode, 149 PCI_SCS2_BAR_SIZE(0), 150 PCI_ACCESS_CONTROL_BASE_HIGH(0, 2), 151 PCI_ACCESS_CONTROL_BASE_LOW(0, 2), 152 PCI_ACCESS_CONTROL_TOP(0, 2), 153 }, { 154 0x1c, PCI_BARE_SCS3En, 155 GT_SCS3_Low_Decode, GT_SCS3_High_Decode, 156 PCI_SCS3_BAR_SIZE(0), 157 PCI_ACCESS_CONTROL_BASE_HIGH(0, 3), 158 PCI_ACCESS_CONTROL_BASE_LOW(0, 3), 159 PCI_ACCESS_CONTROL_TOP(0, 3), 160 }, 161 }, { 162 { 163 0x10, PCI_BARE_SCS0En, 164 GT_SCS0_Low_Decode, GT_SCS0_High_Decode, 165 PCI_SCS0_BAR_SIZE(1), 166 PCI_ACCESS_CONTROL_BASE_HIGH(1, 0), 167 PCI_ACCESS_CONTROL_BASE_LOW(1, 0), 168 PCI_ACCESS_CONTROL_TOP(1, 0), 169 }, { 170 0x14, PCI_BARE_SCS1En, 171 GT_SCS1_Low_Decode, GT_SCS1_High_Decode, 172 PCI_SCS1_BAR_SIZE(1), 173 PCI_ACCESS_CONTROL_BASE_HIGH(1, 1), 174 PCI_ACCESS_CONTROL_BASE_LOW(1, 1), 175 PCI_ACCESS_CONTROL_TOP(1, 1), 176 }, { 177 0x18, PCI_BARE_SCS2En, 178 GT_SCS2_Low_Decode, GT_SCS2_High_Decode, 179 PCI_SCS2_BAR_SIZE(1), 180 PCI_ACCESS_CONTROL_BASE_HIGH(1, 2), 181 PCI_ACCESS_CONTROL_BASE_LOW(1, 2), 182 PCI_ACCESS_CONTROL_TOP(1, 2), 183 }, { 184 0x1c, PCI_BARE_SCS3En, 185 GT_SCS3_Low_Decode, GT_SCS3_High_Decode, 186 PCI_SCS3_BAR_SIZE(1), 187 PCI_ACCESS_CONTROL_BASE_HIGH(1, 3), 188 PCI_ACCESS_CONTROL_BASE_LOW(1, 3), 189 PCI_ACCESS_CONTROL_TOP(1, 3), 190 }, 191 } 192 }; 193 194 int 195 gtpci_match(struct device *parent, struct cfdata *self, void *aux) 196 { 197 struct gt_softc * const gt = (struct gt_softc *) parent; 198 struct gt_attach_args * const ga = aux; 199 200 return GT_PCIOK(gt, ga, >pci_cd); 201 } 202 203 int 204 gtpci_cfprint(void *aux, const char *pnp) 205 { 206 struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux; 207 208 if (pnp) 209 aprint_normal("pci at %s", pnp); 210 211 aprint_normal(" bus %d", pba->pba_bus); 212 213 return (UNCONF); 214 } 215 216 void 217 gtpci_attach(struct device *parent, struct device *self, void *aux) 218 { 219 struct pcibus_attach_args pba; 220 struct gt_attach_args * const ga = aux; 221 struct gt_softc * const gt = (struct gt_softc *) parent; 222 struct gtpci_softc * const gtp = (struct gtpci_softc *) self; 223 struct gtpci_chipset * const gtpc = >p->gtpci_gtpc; 224 struct pci_chipset * const pc = >pc->gtpc_pc; 225 const int busno = ga->ga_unit; 226 uint32_t data; 227 228 GT_PCIFOUND(gt, ga); 229 230 pc->pc_funcs = >pci_functions; 231 pc->pc_parent = self; 232 233 gtpc->gtpc_busno = busno; 234 gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno); 235 gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno); 236 gtpc->gtpc_syncreg = PCI_SYNC_REG(busno); 237 gtpc->gtpc_gt_memt = ga->ga_memt; 238 gtpc->gtpc_gt_memh = ga->ga_memh; 239 240 /* 241 * Let's find out where we are located. 242 */ 243 data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno)); 244 gtpc->gtpc_self = gtpci_make_tag(>pc->gtpc_pc, 245 PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0); 246 247 248 switch (busno) { 249 case 0: 250 gtpc->gtpc_io_bs = gt->gt_pci0_iot; 251 gtpc->gtpc_mem_bs = gt->gt_pci0_memt; 252 break; 253 case 1: 254 gtpc->gtpc_io_bs = gt->gt_pci1_iot; 255 gtpc->gtpc_mem_bs = gt->gt_pci1_memt; 256 break; 257 default: 258 break; 259 } 260 261 /* 262 * If no bus_spaces exist, then it's been disabled. 263 */ 264 if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) { 265 aprint_normal(": disabled\n"); 266 return; 267 } 268 269 aprint_normal("\n"); 270 271 /* 272 * clear any pre-existing error interrupt(s) 273 * clear latched pci error registers 274 * establish ISRs for PCI errors 275 * enable PCI error interrupts 276 */ 277 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0); 278 (void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 279 (void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 280 (void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 281 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 282 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 283 intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL, IPL_GTERR, 284 gtpci_error_intr, pc); 285 intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL, IPL_GTERR, 286 gtpci_error_intr, pc); 287 intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL, IPL_GTERR, 288 gtpci_error_intr, pc); 289 aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n", 290 pc->pc_parent->dv_xname, "pci", busno, 291 intr_string(pci_irqs[gtpc->gtpc_busno][0]), 292 intr_string(pci_irqs[gtpc->gtpc_busno][1]), 293 intr_string(pci_irqs[gtpc->gtpc_busno][2])); 294 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), PCI_SERRMSK_ALL_ERRS); 295 296 /* 297 * Fill in the pci_bus_attach_args 298 */ 299 pba.pba_pc = pc; 300 pba.pba_bus = 0; 301 pba.pba_busname = "pci"; 302 pba.pba_iot = gtpc->gtpc_io_bs; 303 pba.pba_memt = gtpc->gtpc_mem_bs; 304 pba.pba_dmat = gt->gt_dmat; 305 pba.pba_flags = 0; 306 if (pba.pba_iot != NULL) 307 pba.pba_flags |= PCI_FLAGS_IO_ENABLED; 308 if (pba.pba_memt != NULL) 309 pba.pba_flags |= PCI_FLAGS_MEM_ENABLED; 310 311 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 312 if (data & PCI_CMD_MRdMul) 313 pba.pba_flags |= PCI_FLAGS_MRM_OKAY; 314 if (data & PCI_CMD_MRdLine) 315 pba.pba_flags |= PCI_FLAGS_MRL_OKAY; 316 pba.pba_flags |= PCI_FLAGS_MWI_OKAY; 317 318 gt_watchdog_service(); 319 /* 320 * Configure the pci bus. 321 */ 322 config_found(self, &pba, gtpci_cfprint); 323 324 gt_watchdog_service(); 325 326 } 327 328 void 329 gtpci_bus_init(struct gtpci_chipset *gtpc) 330 { 331 const struct pci_init *pi; 332 uint32_t data, datal, datah; 333 pcireg_t pcidata; 334 int i; 335 336 /* 337 * disable all BARs to start. 338 */ 339 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 340 0xffffffff); 341 342 /* 343 * Enable internal arbiter 344 */ 345 data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno)); 346 data |= PCI_ARBCTL_EN; 347 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data); 348 349 /* 350 * Make the GT reflects reality. 351 * We always enable internal memory. 352 */ 353 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x20) & 0xfff; 354 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 0x20, 355 GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) | pcidata); 356 data = PCI_BARE_IntMemEn; 357 358 for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) 359 gtpci_write(gtpc, pi->barsize, 0); 360 361 /* 362 * Enable bus master access (needed for config access). 363 */ 364 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 365 PCI_COMMAND_STATUS_REG); 366 pcidata |= PCI_COMMAND_MASTER_ENABLE; 367 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 368 PCI_COMMAND_STATUS_REG, pcidata); 369 370 /* 371 * Map each SCS BAR to correspond to each SDRAM decode register. 372 */ 373 for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) { 374 datal = gtpci_read(gtpc, pi->low_decode); 375 datah = gtpci_read(gtpc, pi->high_decode); 376 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 377 pi->bar_regno); 378 gtpci_write(gtpc, pi->accctl_high, 0); 379 if (datal < datah) { 380 datal &= 0xfff; 381 pcidata &= 0xfff; 382 pcidata |= datal << 20; 383 data |= pi->bar_enable; 384 datah -= datal; 385 datal |= PCI_ACCCTLBASEL_PrefetchEn| 386 PCI_ACCCTLBASEL_RdPrefetch| 387 PCI_ACCCTLBASEL_RdLinePrefetch| 388 PCI_ACCCTLBASEL_RdMulPrefetch| 389 PCI_ACCCTLBASEL_WBurst_8_QW| 390 PCI_ACCCTLBASEL_PCISwap_NoSwap; 391 gtpci_write(gtpc, pi->accctl_low, datal); 392 } else { 393 pcidata &= 0xfff; 394 datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap; 395 datah = 0; 396 } 397 gtpci_write(gtpc, pi->barsize, 398 datah ? ((datah << 20) | 0xff000) : 0); 399 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 400 pi->bar_regno, pcidata); 401 gtpci_write(gtpc, pi->accctl_low, datal); 402 gtpci_write(gtpc, pi->accctl_top, datah); 403 } 404 405 /* 406 * Now re-enable those BARs that are real. 407 */ 408 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 409 ~data); 410 411 /* 412 * Enable I/O and memory (bus master is already enabled) access. 413 */ 414 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 415 PCI_COMMAND_STATUS_REG); 416 pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 417 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 418 PCI_COMMAND_STATUS_REG, pcidata); 419 } 420 421 void 422 gtpci_bus_attach_hook(struct device *parent, struct device *self, 423 struct pcibus_attach_args *pba) 424 { 425 struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc; 426 uint32_t data; 427 #if defined(DEBUG) 428 pcitag_t tag; 429 int bus, dev; 430 int i; 431 #endif 432 433 if (gtpc->gtpc_pc.pc_parent != parent) 434 return; 435 436 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 437 aprint_normal(": id %d%s%s%s%s%s%s%s%s", 438 PCI_MODE_PciID_GET(data), 439 (data & PCI_MODE_Pci64) ? ", 64bit" : "", 440 (data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "", 441 (data & PCI_MODE_VPD) ? ", VPD" : "", 442 (data & PCI_MODE_MSI) ? ", MSI" : "", 443 (data & PCI_MODE_PMG) ? ", PMG" : "", 444 (data & PCI_MODE_HotSwap) ? ", HotSwap" : "", 445 (data & PCI_MODE_BIST) ? ", BIST" : "", 446 (data & PCI_MODE_PRst) ? "" : ", PRst"); 447 448 #if 0 449 while ((data & PCI_MODE_PRst) == 0) { 450 DELAY(10); 451 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 452 aprint_normal("."); 453 } 454 #endif 455 456 gtpci_bus_init(gtpc); 457 gtpci_bus_configure(gtpc); 458 459 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 460 if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) { 461 aprint_normal("\n%s: ", self->dv_xname); 462 if (data & PCI_CMD_MSwapEn) { 463 switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) { 464 case PCI_CMD_MWordSwap: 465 aprint_normal(" mswap=w"); break; 466 case PCI_CMD_MByteSwap: 467 aprint_normal(" mswap=b"); break; 468 case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap: 469 aprint_normal(" mswap=b+w"); break; 470 case 0: 471 aprint_normal(" mswap=none"); break; 472 } 473 } 474 475 if (data & PCI_CMD_SSwapEn) { 476 switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) { 477 case PCI_CMD_SWordSwap: 478 aprint_normal(" sswap=w"); break; 479 case PCI_CMD_SByteSwap: 480 aprint_normal(" sswap=b"); break; 481 case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap: 482 aprint_normal(" sswap=b+w"); break; 483 case 0: 484 aprint_normal(" sswap=none"); break; 485 } 486 } 487 } 488 489 #if defined(DEBUG) 490 if (gtpci_debug == 0) 491 return; 492 493 data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno)); 494 aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data); 495 496 aprint_normal("\n%s: 0:0:0\n", self->dv_xname); 497 aprint_normal(" %sSCS0=%#010x", 498 (data & 1) ? "-" : "+", 499 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x10)); 500 aprint_normal("/%#010x", gtpci_read(gtpc, 501 PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno))); 502 aprint_normal(" remap %#010x\n", 503 gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 504 505 aprint_normal(" %sSCS1=%#010x", 506 (data & 2) ? "-" : "+", 507 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x14)); 508 aprint_normal("/%#010x", 509 gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno))); 510 aprint_normal(" remap %#010x\n", 511 gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 512 513 aprint_normal(" %sSCS2=%#010x", 514 (data & 4) ? "-" : "+", 515 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x18)); 516 aprint_normal("/%#010x", 517 gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno))); 518 aprint_normal(" remap %#010x\n", 519 gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 520 521 aprint_normal(" %sSCS3=%#010x", 522 (data & 8) ? "-" : "+", 523 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x1c)); 524 aprint_normal("/%#010x", 525 gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno))); 526 aprint_normal(" remap %#010x\n", 527 gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 528 529 aprint_normal(" %sIMem=%#010x", 530 (data & PCI_BARE_IntMemEn) ? "-" : "+", 531 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x20)); 532 aprint_normal("\n"); 533 aprint_normal(" %sIIO=%#010x", 534 (data & PCI_BARE_IntIOEn) ? "-" : "+", 535 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x24)); 536 aprint_normal("\n"); 537 538 gtpci_decompose_tag(>pc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL); 539 tag = gtpci_make_tag(>pc->gtpc_pc, bus, dev, 1); 540 aprint_normal(" %sCS0=%#010x", 541 (data & PCI_BARE_CS0En) ? "-" : "+", 542 gtpci_conf_read(>pc->gtpc_pc, tag, 0x10)); 543 aprint_normal("/%#010x", 544 gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno))); 545 aprint_normal(" remap %#010x\n", 546 gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 547 548 aprint_normal(" %sCS1=%#010x", 549 (data & PCI_BARE_CS1En) ? "-" : "+", 550 gtpci_conf_read(>pc->gtpc_pc, tag, 0x14)); 551 aprint_normal("/%#010x", 552 gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno))); 553 aprint_normal(" remap %#010x\n", 554 gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 555 556 aprint_normal(" %sCS2=%#010x", 557 (data & PCI_BARE_CS2En) ? "-" : "+", 558 gtpci_conf_read(>pc->gtpc_pc, tag, 0x18)); 559 aprint_normal("/%#010x", 560 gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno))); 561 aprint_normal(" remap %#010x\n", 562 gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 563 564 aprint_normal(" %sCS3=%#010x", 565 (data & PCI_BARE_CS3En) ? "-" : "+", 566 gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c)); 567 aprint_normal("/%#010x", 568 gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno))); 569 aprint_normal(" remap %#010x\n", 570 gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 571 572 aprint_normal(" %sBootCS=%#010x", 573 (data & PCI_BARE_BootCSEn) ? "-" : "+", 574 gtpci_conf_read(>pc->gtpc_pc, tag, 0x20)); 575 aprint_normal("/%#010x", 576 gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno))); 577 aprint_normal(" remap %#010x\n", 578 gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno))); 579 580 tag = gtpci_make_tag(>pc->gtpc_pc, bus, tag, 2); 581 aprint_normal(" %sP2PM0=%#010x", 582 (data & PCI_BARE_P2PMem0En) ? "-" : "+", 583 gtpci_conf_read(>pc->gtpc_pc, tag, 0x10)); 584 aprint_normal("/%#010x", 585 gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno))); 586 aprint_normal(" remap %#010x.%#010x\n", 587 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 588 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 589 590 aprint_normal(" %sP2PM1=%#010x", 591 (data & PCI_BARE_P2PMem1En) ? "-" : "+", 592 gtpci_conf_read(>pc->gtpc_pc, tag, 0x14)); 593 aprint_normal("/%#010x", 594 gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno))); 595 aprint_normal(" remap %#010x.%#010x\n", 596 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 597 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 598 599 aprint_normal(" %sP2PIO=%#010x", 600 (data & PCI_BARE_P2PIOEn) ? "-" : "+", 601 gtpci_conf_read(>pc->gtpc_pc, tag, 0x18)); 602 aprint_normal("/%#010x", 603 gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno))); 604 aprint_normal(" remap %#010x\n", 605 gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 606 607 aprint_normal(" %sCPU=%#010x", 608 (data & PCI_BARE_CPUEn) ? "-" : "+", 609 gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c)); 610 aprint_normal("/%#010x", 611 gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno))); 612 aprint_normal(" remap %#010x\n", 613 gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 614 615 for (i = 0; i < 8; i++) { 616 aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i); 617 data = gtpci_read(gtpc, 618 PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i)); 619 if (data) 620 aprint_normal("base=0x%08x.", data); 621 else 622 aprint_normal("base=0x"); 623 data = gtpci_read(gtpc, 624 PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i)); 625 printf("%08x cfg=0x%08x", data << 20, data & ~0xfff); 626 aprint_normal(" top=0x%03x00000", 627 gtpci_read(gtpc, 628 PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i))); 629 } 630 #endif 631 } 632 633 static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings; 634 635 int 636 gtpci_error_intr(void *arg) 637 { 638 pci_chipset_tag_t pc = arg; 639 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 640 uint32_t cause, mask, errmask; 641 u_int32_t alo, ahi, dlo, dhi, cmd; 642 int i; 643 644 cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno)); 645 errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno)); 646 cause &= errmask | 0xf8000000; 647 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause); 648 printf("%s: pci%d error: cause=%#x mask=%#x", 649 pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask); 650 if ((cause & 0xf8000000) == 0) { 651 printf(" ?\n"); 652 return 0; 653 } 654 655 for (i = 0, mask = 1; i <= 26; i++, mask += mask) 656 if (mask & cause) 657 printf(" %s", gtpci_error_strings[i]); 658 659 /* 660 * "no new data is latched until the PCI Error Low Address 661 * register is read. This means that PCI Error Low Address 662 * register must be the last register read by the interrupt 663 * handler." 664 */ 665 dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 666 dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 667 cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 668 ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 669 alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 670 printf("\n%s: pci%d error: %s cmd=%#x", 671 pc->pc_parent->dv_xname, gtpc->gtpc_busno, 672 gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd); 673 if (dhi == 0) 674 printf(" data=%08x", dlo); 675 else 676 printf(" data=%08x.%08x", dhi, dlo); 677 if (ahi == 0) 678 printf(" address=%08x\n", alo); 679 else 680 printf(" address=%08x.%08x\n", ahi, alo); 681 682 #if defined(DEBUG) && defined(DDB) 683 if (gtpci_debug > 1) 684 Debugger(); 685 #endif 686 return 1; 687 } 688 689 690 #if 0 691 void 692 gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs, 693 struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi) 694 { 695 /* See how I/O space is configured. Read the base and top 696 * registers. 697 */ 698 paddr_t pbasel, pbaseh; 699 uint32_t datal, datah; 700 701 datal = gtpci_read(gtpc, lo); 702 datah = gtpci_read(gtpc, hi); 703 pbasel = GT_LowAddr_GET(datal); 704 pbaseh = GT_HighAddr_GET(datah); 705 /* 706 * If the start is greater than the end, ignore the region. 707 */ 708 if (pbaseh < pbasel) 709 return; 710 if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase 711 && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) { 712 bs->bs_regions[bs->bs_nregion].br_vbase = 713 gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask); 714 } 715 bs->bs_regions[bs->bs_nregion].br_pbase = pbasel; 716 if (bs->bs_flags & _BUS_SPACE_RELATIVE) { 717 bs->bs_regions[bs->bs_nregion].br_start = 0; 718 bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel; 719 } else { 720 bs->bs_regions[bs->bs_nregion].br_start = pbasel; 721 bs->bs_regions[bs->bs_nregion].br_end = pbaseh; 722 } 723 bs->bs_nregion++; 724 } 725 #endif 726 727 /* 728 * Internal functions. 729 */ 730 int 731 gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 732 { 733 return 32; 734 } 735 736 pcitag_t 737 gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno) 738 { 739 return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0); 740 } 741 742 void 743 gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 744 int *bp, int *dp, int *fp) 745 { 746 if (bp != NULL) 747 *bp = PCI_CFG_GET_BUSNO(tag); 748 if (dp != NULL) 749 *dp = PCI_CFG_GET_DEVNO(tag); 750 if (fp != NULL) 751 *fp = PCI_CFG_GET_FUNCNO(tag); 752 } 753 754 pcireg_t 755 gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno) 756 { 757 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 758 #ifdef DIAGNOSTIC 759 if ((regno & 3) || (regno & ~0xff)) 760 panic("gtpci_conf_read: bad regno %#x\n", regno); 761 #endif 762 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 763 return gtpci_read(gtpc, gtpc->gtpc_cfgdata); 764 } 765 766 void 767 gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data) 768 { 769 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 770 #ifdef DIAGNOSTIC 771 if ((regno & 3) || (regno & ~0xff)) 772 panic("gtpci_conf_write: bad regno %#x\n", regno); 773 #endif 774 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 775 gtpci_write(gtpc, gtpc->gtpc_cfgdata, data); 776 } 777 778 const char * 779 gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih) 780 { 781 return intr_string(pih); 782 } 783 784 const struct evcnt * 785 gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih) 786 { 787 return intr_evcnt(pih); 788 } 789 790 void * 791 gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih, 792 int ipl, int (*handler)(void *), void *arg) 793 { 794 return intr_establish(pih, IST_LEVEL, ipl, handler, arg); 795 } 796 797 void 798 gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 799 { 800 intr_disestablish(cookie); 801 } 802