1 /* $NetBSD: gtpci.c,v 1.9 2003/06/12 19:18:49 scw Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include "opt_marvell.h" 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/extent.h> 44 #include <sys/malloc.h> 45 #include <lib/libkern/libkern.h> 46 47 #define _BUS_SPACE_PRIVATE 48 #define _BUS_DMA_PRIVATE 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pciconf.h> 55 #include <dev/marvell/gtreg.h> 56 #include <dev/marvell/gtvar.h> 57 #include <dev/marvell/gtintrreg.h> 58 #include <dev/marvell/gtpcireg.h> 59 #include <dev/marvell/gtpcivar.h> 60 #include <dev/marvell/gtvar.h> 61 62 static int gtpci_error_intr(void *); 63 64 static void gtpci_bus_init(struct gtpci_chipset *); 65 66 static void gtpci_bus_attach_hook(struct device *, struct device *, 67 struct pcibus_attach_args *); 68 static int gtpci_bus_maxdevs(pci_chipset_tag_t, int); 69 70 static const char * 71 gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); 72 static const struct evcnt * 73 gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t); 74 static void *gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 75 int, int (*)(void *), void *); 76 static void gtpci_intr_disestablish(pci_chipset_tag_t, void *); 77 78 #ifdef DEBUG 79 int gtpci_debug = 0; 80 #endif 81 82 struct gtpci_softc { 83 struct device gtpci_dev; 84 struct gtpci_chipset gtpci_gtpc; 85 }; 86 87 static int gtpci_cfprint(void *, const char *); 88 static int gtpci_match(struct device *, struct cfdata *, void *); 89 static void gtpci_attach(struct device *, struct device *, void *); 90 91 CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc), 92 gtpci_match, gtpci_attach, NULL, NULL); 93 94 extern struct cfdriver gtpci_cd; 95 96 const struct pci_chipset_functions gtpci_functions = { 97 gtpci_bus_attach_hook, 98 gtpci_bus_maxdevs, 99 gtpci_md_bus_devorder, 100 101 gtpci_make_tag, 102 gtpci_decompose_tag, 103 104 gtpci_conf_read, 105 gtpci_conf_write, 106 gtpci_md_conf_hook, 107 gtpci_md_conf_interrupt, 108 109 gtpci_md_intr_map, 110 gtpci_intr_string, 111 gtpci_intr_evcnt, 112 gtpci_intr_establish, 113 gtpci_intr_disestablish 114 }; 115 116 static const int pci_irqs[2][3] = { 117 { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 }, 118 { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 }, 119 }; 120 121 static const struct pci_init { 122 int bar_regno; 123 u_int32_t bar_enable; 124 bus_addr_t low_decode; 125 bus_addr_t high_decode; 126 bus_addr_t barsize; 127 bus_addr_t accctl_high; 128 bus_addr_t accctl_low; 129 bus_addr_t accctl_top; 130 } pci_initinfo[2][4] = { 131 { 132 { 133 0x10, PCI_BARE_SCS0En, 134 GT_SCS0_Low_Decode, GT_SCS0_High_Decode, 135 PCI_SCS0_BAR_SIZE(0), 136 PCI_ACCESS_CONTROL_BASE_HIGH(0, 0), 137 PCI_ACCESS_CONTROL_BASE_LOW(0, 0), 138 PCI_ACCESS_CONTROL_TOP(0, 0), 139 }, { 140 0x14, PCI_BARE_SCS1En, 141 GT_SCS1_Low_Decode, GT_SCS1_High_Decode, 142 PCI_SCS1_BAR_SIZE(0), 143 PCI_ACCESS_CONTROL_BASE_HIGH(0, 1), 144 PCI_ACCESS_CONTROL_BASE_LOW(0, 1), 145 PCI_ACCESS_CONTROL_TOP(0, 1), 146 }, { 147 0x18, PCI_BARE_SCS2En, 148 GT_SCS2_Low_Decode, GT_SCS2_High_Decode, 149 PCI_SCS2_BAR_SIZE(0), 150 PCI_ACCESS_CONTROL_BASE_HIGH(0, 2), 151 PCI_ACCESS_CONTROL_BASE_LOW(0, 2), 152 PCI_ACCESS_CONTROL_TOP(0, 2), 153 }, { 154 0x1c, PCI_BARE_SCS3En, 155 GT_SCS3_Low_Decode, GT_SCS3_High_Decode, 156 PCI_SCS3_BAR_SIZE(0), 157 PCI_ACCESS_CONTROL_BASE_HIGH(0, 3), 158 PCI_ACCESS_CONTROL_BASE_LOW(0, 3), 159 PCI_ACCESS_CONTROL_TOP(0, 3), 160 }, 161 }, { 162 { 163 0x10, PCI_BARE_SCS0En, 164 GT_SCS0_Low_Decode, GT_SCS0_High_Decode, 165 PCI_SCS0_BAR_SIZE(1), 166 PCI_ACCESS_CONTROL_BASE_HIGH(1, 0), 167 PCI_ACCESS_CONTROL_BASE_LOW(1, 0), 168 PCI_ACCESS_CONTROL_TOP(1, 0), 169 }, { 170 0x14, PCI_BARE_SCS1En, 171 GT_SCS1_Low_Decode, GT_SCS1_High_Decode, 172 PCI_SCS1_BAR_SIZE(1), 173 PCI_ACCESS_CONTROL_BASE_HIGH(1, 1), 174 PCI_ACCESS_CONTROL_BASE_LOW(1, 1), 175 PCI_ACCESS_CONTROL_TOP(1, 1), 176 }, { 177 0x18, PCI_BARE_SCS2En, 178 GT_SCS2_Low_Decode, GT_SCS2_High_Decode, 179 PCI_SCS2_BAR_SIZE(1), 180 PCI_ACCESS_CONTROL_BASE_HIGH(1, 2), 181 PCI_ACCESS_CONTROL_BASE_LOW(1, 2), 182 PCI_ACCESS_CONTROL_TOP(1, 2), 183 }, { 184 0x1c, PCI_BARE_SCS3En, 185 GT_SCS3_Low_Decode, GT_SCS3_High_Decode, 186 PCI_SCS3_BAR_SIZE(1), 187 PCI_ACCESS_CONTROL_BASE_HIGH(1, 3), 188 PCI_ACCESS_CONTROL_BASE_LOW(1, 3), 189 PCI_ACCESS_CONTROL_TOP(1, 3), 190 }, 191 } 192 }; 193 194 int 195 gtpci_match(struct device *parent, struct cfdata *self, void *aux) 196 { 197 struct gt_softc * const gt = (struct gt_softc *) parent; 198 struct gt_attach_args * const ga = aux; 199 200 return GT_PCIOK(gt, ga, >pci_cd); 201 } 202 203 int 204 gtpci_cfprint(void *aux, const char *pnp) 205 { 206 struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux; 207 208 if (pnp) 209 aprint_normal("pci at %s", pnp); 210 211 aprint_normal(" bus %d", pba->pba_bus); 212 213 return (UNCONF); 214 } 215 216 void 217 gtpci_attach(struct device *parent, struct device *self, void *aux) 218 { 219 struct pcibus_attach_args pba; 220 struct gt_attach_args * const ga = aux; 221 struct gt_softc * const gt = (struct gt_softc *) parent; 222 struct gtpci_softc * const gtp = (struct gtpci_softc *) self; 223 struct gtpci_chipset * const gtpc = >p->gtpci_gtpc; 224 struct pci_chipset * const pc = >pc->gtpc_pc; 225 const int busno = ga->ga_unit; 226 uint32_t data; 227 228 GT_PCIFOUND(gt, ga); 229 230 pc->pc_funcs = >pci_functions; 231 pc->pc_parent = self; 232 233 gtpc->gtpc_busno = busno; 234 gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno); 235 gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno); 236 gtpc->gtpc_syncreg = PCI_SYNC_REG(busno); 237 gtpc->gtpc_gt_memt = ga->ga_memt; 238 gtpc->gtpc_gt_memh = ga->ga_memh; 239 240 /* 241 * Let's find out where we are located. 242 */ 243 data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno)); 244 gtpc->gtpc_self = gtpci_make_tag(>pc->gtpc_pc, 245 PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0); 246 247 248 switch (busno) { 249 case 0: 250 gtpc->gtpc_io_bs = gt->gt_pci0_iot; 251 gtpc->gtpc_mem_bs = gt->gt_pci0_memt; 252 gtpc->gtpc_host = gt->gt_pci0_host; 253 break; 254 case 1: 255 gtpc->gtpc_io_bs = gt->gt_pci1_iot; 256 gtpc->gtpc_mem_bs = gt->gt_pci1_memt; 257 gtpc->gtpc_host = gt->gt_pci1_host; 258 break; 259 default: 260 break; 261 } 262 263 /* 264 * If no bus_spaces exist, then it's been disabled. 265 */ 266 if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) { 267 aprint_normal(": disabled\n"); 268 return; 269 } 270 271 aprint_normal("\n"); 272 273 /* 274 * clear any pre-existing error interrupt(s) 275 * clear latched pci error registers 276 * establish ISRs for PCI errors 277 * enable PCI error interrupts 278 */ 279 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 0); 280 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0); 281 (void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 282 (void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 283 (void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 284 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 285 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 286 if (gtpc->gtpc_host) { 287 intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL, 288 IPL_GTERR, gtpci_error_intr, pc); 289 intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL, 290 IPL_GTERR, gtpci_error_intr, pc); 291 intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL, 292 IPL_GTERR, gtpci_error_intr, pc); 293 aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n", 294 pc->pc_parent->dv_xname, "pci", busno, 295 intr_string(pci_irqs[gtpc->gtpc_busno][0]), 296 intr_string(pci_irqs[gtpc->gtpc_busno][1]), 297 intr_string(pci_irqs[gtpc->gtpc_busno][2])); 298 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 299 PCI_SERRMSK_ALL_ERRS); 300 } 301 302 /* 303 * Fill in the pci_bus_attach_args 304 */ 305 pba.pba_pc = pc; 306 pba.pba_bus = 0; 307 pba.pba_busname = "pci"; 308 pba.pba_iot = gtpc->gtpc_io_bs; 309 pba.pba_memt = gtpc->gtpc_mem_bs; 310 pba.pba_dmat = gt->gt_dmat; 311 pba.pba_flags = 0; 312 if (pba.pba_iot != NULL) 313 pba.pba_flags |= PCI_FLAGS_IO_ENABLED; 314 if (pba.pba_memt != NULL) 315 pba.pba_flags |= PCI_FLAGS_MEM_ENABLED; 316 317 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 318 if (data & PCI_CMD_MRdMul) 319 pba.pba_flags |= PCI_FLAGS_MRM_OKAY; 320 if (data & PCI_CMD_MRdLine) 321 pba.pba_flags |= PCI_FLAGS_MRL_OKAY; 322 pba.pba_flags |= PCI_FLAGS_MWI_OKAY; 323 324 gt_watchdog_service(); 325 /* 326 * Configure the pci bus. 327 */ 328 config_found(self, &pba, gtpci_cfprint); 329 330 gt_watchdog_service(); 331 332 } 333 334 void 335 gtpci_bus_init(struct gtpci_chipset *gtpc) 336 { 337 const struct pci_init *pi; 338 uint32_t data, datal, datah; 339 pcireg_t pcidata; 340 int i; 341 342 /* 343 * disable all BARs to start. 344 */ 345 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 346 0xffffffff); 347 348 #ifndef GT_PCI0_EXT_ARBITER 349 #define GT_PCI0_EXT_ARBITER 0 350 #endif 351 #ifndef GT_PCI1_EXT_ARBITER 352 #define GT_PCI1_EXT_ARBITER 0 353 #endif 354 355 if (gtpc->gtpc_host && 356 ((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) || 357 (!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1))) { 358 /* 359 * Enable internal arbiter 360 */ 361 data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno)); 362 data |= PCI_ARBCTL_EN; 363 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data); 364 } else { 365 /* 366 * Make sure the internal arbiter is disabled 367 */ 368 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0); 369 } 370 371 /* 372 * Make the GT reflects reality. 373 * We always enable internal memory. 374 */ 375 if (gtpc->gtpc_host) { 376 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 377 0x20) & 0xfff; 378 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 0x20, 379 GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) | 380 pcidata); 381 } 382 data = PCI_BARE_IntMemEn; 383 384 for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) 385 gtpci_write(gtpc, pi->barsize, 0); 386 387 if (gtpc->gtpc_host) { 388 /* 389 * Enable bus master access (needed for config access). 390 */ 391 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 392 PCI_COMMAND_STATUS_REG); 393 pcidata |= PCI_COMMAND_MASTER_ENABLE; 394 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 395 PCI_COMMAND_STATUS_REG, pcidata); 396 } 397 398 /* 399 * Map each SCS BAR to correspond to each SDRAM decode register. 400 */ 401 for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) { 402 datal = gtpci_read(gtpc, pi->low_decode); 403 datah = gtpci_read(gtpc, pi->high_decode); 404 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 405 pi->bar_regno); 406 gtpci_write(gtpc, pi->accctl_high, 0); 407 if (datal < datah) { 408 datal &= 0xfff; 409 pcidata &= 0xfff; 410 pcidata |= datal << 20; 411 data |= pi->bar_enable; 412 datah -= datal; 413 datal |= PCI_ACCCTLBASEL_PrefetchEn| 414 PCI_ACCCTLBASEL_RdPrefetch| 415 PCI_ACCCTLBASEL_RdLinePrefetch| 416 PCI_ACCCTLBASEL_RdMulPrefetch| 417 PCI_ACCCTLBASEL_WBurst_8_QW| 418 PCI_ACCCTLBASEL_PCISwap_NoSwap; 419 gtpci_write(gtpc, pi->accctl_low, datal); 420 } else { 421 pcidata &= 0xfff; 422 datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap; 423 datah = 0; 424 } 425 gtpci_write(gtpc, pi->barsize, 426 datah ? ((datah << 20) | 0xff000) : 0); 427 if (gtpc->gtpc_host) { 428 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 429 pi->bar_regno, pcidata); 430 } 431 gtpci_write(gtpc, pi->accctl_low, datal); 432 gtpci_write(gtpc, pi->accctl_top, datah); 433 } 434 435 /* 436 * Now re-enable those BARs that are real. 437 */ 438 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 439 ~data); 440 441 if (gtpc->gtpc_host) { 442 /* 443 * Enable I/O and memory (bus master is already enabled) access. 444 */ 445 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 446 PCI_COMMAND_STATUS_REG); 447 pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 448 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 449 PCI_COMMAND_STATUS_REG, pcidata); 450 } 451 } 452 453 void 454 gtpci_bus_attach_hook(struct device *parent, struct device *self, 455 struct pcibus_attach_args *pba) 456 { 457 struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc; 458 uint32_t data; 459 #if defined(DEBUG) 460 pcitag_t tag; 461 int bus, dev; 462 int i; 463 #endif 464 465 if (gtpc->gtpc_pc.pc_parent != parent) 466 return; 467 468 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 469 aprint_normal(": id %d%s%s%s%s%s%s%s%s", 470 PCI_MODE_PciID_GET(data), 471 (data & PCI_MODE_Pci64) ? ", 64bit" : "", 472 (data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "", 473 (data & PCI_MODE_VPD) ? ", VPD" : "", 474 (data & PCI_MODE_MSI) ? ", MSI" : "", 475 (data & PCI_MODE_PMG) ? ", PMG" : "", 476 (data & PCI_MODE_HotSwap) ? ", HotSwap" : "", 477 (data & PCI_MODE_BIST) ? ", BIST" : "", 478 (data & PCI_MODE_PRst) ? "" : ", PRst"); 479 480 #if 0 481 while ((data & PCI_MODE_PRst) == 0) { 482 DELAY(10); 483 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 484 aprint_normal("."); 485 } 486 #endif 487 488 gtpci_bus_init(gtpc); 489 gtpci_bus_configure(gtpc); 490 491 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 492 if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) { 493 aprint_normal("\n%s: ", self->dv_xname); 494 if (data & PCI_CMD_MSwapEn) { 495 switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) { 496 case PCI_CMD_MWordSwap: 497 aprint_normal(" mswap=w"); break; 498 case PCI_CMD_MByteSwap: 499 aprint_normal(" mswap=b"); break; 500 case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap: 501 aprint_normal(" mswap=b+w"); break; 502 case 0: 503 aprint_normal(" mswap=none"); break; 504 } 505 } 506 507 if (data & PCI_CMD_SSwapEn) { 508 switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) { 509 case PCI_CMD_SWordSwap: 510 aprint_normal(" sswap=w"); break; 511 case PCI_CMD_SByteSwap: 512 aprint_normal(" sswap=b"); break; 513 case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap: 514 aprint_normal(" sswap=b+w"); break; 515 case 0: 516 aprint_normal(" sswap=none"); break; 517 } 518 } 519 } 520 521 #if defined(DEBUG) 522 if (gtpci_debug == 0) 523 return; 524 525 data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno)); 526 aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data); 527 528 aprint_normal("\n%s: 0:0:0\n", self->dv_xname); 529 aprint_normal(" %sSCS0=%#010x", 530 (data & 1) ? "-" : "+", 531 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x10)); 532 aprint_normal("/%#010x", gtpci_read(gtpc, 533 PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno))); 534 aprint_normal(" remap %#010x\n", 535 gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 536 537 aprint_normal(" %sSCS1=%#010x", 538 (data & 2) ? "-" : "+", 539 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x14)); 540 aprint_normal("/%#010x", 541 gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno))); 542 aprint_normal(" remap %#010x\n", 543 gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 544 545 aprint_normal(" %sSCS2=%#010x", 546 (data & 4) ? "-" : "+", 547 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x18)); 548 aprint_normal("/%#010x", 549 gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno))); 550 aprint_normal(" remap %#010x\n", 551 gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 552 553 aprint_normal(" %sSCS3=%#010x", 554 (data & 8) ? "-" : "+", 555 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x1c)); 556 aprint_normal("/%#010x", 557 gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno))); 558 aprint_normal(" remap %#010x\n", 559 gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 560 561 aprint_normal(" %sIMem=%#010x", 562 (data & PCI_BARE_IntMemEn) ? "-" : "+", 563 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x20)); 564 aprint_normal("\n"); 565 aprint_normal(" %sIIO=%#010x", 566 (data & PCI_BARE_IntIOEn) ? "-" : "+", 567 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x24)); 568 aprint_normal("\n"); 569 570 gtpci_decompose_tag(>pc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL); 571 tag = gtpci_make_tag(>pc->gtpc_pc, bus, dev, 1); 572 aprint_normal(" %sCS0=%#010x", 573 (data & PCI_BARE_CS0En) ? "-" : "+", 574 gtpci_conf_read(>pc->gtpc_pc, tag, 0x10)); 575 aprint_normal("/%#010x", 576 gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno))); 577 aprint_normal(" remap %#010x\n", 578 gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 579 580 aprint_normal(" %sCS1=%#010x", 581 (data & PCI_BARE_CS1En) ? "-" : "+", 582 gtpci_conf_read(>pc->gtpc_pc, tag, 0x14)); 583 aprint_normal("/%#010x", 584 gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno))); 585 aprint_normal(" remap %#010x\n", 586 gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 587 588 aprint_normal(" %sCS2=%#010x", 589 (data & PCI_BARE_CS2En) ? "-" : "+", 590 gtpci_conf_read(>pc->gtpc_pc, tag, 0x18)); 591 aprint_normal("/%#010x", 592 gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno))); 593 aprint_normal(" remap %#010x\n", 594 gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 595 596 aprint_normal(" %sCS3=%#010x", 597 (data & PCI_BARE_CS3En) ? "-" : "+", 598 gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c)); 599 aprint_normal("/%#010x", 600 gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno))); 601 aprint_normal(" remap %#010x\n", 602 gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 603 604 aprint_normal(" %sBootCS=%#010x", 605 (data & PCI_BARE_BootCSEn) ? "-" : "+", 606 gtpci_conf_read(>pc->gtpc_pc, tag, 0x20)); 607 aprint_normal("/%#010x", 608 gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno))); 609 aprint_normal(" remap %#010x\n", 610 gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno))); 611 612 tag = gtpci_make_tag(>pc->gtpc_pc, bus, tag, 2); 613 aprint_normal(" %sP2PM0=%#010x", 614 (data & PCI_BARE_P2PMem0En) ? "-" : "+", 615 gtpci_conf_read(>pc->gtpc_pc, tag, 0x10)); 616 aprint_normal("/%#010x", 617 gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno))); 618 aprint_normal(" remap %#010x.%#010x\n", 619 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 620 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 621 622 aprint_normal(" %sP2PM1=%#010x", 623 (data & PCI_BARE_P2PMem1En) ? "-" : "+", 624 gtpci_conf_read(>pc->gtpc_pc, tag, 0x14)); 625 aprint_normal("/%#010x", 626 gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno))); 627 aprint_normal(" remap %#010x.%#010x\n", 628 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 629 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 630 631 aprint_normal(" %sP2PIO=%#010x", 632 (data & PCI_BARE_P2PIOEn) ? "-" : "+", 633 gtpci_conf_read(>pc->gtpc_pc, tag, 0x18)); 634 aprint_normal("/%#010x", 635 gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno))); 636 aprint_normal(" remap %#010x\n", 637 gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 638 639 aprint_normal(" %sCPU=%#010x", 640 (data & PCI_BARE_CPUEn) ? "-" : "+", 641 gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c)); 642 aprint_normal("/%#010x", 643 gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno))); 644 aprint_normal(" remap %#010x\n", 645 gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 646 647 for (i = 0; i < 8; i++) { 648 aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i); 649 data = gtpci_read(gtpc, 650 PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i)); 651 if (data) 652 aprint_normal("base=0x%08x.", data); 653 else 654 aprint_normal("base=0x"); 655 data = gtpci_read(gtpc, 656 PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i)); 657 printf("%08x cfg=0x%08x", data << 20, data & ~0xfff); 658 aprint_normal(" top=0x%03x00000", 659 gtpci_read(gtpc, 660 PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i))); 661 } 662 #endif 663 } 664 665 static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings; 666 667 int 668 gtpci_error_intr(void *arg) 669 { 670 pci_chipset_tag_t pc = arg; 671 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 672 uint32_t cause, mask, errmask; 673 u_int32_t alo, ahi, dlo, dhi, cmd; 674 int i; 675 676 cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno)); 677 errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno)); 678 cause &= errmask | 0xf8000000; 679 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause); 680 printf("%s: pci%d error: cause=%#x mask=%#x", 681 pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask); 682 if ((cause & 0xf8000000) == 0) { 683 printf(" ?\n"); 684 return 0; 685 } 686 687 for (i = 0, mask = 1; i <= 26; i++, mask += mask) 688 if (mask & cause) 689 printf(" %s", gtpci_error_strings[i]); 690 691 /* 692 * "no new data is latched until the PCI Error Low Address 693 * register is read. This means that PCI Error Low Address 694 * register must be the last register read by the interrupt 695 * handler." 696 */ 697 dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 698 dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 699 cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 700 ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 701 alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 702 printf("\n%s: pci%d error: %s cmd=%#x", 703 pc->pc_parent->dv_xname, gtpc->gtpc_busno, 704 gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd); 705 if (dhi == 0) 706 printf(" data=%08x", dlo); 707 else 708 printf(" data=%08x.%08x", dhi, dlo); 709 if (ahi == 0) 710 printf(" address=%08x\n", alo); 711 else 712 printf(" address=%08x.%08x\n", ahi, alo); 713 714 #if defined(DEBUG) && defined(DDB) 715 if (gtpci_debug > 1) 716 Debugger(); 717 #endif 718 return 1; 719 } 720 721 722 #if 0 723 void 724 gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs, 725 struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi) 726 { 727 /* See how I/O space is configured. Read the base and top 728 * registers. 729 */ 730 paddr_t pbasel, pbaseh; 731 uint32_t datal, datah; 732 733 datal = gtpci_read(gtpc, lo); 734 datah = gtpci_read(gtpc, hi); 735 pbasel = GT_LowAddr_GET(datal); 736 pbaseh = GT_HighAddr_GET(datah); 737 /* 738 * If the start is greater than the end, ignore the region. 739 */ 740 if (pbaseh < pbasel) 741 return; 742 if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase 743 && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) { 744 bs->bs_regions[bs->bs_nregion].br_vbase = 745 gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask); 746 } 747 bs->bs_regions[bs->bs_nregion].br_pbase = pbasel; 748 if (bs->bs_flags & _BUS_SPACE_RELATIVE) { 749 bs->bs_regions[bs->bs_nregion].br_start = 0; 750 bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel; 751 } else { 752 bs->bs_regions[bs->bs_nregion].br_start = pbasel; 753 bs->bs_regions[bs->bs_nregion].br_end = pbaseh; 754 } 755 bs->bs_nregion++; 756 } 757 #endif 758 759 /* 760 * Internal functions. 761 */ 762 int 763 gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 764 { 765 return 32; 766 } 767 768 pcitag_t 769 gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno) 770 { 771 return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0); 772 } 773 774 void 775 gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 776 int *bp, int *dp, int *fp) 777 { 778 if (bp != NULL) 779 *bp = PCI_CFG_GET_BUSNO(tag); 780 if (dp != NULL) 781 *dp = PCI_CFG_GET_DEVNO(tag); 782 if (fp != NULL) 783 *fp = PCI_CFG_GET_FUNCNO(tag); 784 } 785 786 pcireg_t 787 gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno) 788 { 789 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 790 #ifdef DIAGNOSTIC 791 if ((regno & 3) || (regno & ~0xff)) 792 panic("gtpci_conf_read: bad regno %#x\n", regno); 793 #endif 794 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 795 return gtpci_read(gtpc, gtpc->gtpc_cfgdata); 796 } 797 798 void 799 gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data) 800 { 801 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 802 #ifdef DIAGNOSTIC 803 if ((regno & 3) || (regno & ~0xff)) 804 panic("gtpci_conf_write: bad regno %#x\n", regno); 805 #endif 806 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 807 gtpci_write(gtpc, gtpc->gtpc_cfgdata, data); 808 } 809 810 const char * 811 gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih) 812 { 813 return intr_string(pih); 814 } 815 816 const struct evcnt * 817 gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih) 818 { 819 return intr_evcnt(pih); 820 } 821 822 void * 823 gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih, 824 int ipl, int (*handler)(void *), void *arg) 825 { 826 return intr_establish(pih, IST_LEVEL, ipl, handler, arg); 827 } 828 829 void 830 gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 831 { 832 intr_disestablish(cookie); 833 } 834