1 /* $NetBSD: gtmpscreg.h,v 1.4 2010/04/28 13:51:56 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gtmpscreg.h - register defines for GT-64260 MPSC 42 * 43 * creation Sun Apr 8 11:49:57 PDT 2001 cliff 44 */ 45 46 #ifndef _GTMPSCREG_H 47 #define _GTMPSCREG_H 48 49 #ifndef BIT 50 #define BIT(bitno) (1U << (bitno)) 51 #endif 52 #ifndef BITS 53 #define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo))) 54 #endif 55 56 #define GTMPSC_BASE(u) (MPSC0_BASE + ((u) << 12)) 57 #define GTMPSC_SIZE 0x1000 58 59 #define GTMPSC_NCHAN 2 /* Number of MPSC channels */ 60 61 /******************************************************************************* 62 * 63 * MPSC register address offsets relative to the base mapping 64 */ 65 #define GTMPSC_MMCR_LO 0x000 /* MPSC Main Config Register Low */ 66 #define GTMPSC_MMCR_HI 0x004 /* MPSC Main Config Register High */ 67 #define GTMPSC_MPCR 0x008 /* MPSC Protocol Config Register */ 68 #define GTMPSC_CHR_BASE 0x008 /* MPSC Channel Register Base */ 69 #define GTMPSC_CHRN(n) (GTMPSC_CHR_BASE + ((n) << 2)) 70 #define GTMPSC_NCHR 11 /* CHR 1-11? */ 71 72 #define GTMPSC_MRR 0xb400 /* MPSC Routing Register */ 73 #define GTMPSC_RCRR 0xb404 /* MPSC RX Clock Routing Register */ 74 #define GTMPSC_TCRR 0xb408 /* MPSC TX Clock Routing Register */ 75 76 77 /******************************************************************************* 78 * 79 * MPSC register values & bit defines 80 * 81 * values are provided for UART mode only 82 */ 83 /* 84 * MPSC Routing Register bits 85 */ 86 #define GTMPSC_MRR_PORT0 0 /* serial port #0 */ 87 #define GTMPSC_MRR_NONE 7 /* unconnected */ 88 /* all other "routes" resvd. */ 89 #define GTMPSC_MRR_MR0_MASK BITS(2,0) /* routing mask for MPSC0 */ 90 #define GTMPSC_MRR_RESa BITS(5,3) 91 #define GTMPSC_MRR_MR1_MASK BITS(8,6) /* routing mask for MPSC1 */ 92 #define GTMPSC_MRR_RESb BITS(30,9) 93 #define GTMPSC_MRRE_DSC BIT(31) /* "Don't Stop Clock" */ 94 #define GTMPSC_MRR_RES (GTMPSC_MRR_RESa|GTMPSC_MRR_RESb) 95 /* 96 * MPSC Clock Routing Register bits 97 * the bitfields and route definitions are common for RCRR and TCRR 98 * except for MPSC_TCRR_TSCLK0 99 */ 100 #define GTMPSC_CRR_BRG0 0x0 /* Baud Rate Generator #0 */ 101 #define GTMPSC_CRR_BRG1 0x1 /* Baud Rate Generator #1 */ 102 #define GTMPSC_CRR_BRG2 0x2 /* Baud Rate Generator #2 */ 103 #define GTMPSC_CRR_SCLK0 0x8 /* SCLK0 */ 104 #define GTMPSC_TCRR_TSCLK0 0x9 /* TSCLK0 (for TCRR only) */ 105 /* all other values resvd. */ 106 #define GTMPSC_CRR(u, v) ((v) << GTMPSC_CRR_SHIFT(u)) 107 #define GTMPSC_CRR_SHIFT(u) ((u) * 8) 108 #define GTMPSC_CRR_MASK 0xf 109 #define GTMPSC_CRR_RESa BITS(7,4) 110 #define GTMPSC_CRR_RESb BITS(31,12) 111 #define GTMPSC_CRR_RES (GTMPSC_CRR_RESa|GTMPSC_CRR_RESb) 112 /* 113 * MPSC Main Configuration Register LO bits 114 */ 115 #define GTMPSC_MMCR_LO_MODE_MASK BITS(2,0) 116 #define GTMPSC_MMCR_LO_MODE_UART (0x4 << 0) /* UART mode */ 117 #define GTMPSC_MMCR_LO_TTX BIT(3) /* Transparent TX */ 118 #define GTMPSC_MMCR_LO_TRX BIT(4) /* Transparent RX */ 119 #define GTMPSC_MMCR_LO_RESa BIT(5) 120 #define GTMPSC_MMCR_LO_ET BIT(6) /* Enable TX */ 121 #define GTMPSC_MMCR_LO_ER BIT(7) /* Enable RX */ 122 #define GTMPSC_MMCR_LO_LPBK_MASK BITS(9,8) /* Loop Back */ 123 #define GTMPSC_MMCR_LO_LPBK_NONE (0 << 8) /* Normal (non-loop) */ 124 #define GTMPSC_MMCR_LO_LPBK_LOOP (1 << 8) /* Loop Back */ 125 #define GTMPSC_MMCR_LO_LPBK_ECHO (2 << 8) /* Echo */ 126 #define GTMPSC_MMCR_LO_LPBK_LBE (3 << 8) /* Loop Back and Echo */ 127 #define GTMPSC_MMCR_LO_NLM BIT(10) /* Null Modem */ 128 #define GTMPSC_MMCR_LO_RESb BIT(11) 129 #define GTMPSC_MMCR_LO_TSYN BIT(12) /* Transmitter sync to Rcvr. */ 130 #define GTMPSC_MMCR_LO_RESc BIT(13) 131 #define GTMPSC_MMCR_LO_TSNS_MASK BITS(15,14) /* Transmit Sense */ 132 #define GTMPSC_MMCR_LO_TSNS_INF (0 << 14) /* Infinite */ 133 #define GTMPSC_MMCR_LO_TIDL BIT(16) /* TX Idles */ 134 #define GTMPSC_MMCR_LO_RTSM BIT(17) /* RTS Mode */ 135 #define GTMPSC_MMCR_LO_RESd BIT(18) 136 #define GTMPSC_MMCR_LO_CTSS BIT(19) /* CTS Sampling mode */ 137 #define GTMPSC_MMCR_LO_CDS BIT(20) /* CD Sampling mode */ 138 #define GTMPSC_MMCR_LO_CTSM BIT(21) /* CTS operating Mode */ 139 #define GTMPSC_MMCR_LO_CDM BIT(22) /* CD operating Mode */ 140 #define GTMPSC_MMCR_LO_CRCM_MASK BITS(25,23) /* CRC Mode */ 141 #define GTMPSC_MMCR_LO_CRCM_NONE (0 << 23) /* CRC Mode */ 142 #define GTMPSC_MMCR_LO_RESe BITS(27,26) 143 #define GTMPSC_MMCR_LO_TRVD BIT(28) /* Transmit Reverse Data */ 144 #define GTMPSC_MMCR_LO_RRVD BIT(29) /* Receive Reverse Data */ 145 #define GTMPSC_MMCR_LO_RESf BIT(30) 146 #define GTMPSC_MMCR_LO_GDE BIT(31) /* Glitch Detect Enable */ 147 #define GTMPSC_MMCR_LO_RES \ 148 (GTMPSC_MMCR_LO_RESa|GTMPSC_MMCR_LO_RESb|GTMPSC_MMCR_LO_RESc \ 149 |GTMPSC_MMCR_LO_RESd|GTMPSC_MMCR_LO_RESe|GTMPSC_MMCR_LO_RESf) 150 /* 151 * MPSC Main Configuration Register HI bits 152 */ 153 #define GTMPSC_MMCR_HI_TCI BIT(0) /* TX Clock Invert */ 154 #define GTMPSC_MMCR_HI_TINV BIT(1) /* TX Bitstream Inversion */ 155 #define GTMPSC_MMCR_HI_TPL BITS(4,2) /* TX Preable Length */ 156 #define GTMPSC_MMCR_HI_TPL_NONE 0 /* no TX Preable (default) */ 157 #define GTMPSC_MMCR_HI_TPL_16 (6 << 2) /* 16 byte preamble */ 158 #define GTMPSC_MMCR_HI_TPPT_MASK BITS(8,5) /* TX Preable Pattern */ 159 #define GTMPSC_MMCR_HI_TPPT_NONE (0 << 5) /* TX Preable Pattern */ 160 #define GTMPSC_MMCR_HI_TCDV_MASK BITS(10,9) /* TX Clock Divide */ 161 #define GTMPSC_MMCR_HI_TCDV_1X (0 << 9) /* 1x clock mode */ 162 #define GTMPSC_MMCR_HI_TCDV_8X (1 << 9) /* 8x clock mode */ 163 #define GTMPSC_MMCR_HI_TCDV_16X (2 << 9) /* 16x clock mode */ 164 #define GTMPSC_MMCR_HI_TCDV_32X (3 << 9) /* 32x clock mode */ 165 #define GTMPSC_MMCR_HI_TDEC_MASK BITS(13,11) /* TX Encoder */ 166 #define GTMPSC_MMCR_HI_TDEC_NRZ (0 << 9) /* NRZ (default) */ 167 #define GTMPSC_MMCR_HI_TDEC_NRZI (1 << 9) /* NRZI (mark) */ 168 #define GTMPSC_MMCR_HI_TDEC_FM0 (2 << 9) /* FM0 */ 169 #define GTMPSC_MMCR_HI_TDEC_MAN (4 << 9) /* Manchester */ 170 #define GTMPSC_MMCR_HI_TDEC_DMAN (6 << 9) /* Differential Manchester */ 171 /* all other values rsvd. */ 172 #define GTMPSC_MMCR_HI_RESa BITS(15,14) 173 #define GTMPSC_MMCR_HI_RINV BIT(16) /* RX Bitstream Inversion */ 174 #define GTMPSC_MMCR_HI_GDW BITS(20,17) /* Clock Glitch Width */ 175 #define GTMPSC_MMCR_HI_RESb BIT(21) 176 #define GTMPSC_MMCR_HI_RDW BIT(22) /* Reveive Data Width */ 177 #define GTMPSC_MMCR_HI_RSYL_MASK BITS(24,23) /* Reveive Sync Width */ 178 #define GTMPSC_MMCR_HI_RSYL_EXT (0 << 23) /* External sync */ 179 #define GTMPSC_MMCR_HI_RSYL_4BIT (1 << 23) /* 4-bit sync */ 180 #define GTMPSC_MMCR_HI_RSYL_8BIT (2 << 23) /* 8-bit sync */ 181 #define GTMPSC_MMCR_HI_RSYL_16BIT (3 << 23) /* 16-bit sync */ 182 #define GTMPSC_MMCR_HI_RCDV_MASK BITS(26,25) /* Receive Clock Divider */ 183 #define GTMPSC_MMCR_HI_RCDV_1X (0 << 25) /* 1x clock mode (default) */ 184 #define GTMPSC_MMCR_HI_RCDV_8X (1 << 25) /* 8x clock mode (default) */ 185 #define GTMPSC_MMCR_HI_RCDV_16X (2 << 25) /* 16x clock mode (default) */ 186 #define GTMPSC_MMCR_HI_RCDV_32X (3 << 25) /* 16x clock mode (default) */ 187 #define GTMPSC_MMCR_HI_RENC_MASK BITS(29,27) /* Receive Encoder */ 188 #define GTMPSC_MMCR_HI_RENC_NRZ (0 << 27) /* NRZ (default) */ 189 #define GTMPSC_MMCR_HI_RENC_NRZI (1 << 27) /* NRZI */ 190 #define GTMPSC_MMCR_HI_RENC_FM0 (2 << 27) /* FM0 */ 191 #define GTMPSC_MMCR_HI_RENC_MAN (4 << 27) /* Manchester */ 192 #define GTMPSC_MMCR_HI_RENC_DMAN (6 << 27) /* Differential Manchester */ 193 /* all other values rsvd. */ 194 #define GTMPSC_MMCR_HI_SEDG_MASK BITS(31,30) /* Sync Clock Edge */ 195 #define GTMPSC_MMCR_HI_SEDG_BOTH (0 << 30) /* rising and falling (dflt) */ 196 #define GTMPSC_MMCR_HI_SEDG_RISE (1 << 30) /* rising edge */ 197 #define GTMPSC_MMCR_HI_SEDG_FALL (2 << 30) /* falling edge */ 198 #define GTMPSC_MMCR_HI_SEDG_NONE (3 << 30) /* no adjustment */ 199 /* 200 * SDMAx Command/Status Register bits for UART Mode, RX 201 * 202 * XXX these belong in sdmareg.h ? 203 */ 204 #define SDMA_CSR_RX_PE BIT(0) /* Parity Error */ 205 #define SDMA_CSR_RX_CDL BIT(1) /* Carrier Detect Loss */ 206 #define SDMA_CSR_RX_RESa BIT(2) 207 #define SDMA_CSR_RX_FR BIT(3) /* Framing Error */ 208 #define SDMA_CSR_RX_RESb BITS(5,4) 209 #define SDMA_CSR_RX_OR BIT(6) /* Data Overrun */ 210 #define SDMA_CSR_RX_RESc BITS(8,7) 211 #define SDMA_CSR_RX_BR BIT(9) /* Break Received */ 212 #define SDMA_CSR_RX_MI BIT(10) /* Max Idle */ 213 #define SDMA_CSR_RX_ADDR BIT(11) /* Address */ 214 #define SDMA_CSR_RX_AMATCH BIT(12) /* Address match */ 215 #define SDMA_CSR_RX_CT BIT(13) /* Transparency Control char */ 216 #define SDMA_CSR_RX_C BIT(14) /* Control char */ 217 #define SDMA_CSR_RX_ES BIT(15) /* Error Summary */ 218 #define SDMA_CSR_RX_L BIT(16) /* Last */ 219 #define SDMA_CSR_RX_F BIT(17) /* First */ 220 #define SDMA_CSR_RX_RESd BITS(22,18) 221 #define SDMA_CSR_RX_EI BIT(23) /* Enable Interrupt */ 222 #define SDMA_CSR_RX_RESe BITS(29,24) 223 #define SDMA_CSR_RX_AUTO BIT(30) /* Auto Mode */ 224 #define SDMA_CSR_RX_OWN BIT(31) /* Owner */ 225 #define SDMA_CSR_RX_RES (SDMA_CSR_RX_RESa|SDMA_CSR_RX_RESb|SDMA_CSR_RX_RESc \ 226 |SDMA_CSR_RX_RESd|SDMA_CSR_RX_RESe) 227 /* 228 * SDMAx Command/Status Register bits for UART Mode, TX 229 */ 230 #define SDMA_CSR_TX_RESa BIT(0) 231 #define SDMA_CSR_TX_CTSL BIT(1) /* CTS Loss */ 232 #define SDMA_CSR_TX_RESb BITS(14,2) 233 #define SDMA_CSR_TX_ES BIT(15) /* Error Summary */ 234 #define SDMA_CSR_TX_L BIT(16) /* Last */ 235 #define SDMA_CSR_TX_F BIT(17) /* First */ 236 #define SDMA_CSR_TX_P BIT(18) /* Preamble */ 237 #define SDMA_CSR_TX_ADDR BIT(19) /* Address */ 238 #define SDMA_CSR_TX_NS BIT(20) /* No Stop Bit */ 239 #define SDMA_CSR_TX_RESc BITS(22,21) 240 #define SDMA_CSR_TX_EI BIT(23) /* Enable Interrupt */ 241 #define SDMA_CSR_TX_RESd BITS(29,24) 242 #define SDMA_CSR_TX_AUTO BIT(30) /* Auto Mode */ 243 #define SDMA_CSR_TX_OWN BIT(31) /* Owner */ 244 #define SDMA_CSR_TX_RES \ 245 (SDMA_CSR_TX_RESa|SDMA_CSR_TX_RESb|SDMA_CSR_TX_RESc|SDMA_CSR_TX_RESd) 246 /* 247 * MPSCx Protocol Configuration Register for UART Mode 248 */ 249 #define GTMPSC_MPCR_RESa BITS(5,0) 250 #define GTMPSC_MPCR_DRT BIT(6) /* Disable Rx on Tx */ 251 #define GTMPSC_MPCR_ISO BIT(7) /* Isochronous Mode */ 252 #define GTMPSC_MPCR_RZS BIT(8) /* Rx Zero Stop Bit(s) */ 253 #define GTMPSC_MPCR_FRZ BIT(9) /* Freeze Tx */ 254 #define GTMPSC_MPCR_UM_MASK BITS(11,10) /* UART Mode mask */ 255 #define GTMPSC_MPCR_UM_NORM (0 << 10) /* Normal UART Mode */ 256 #define GTMPSC_MPCR_UM_MDROP (1 << 10) /* Multi-Drop UART Mode */ 257 /* other values are resvd. */ 258 #define GTMPSC_MPCR_CLMASK BITS(13,12) /* Character Length mask */ 259 #define GTMPSC_MPCR_CL_5 (0 << 12) /* 5 data bits */ 260 #define GTMPSC_MPCR_CL_6 (1 << 12) /* 6 data bits */ 261 #define GTMPSC_MPCR_CL_7 (2 << 12) /* 7 data bits */ 262 #define GTMPSC_MPCR_CL_8 (3 << 12) /* 8 data bits */ 263 #define GTMPSC_MPCR_SBL_1 (0 << 14) /* 1 stop bit */ 264 #define GTMPSC_MPCR_SBL_2 (1 << 14) /* 2 stop bits */ 265 #define GTMPSC_MPCR_FLC_NORM 0x0 /* Normal Flow Ctl mode */ 266 #define GTMPSC_MPCR_FLC_ASYNC BIT(15) /* Asynchronous Flow Ctl mode */ 267 #define GTMPSC_MPCR_RESb BITS(31,16) 268 #define GTMPSC_MPCR_RES (GTMPSC_MPCR_RESa|GTMPSC_MPCR_RESb) 269 /* 270 * MPSC Channel Register 1 for UART Mode "Break/Stuff" 271 */ 272 #define GTMPSC_CHR1_TCS BITS(7,0) /* Constrol Stuff Character */ 273 #define GTMPSC_CHR1_BRK BITS(23,16) /* Break Count */ 274 #define GTMPSC_CHR1_RES BITS(15,8)|BITS(31,24) 275 /* 276 * MPSC Channel Register 2 for UART Mode "Command" 277 */ 278 #define GTMPSC_CHR2_RESa BIT(0) 279 #define GTMPSC_CHR2_TEV BIT(1) /* Tx Enb. Vert. Redundancy */ 280 #define GTMPSC_CHR2_TPM_MASK BITS(3,2) /* Tx Parity Mode mask */ 281 #define GTMPSC_CHR2_TPM_ODD (0 << 2) /* Odd Tx Parity */ 282 #define GTMPSC_CHR2_TPM_LOW (1 << 2) /* Low (always 0) Tx Parity */ 283 #define GTMPSC_CHR2_TPM_EVEN (2 << 2) /* Even Tx Parity */ 284 #define GTMPSC_CHR2_TPM_HIGH (3 << 2) /* High (always 1) Tx Parity */ 285 #define GTMPSC_CHR2_RESb BITS(6,4) 286 #define GTMPSC_CHR2_TXABORT BIT(7) /* Tx Abort */ 287 #define GTMPSC_CHR2_RESc BIT(8) 288 #define GTMPSC_CHR2_TCS BIT(9) /* Tx TCS Char */ 289 #define GTMPSC_CHR2_RESd BITS(16,10) 290 #define GTMPSC_CHR2_REC BIT(17) /* Rx Enb. Vert. Redundancy */ 291 #define GTMPSC_CHR2_RPM_MASK BITS(19,18) /* Rx Parity Mode mask */ 292 #define GTMPSC_CHR2_RPM_ODD (0 << 18) /* Odd Rx Parity */ 293 #define GTMPSC_CHR2_RPM_LOW (1 << 18) /* Low (always 0) Rx Parity */ 294 #define GTMPSC_CHR2_RPM_EVEN (2 << 18) /* Even Rx Parity */ 295 #define GTMPSC_CHR2_RPM_HIGH (3 << 18) /* High (always 1) Rx Parity */ 296 #define GTMPSC_CHR2_RESe BITS(22,20) 297 #define GTMPSC_CHR2_RXABORT BIT(23) /* Rx Abort */ 298 #define GTMPSC_CHR2_RESf BIT(24) 299 #define GTMPSC_CHR2_CRD BIT(25) /* Close RX Descriptor */ 300 #define GTMPSC_CHR2_RESg BITS(30,26) 301 #define GTMPSC_CHR2_EH BIT(31) /* Enter Hunt */ 302 #define GTMPSC_CHR2_RES \ 303 (GTMPSC_CHR2_RESa|GTMPSC_CHR2_RESb|GTMPSC_CHR2_RESc| \ 304 GTMPSC_CHR2_RESd|GTMPSC_CHR2_RESe|GTMPSC_CHR2_RESf| \ 305 GTMPSC_CHR2_RESg) 306 /* 307 * MPSC Channel Register 3 for UART Mode "Max Idle" 308 */ 309 #define GTMPSC_CHR3_MIR BITS(15,0) /* Max Idle Char count */ 310 #define GTMPSC_CHR3_RES BITS(31,16) 311 /* 312 * MPSC Channel Register 4 for UART Mode "Control Filtering" 313 */ 314 #define GTMPSC_CHR4_CFR BITS(7,0) /* Control bit compare enable */ 315 #define GTMPSC_CHR4_RES BITS(31,8) 316 /* 317 * MPSC Channel Registers 5..8 for UART Mode "UART Control Character" 318 * 319 * NOTE: two 16 bit CHRCC fields exist in each of Channel Registers 5..8 320 */ 321 #define GTMPSC_CHRCC_SHIFT 16 322 #define GTMPSC_CHRCC_CHAR BITS(7,0) /* the control character */ 323 #define GTMPSC_CHRCC_RES BITS(11,8) 324 #define GTMPSC_CHRCC_INT BIT(12) /* Interrupt */ 325 #define GTMPSC_CHRCC_CO BIT(13) /* ISO 3309 Control Octet */ 326 #define GTMPSC_CHRCC_R BIT(14) /* Reject */ 327 #define GTMPSC_CHRCC_V BIT(15) /* Valid */ 328 /* 329 * MPSC Channel Register 9 for UART Mode "Address" (for multidrop operation) 330 */ 331 #define GTMPSC_CHR9_AD1 BITS(7,0) /* address #1 */ 332 #define GTMPSC_CHR9_RESa BITS(14,8) 333 #define GTMPSC_CHR9_MODE1 BIT(15) /* mode #1 */ 334 #define GTMPSC_CHR9_AD2 BITS(23,16) /* address #2 */ 335 #define GTMPSC_CHR9_RESb BITS(30,24) 336 #define GTMPSC_CHR9_MODE2 BIT(31) /* mode #2 */ 337 #define GTMPSC_CHR9_RES (GTMPSC_CHR9_RESa|GTMPSC_CHR9_RESb) 338 /* 339 * MPSC Channel Register 10 for UART Mode "Event Status" 340 */ 341 #define GTMPSC_CHR10_CTS BIT(0) /* Clear To Send */ 342 #define GTMPSC_CHR10_CD BIT(1) /* Carrier Detect */ 343 #define GTMPSC_CHR10_RESa BIT(2) 344 #define GTMPSC_CHR10_TIDLE BIT(3) /* Tx in Idle State */ 345 #define GTMPSC_CHR10_RESb BIT(4) 346 #define GTMPSC_CHR10_RHS BIT(5) /* Rx in HUNT State */ 347 #define GTMPSC_CHR10_RESc BIT(6) 348 #define GTMPSC_CHR10_RLS BIT(7) /* Rx Line STatus */ 349 #define GTMPSC_CHR10_RESd BITS(10,8) 350 #define GTMPSC_CHR10_RLIDL BIT(11) /* Rx IDLE Line */ 351 #define GTMPSC_CHR10_RESe BITS(15,12) 352 #define GTMPSC_CHR10_RCRn BITS(23,16) /* Received Control Char # */ 353 #define GTMPSC_CHR10_RESf BITS(31,24) 354 #define GTMPSC_CHR10_RES \ 355 (GTMPSC_CHR10_RESa|GTMPSC_CHR10_RESb|GTMPSC_CHR10_RESc \ 356 |GTMPSC_CHR10_RESd|GTMPSC_CHR10_RESe|GTMPSC_CHR10_RESf) 357 358 359 #endif /* _GTMPSCREG_H */ 360