1 /* $NetBSD: gtintrvar.h,v 1.1 2010/04/28 13:51:56 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2009 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _MARVELL_GTINTRVAR_H_ 28 #define _MARVELL_GTINTRVAR_H_ 29 30 #include <dev/marvell/gtreg.h> 31 32 /* 33 * Main Interrupt related functions 34 */ 35 36 static __inline uint32_t 37 discovery_enable_intr(struct gt_softc *sc, int irq) 38 { 39 bus_size_t reg; 40 uint32_t cim; 41 42 reg = (irq < 32) ? ICR_CIM_LO : ICR_CIM_HI; 43 cim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg); 44 cim |= 1 << (irq & 31); 45 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, cim); 46 return cim; 47 } 48 49 static __inline uint32_t 50 discovery_disable_intr(struct gt_softc *sc, int irq) 51 { 52 bus_size_t reg; 53 uint32_t cim; 54 55 reg = (irq < 32) ? ICR_CIM_LO : ICR_CIM_HI; 56 cim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg); 57 cim &= ~(1 << (irq & 31)); 58 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, cim); 59 return cim; 60 } 61 62 static __inline int 63 discovery_mic_low(struct gt_softc *sc) 64 { 65 66 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, ICR_MIC_LO); 67 } 68 69 static __inline int 70 discovery_mic_high(struct gt_softc *sc) 71 { 72 73 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, ICR_MIC_HI); 74 } 75 76 77 /* 78 * GPP Interrupt related functions 79 */ 80 81 static __inline uint32_t 82 discovery_gpp_enable_intr(struct gt_softc *sc, int pin) 83 { 84 uint32_t gppim; 85 86 gppim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask); 87 gppim |= 1 << pin; 88 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask, gppim); 89 return gppim; 90 } 91 92 static __inline uint32_t 93 discovery_gpp_disable_intr(struct gt_softc *sc, int pin) 94 { 95 uint32_t gppim; 96 97 gppim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask); 98 gppim &= ~(1 << pin); 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask, gppim); 100 return gppim; 101 } 102 103 static __inline void 104 discovery_gpp_clear_cause(struct gt_softc *sc, int pin) 105 { 106 uint32_t gppic; 107 108 gppic = 109 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Cause); 110 gppic &= ~(1 << pin); 111 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Cause, 112 gppic); 113 } 114 115 static __inline int 116 discovery_gpp_cause(struct gt_softc *sc) 117 { 118 119 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Cause); 120 } 121 122 static __inline int 123 discovery_gpp_mask(struct gt_softc *sc) 124 { 125 126 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask); 127 } 128 #endif /* _MARVELL_GTINTRVAR_H_ */ 129