1 /* $NetBSD: gtbrgreg.h,v 1.1 2003/03/05 22:08:18 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gtbrgreg.h - register defines for GT-64260 Baud Rate Generator 42 * 43 * creation Thu Apr 12 21:47:54 PDT 2001 cliff 44 */ 45 46 #ifndef _GTBRGREG_H 47 #define _GTBRGREG_H 48 49 #ifndef BIT 50 #define BIT(bitno) (1U << (bitno)) 51 #endif 52 #ifndef BITS 53 #define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo))) 54 #endif 55 56 57 /******************************************************************************* 58 * 59 * BRG register address offsets relative to the base mapping 60 */ 61 #define BRG_BCR0 0xb200 /* BRG0 Configuration Register */ 62 #define BRG_BTR0 0xb204 /* BRG0 Baud Tuning Register */ 63 #define BRG_BCR1 0xb208 /* BRG1 Configuration Register */ 64 #define BRG_BTR1 0xb20c /* BRG1 Baud Tuning Register */ 65 #define BRG_BCR2 0xb210 /* BRG2 Configuration Register */ 66 #define BRG_BTR2 0xb214 /* BRG2 Baud Tuning Register */ 67 #define BRG_CAUSE 0xb834 /* BRG Cause Register */ 68 #define BRG_MASK 0xb8b4 /* BRG Cause Register */ 69 70 /******************************************************************************* 71 * 72 * BRG register values & bit defines 73 */ 74 /* 75 * BRG Configuration Register bits 76 */ 77 #define BRG_BCR_CDV BITS(15,0) /* Count Down Value */ 78 #define BRG_BCR_EN BIT(16) /* Enable BRG */ 79 #define BRG_BCR_RST BIT(17) /* Reset BRG */ 80 #define BRG_BCR_CLKS_MASK BITS(22,18) /* Clock Source */ 81 #define BRG_BCR_CLKS_BCLKIN (0 << 18) /* from MPP */ 82 #define BRG_BCR_CLKS_SCLK0 (2 << 18) /* from S0 port */ 83 #define BRG_BCR_CLKS_TSCLK0 (3 << 18) /* from S0 port */ 84 #define BRG_BCR_CLKS_SCLK1 (6 << 18) /* from S1 port */ 85 #define BRG_BCR_CLKS_TSCLK1 (7 << 18) /* from S1 port */ 86 #define BRG_BCR_CLKS_TCLK (8 << 18) /* "Tclk" ??? */ 87 /* all other values resvd. */ 88 #define BRG_BCR_RES BITS(31,23) 89 /* 90 * BRG Baud Tuning Register bits 91 */ 92 #define BRG_BTR_CUV BITS(15,0) /* Count Up Value */ 93 #define BRG_BTR_RES BITS(31,16) 94 /* 95 * BRG Cause and Mask interrupt Register bits 96 */ 97 #define BRG_INTR_BTR0 BIT(0) /* Baud Tuning 0 irpt. */ 98 #define BRG_INTR_BTR1 BIT(1) /* Baud Tuning 1 irpt. */ 99 #define BRG_INTR_BTR2 BIT(2) /* Baud Tuning 2 irpt. */ 100 #define BRG_INTR_RES BITS(31,3) 101 102 #endif /* _GTBRGREG_H */ 103