1 /* $NetBSD: gt.c,v 1.12 2005/12/24 20:27:41 perry Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gt.c -- GT system controller driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.12 2005/12/24 20:27:41 perry Exp $"); 46 47 #include "opt_marvell.h" 48 #include "locators.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/cdefs.h> 53 #include <sys/extent.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 58 #define _BUS_SPACE_PRIVATE 59 #define _BUS_DMA_PRIVATE 60 #include <machine/bus.h> 61 62 #include <powerpc/spr.h> 63 #include <powerpc/oea/hid.h> 64 65 #include <dev/marvell/gtreg.h> 66 #include <dev/marvell/gtintrreg.h> 67 #include <dev/marvell/gtvar.h> 68 #include <dev/marvell/gtethreg.h> 69 70 #ifdef DEBUG 71 #include <sys/systm.h> /* for Debugger() */ 72 #endif 73 74 #if ((GT_MPP_WATCHDOG & 0xf0f0f0f0) != 0) 75 # error /* unqualified: configuration botch! */ 76 #endif 77 #if ((GT_MPP_WATCHDOG & GT_MPP_INTERRUPTS) != 0) 78 # error /* conflict: configuration botch! */ 79 #endif 80 81 static void gt_comm_intr_enb(struct gt_softc *); 82 static void gt_devbus_intr_enb(struct gt_softc *); 83 #ifdef GT_ECC 84 static void gt_ecc_intr_enb(struct gt_softc *); 85 #endif 86 87 88 void gt_init_hostid (struct gt_softc *); 89 void gt_init_interrupt (struct gt_softc *); 90 static int gt_comm_intr (void *); 91 92 void gt_watchdog_init(struct gt_softc *); 93 void gt_watchdog_enable(void); 94 void gt_watchdog_disable(void); 95 void gt_watchdog_reset(void); 96 97 extern struct cfdriver gt_cd; 98 99 static int gtfound = 0; 100 101 static struct gt_softc *gt_watchdog_sc = 0; 102 static int gt_watchdog_state = 0; 103 104 int 105 gt_cfprint (void *aux, const char *pnp) 106 { 107 struct gt_attach_args *ga = aux; 108 109 if (pnp) { 110 aprint_normal("%s at %s", ga->ga_name, pnp); 111 } 112 113 aprint_normal(" unit %d", ga->ga_unit); 114 return (UNCONF); 115 } 116 117 118 static int 119 gt_cfsearch(struct device *parent, struct cfdata *cf, 120 const int *ldesc, void *aux) 121 { 122 struct gt_softc *gt = (struct gt_softc *) parent; 123 struct gt_attach_args ga; 124 125 ga.ga_name = cf->cf_name; 126 ga.ga_dmat = gt->gt_dmat; 127 ga.ga_memt = gt->gt_memt; 128 ga.ga_memh = gt->gt_memh; 129 ga.ga_unit = cf->cf_loc[GTCF_UNIT]; 130 131 if (config_match(parent, cf, &ga) > 0) 132 config_attach(parent, cf, &ga, gt_cfprint); 133 134 return (0); 135 } 136 137 void 138 gt_attach_common(struct gt_softc *gt) 139 { 140 uint32_t cpucfg, cpumode, cpumstr; 141 #ifdef DEBUG 142 uint32_t loaddr, hiaddr; 143 #endif 144 145 gtfound = 1; 146 147 cpumode = gt_read(gt, GT_CPU_Mode); 148 aprint_normal(": id %d", GT_CPUMode_MultiGTID_GET(cpumode)); 149 if (cpumode & GT_CPUMode_MultiGT) 150 aprint_normal (" (multi)"); 151 switch (GT_CPUMode_CPUType_GET(cpumode)) { 152 case 4: aprint_normal(", 60x bus"); break; 153 case 5: aprint_normal(", MPX bus"); break; 154 default: aprint_normal(", %#x(?) bus", GT_CPUMode_CPUType_GET(cpumode)); break; 155 } 156 157 cpumstr = gt_read(gt, GT_CPU_Master_Ctl); 158 cpumstr &= ~(GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock); 159 #if 0 160 cpumstr |= GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock; 161 #endif 162 gt_write(gt, GT_CPU_Master_Ctl, cpumstr); 163 164 switch (cpumstr & (GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock)) { 165 case 0: break; 166 case GT_CPUMstrCtl_CleanBlock: aprint_normal(", snoop=clean"); break; 167 case GT_CPUMstrCtl_FlushBlock: aprint_normal(", snoop=flush"); break; 168 case GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock: 169 aprint_normal(", snoop=clean&flush"); break; 170 } 171 aprint_normal(" wdog=%#x,%#x\n", 172 gt_read(gt, GT_WDOG_Config), 173 gt_read(gt, GT_WDOG_Value)); 174 175 #if DEBUG 176 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS0_Low_Decode)); 177 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS0_High_Decode)); 178 aprint_normal("%s: scs[0]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 179 180 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS1_Low_Decode)); 181 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS1_High_Decode)); 182 aprint_normal("%s: scs[1]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 183 184 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS2_Low_Decode)); 185 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS2_High_Decode)); 186 aprint_normal("%s: scs[2]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 187 188 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS3_Low_Decode)); 189 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS3_High_Decode)); 190 aprint_normal("%s: scs[3]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 191 192 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS0_Low_Decode)); 193 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS0_High_Decode)); 194 aprint_normal("%s: cs[0]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 195 196 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS1_Low_Decode)); 197 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS1_High_Decode)); 198 aprint_normal("%s: cs[1]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 199 200 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS2_Low_Decode)); 201 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS2_High_Decode)); 202 aprint_normal("%s: cs[2]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 203 204 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS3_Low_Decode)); 205 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS3_High_Decode)); 206 aprint_normal("%s: cs[3]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 207 208 loaddr = GT_LowAddr_GET(gt_read(gt, GT_BootCS_Low_Decode)); 209 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_BootCS_High_Decode)); 210 aprint_normal("%s: bootcs=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 211 212 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_IO_Low_Decode)); 213 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_IO_High_Decode)); 214 aprint_normal("%s: pci0io=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 215 216 loaddr = gt_read(gt, GT_PCI0_IO_Remap); 217 aprint_normal("remap=%#010x\n", loaddr); 218 219 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem0_Low_Decode)); 220 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem0_High_Decode)); 221 aprint_normal("%s: pci0mem[0]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 222 223 loaddr = gt_read(gt, GT_PCI0_Mem0_Remap_Low); 224 hiaddr = gt_read(gt, GT_PCI0_Mem0_Remap_High); 225 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 226 227 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem1_Low_Decode)); 228 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem1_High_Decode)); 229 aprint_normal("%s: pci0mem[1]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 230 231 loaddr = gt_read(gt, GT_PCI0_Mem1_Remap_Low); 232 hiaddr = gt_read(gt, GT_PCI0_Mem1_Remap_High); 233 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 234 235 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem2_Low_Decode)); 236 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem2_High_Decode)); 237 aprint_normal("%s: pci0mem[2]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 238 239 loaddr = gt_read(gt, GT_PCI0_Mem2_Remap_Low); 240 hiaddr = gt_read(gt, GT_PCI0_Mem2_Remap_High); 241 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 242 243 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem3_Low_Decode)); 244 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem3_High_Decode)); 245 aprint_normal("%s: pci0mem[3]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 246 247 loaddr = gt_read(gt, GT_PCI0_Mem3_Remap_Low); 248 hiaddr = gt_read(gt, GT_PCI0_Mem3_Remap_High); 249 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 250 251 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_IO_Low_Decode)); 252 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_IO_High_Decode)); 253 aprint_normal("%s: pci1io=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 254 255 loaddr = gt_read(gt, GT_PCI1_IO_Remap); 256 aprint_normal("remap=%#010x\n", loaddr); 257 258 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem0_Low_Decode)); 259 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem0_High_Decode)); 260 aprint_normal("%s: pci1mem[0]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 261 262 loaddr = gt_read(gt, GT_PCI1_Mem0_Remap_Low); 263 hiaddr = gt_read(gt, GT_PCI1_Mem0_Remap_High); 264 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 265 266 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem1_Low_Decode)); 267 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem1_High_Decode)); 268 aprint_normal("%s: pci1mem[1]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 269 270 loaddr = gt_read(gt, GT_PCI1_Mem1_Remap_Low); 271 hiaddr = gt_read(gt, GT_PCI1_Mem1_Remap_High); 272 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 273 274 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem2_Low_Decode)); 275 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem2_High_Decode)); 276 aprint_normal("%s: pci1mem[2]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 277 278 loaddr = gt_read(gt, GT_PCI1_Mem2_Remap_Low); 279 hiaddr = gt_read(gt, GT_PCI1_Mem2_Remap_High); 280 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 281 282 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem3_Low_Decode)); 283 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem3_High_Decode)); 284 aprint_normal("%s: pci1mem[3]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 285 286 loaddr = gt_read(gt, GT_PCI1_Mem3_Remap_Low); 287 hiaddr = gt_read(gt, GT_PCI1_Mem3_Remap_High); 288 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 289 290 loaddr = GT_LowAddr_GET(gt_read(gt, GT_Internal_Decode)); 291 aprint_normal("%s: internal=%#10x-%#10x\n", gt->gt_dev.dv_xname, 292 loaddr, loaddr+256*1024); 293 294 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU0_Low_Decode)); 295 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU0_High_Decode)); 296 aprint_normal("%s: cpu0=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 297 298 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU1_Low_Decode)); 299 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU1_High_Decode)); 300 aprint_normal("%s: cpu1=%#10x-%#10x", gt->gt_dev.dv_xname, loaddr, hiaddr); 301 #endif 302 303 aprint_normal("%s:", gt->gt_dev.dv_xname); 304 305 cpucfg = gt_read(gt, GT_CPU_Cfg); 306 cpucfg |= GT_CPUCfg_ConfSBDis; /* per errata #46 */ 307 cpucfg |= GT_CPUCfg_AACKDelay; /* per restriction #18 */ 308 gt_write(gt, GT_CPU_Cfg, cpucfg); 309 if (cpucfg & GT_CPUCfg_Pipeline) 310 aprint_normal(" pipeline"); 311 if (cpucfg & GT_CPUCfg_AACKDelay) 312 aprint_normal(" aack-delay"); 313 if (cpucfg & GT_CPUCfg_RdOOO) 314 aprint_normal(" read-ooo"); 315 if (cpucfg & GT_CPUCfg_IOSBDis) 316 aprint_normal(" io-sb-dis"); 317 if (cpucfg & GT_CPUCfg_ConfSBDis) 318 aprint_normal(" conf-sb-dis"); 319 if (cpucfg & GT_CPUCfg_ClkSync) 320 aprint_normal(" clk-sync"); 321 aprint_normal("\n"); 322 323 gt_init_hostid(gt); 324 325 gt_watchdog_init(gt); 326 327 gt_init_interrupt(gt); 328 329 #ifdef GT_ECC 330 gt_ecc_intr_enb(gt); 331 #endif 332 333 gt_comm_intr_enb(gt); 334 gt_devbus_intr_enb(gt); 335 336 gt_watchdog_disable(); 337 config_search_ia(gt_cfsearch, >->gt_dev, "gt", NULL); 338 gt_watchdog_service(); 339 gt_watchdog_enable(); 340 } 341 342 void 343 gt_init_hostid(struct gt_softc *gt) 344 { 345 346 hostid = 1; /* XXX: Used by i2c; needs work -- AKB */ 347 } 348 349 void 350 gt_init_interrupt(struct gt_softc *gt) 351 { 352 u_int32_t mppirpts = GT_MPP_INTERRUPTS; /* from config */ 353 u_int32_t r; 354 u_int32_t mppbit; 355 u_int32_t mask; 356 u_int32_t mppsel; 357 u_int32_t regoff; 358 359 gt_write(gt, ICR_CIM_LO, 0); 360 gt_write(gt, ICR_CIM_HI, 0); 361 362 /* 363 * configure the GPP interrupts: 364 * - set the configured MPP pins in GPP mode 365 * - set the configured GPP pins to input, active low, interrupt enbl 366 */ 367 #ifdef DEBUG 368 printf("%s: mpp cfg ", gt->gt_dev.dv_xname); 369 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) 370 printf("%#x ", gt_read(gt, regoff)); 371 printf(", mppirpts 0x%x\n", mppirpts); 372 #endif 373 mppbit = 0x1; 374 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) { 375 mask = 0; 376 for (mppsel = 0xf; mppsel; mppsel <<= 4) { 377 if (mppirpts & mppbit) 378 mask |= mppsel; 379 mppbit <<= 1; 380 } 381 if (mask) { 382 r = gt_read(gt, regoff); 383 r &= ~mask; 384 gt_write(gt, regoff, r); 385 } 386 } 387 388 r = gt_read(gt, GT_GPP_IO_Control); 389 r &= ~mppirpts; 390 gt_write(gt, GT_GPP_IO_Control, r); 391 392 r = gt_read(gt, GT_GPP_Level_Control); 393 r |= mppirpts; 394 gt_write(gt, GT_GPP_Level_Control, r); 395 396 r = gt_read(gt, GT_GPP_Interrupt_Mask); 397 r |= mppirpts; 398 gt_write(gt, GT_GPP_Interrupt_Mask, r); 399 } 400 401 uint32_t 402 gt_read_mpp (void) 403 { 404 return gt_read((struct gt_softc *)gt_cd.cd_devs[0], GT_GPP_Value); 405 } 406 407 #if 0 408 int 409 gt_bs_extent_init(struct discovery_bus_space *bs, char *name) 410 { 411 u_long start, end; 412 int i, j, error; 413 414 if (bs->bs_nregion == 0) { 415 bs->bs_extent = extent_create(name, 0xffffffffUL, 0xffffffffUL, 416 M_DEVBUF, NULL, 0, EX_NOCOALESCE|EX_WAITOK); 417 KASSERT(bs->bs_extent != NULL); 418 return 0; 419 } 420 /* 421 * Find the top and bottoms of this bus space. 422 */ 423 start = bs->bs_regions[0].br_start; 424 end = bs->bs_regions[0].br_end; 425 #ifdef DEBUG 426 if (gtpci_debug > 1) 427 printf("gtpci_bs_extent_init: %s: region %d: %#lx-%#lx\n", 428 name, 0, bs->bs_regions[0].br_start, 429 bs->bs_regions[0].br_end); 430 #endif 431 for (i = 1; i < bs->bs_nregion; i++) { 432 if (bs->bs_regions[i].br_start < start) 433 start = bs->bs_regions[i].br_start; 434 if (bs->bs_regions[i].br_end > end) 435 end = bs->bs_regions[i].br_end; 436 #ifdef DEBUG 437 if (gtpci_debug > 1) 438 printf("gtpci_bs_extent_init: %s: region %d:" 439 " %#lx-%#lx\n", 440 name, i, bs->bs_regions[i].br_start, 441 bs->bs_regions[i].br_end); 442 #endif 443 } 444 /* 445 * Now that we have the top and bottom limits of this 446 * bus space, create the extent map that will manage this 447 * space for us. 448 */ 449 #ifdef DEBUG 450 if (gtpci_debug > 1) 451 printf("gtpci_bs_extent_init: %s: create: %#lx-%#lx\n", 452 name, start, end); 453 #endif 454 bs->bs_extent = extent_create(name, start, end, M_DEVBUF, 455 NULL, 0, EX_NOCOALESCE|EX_WAITOK); 456 KASSERT(bs->bs_extent != NULL); 457 458 /* If there was more than one bus space region, then there 459 * might gaps in between them. Allocate the gap so that 460 * they will not be legal addresses in the extent. 461 */ 462 for (i = 0; i < bs->bs_nregion && bs->bs_nregion > 1; i++) { 463 /* Initial start is "infinity" and the inital end is 464 * is the end of this bus region. 465 */ 466 start = ~0UL; 467 end = bs->bs_regions[i].br_end; 468 /* For each region, if it starts after this region but less 469 * than the saved start, use its start address. If the start 470 * address is one past the end address, then we're done 471 */ 472 for (j = 0; j < bs->bs_nregion && start > end + 1; j++) { 473 if (i == j) 474 continue; 475 if (bs->bs_regions[j].br_start > end && 476 bs->bs_regions[j].br_start < start) 477 start = bs->bs_regions[j].br_start; 478 } 479 /* 480 * If we found a gap, allocate it away. 481 */ 482 if (start != ~0UL && start != end + 1) { 483 #ifdef DEBUG 484 if (gtpci_debug > 1) 485 printf("gtpci_bs_extent_init: %s: alloc(hole): %#lx-%#lx\n", 486 name, end + 1, start - 1); 487 #endif 488 error = extent_alloc_region(bs->bs_extent, end + 1, 489 start - (end + 1), EX_NOWAIT); 490 KASSERT(error == 0); 491 } 492 } 493 return 1; 494 } 495 #endif 496 497 /* 498 * unknown board, enable everything 499 */ 500 # define GT_CommUnitIntr_DFLT GT_CommUnitIntr_S0|GT_CommUnitIntr_S1 \ 501 |GT_CommUnitIntr_E0|GT_CommUnitIntr_E1 \ 502 |GT_CommUnitIntr_E2 503 504 static const char * const gt_comm_subunit_name[8] = { 505 "ethernet 0", 506 "ethernet 1", 507 "ethernet 2", 508 "(reserved)", 509 "MPSC 0", 510 "MPSC 1", 511 "(reserved)", 512 "(sel)", 513 }; 514 515 static int 516 gt_comm_intr(void *arg) 517 { 518 struct gt_softc *gt = (struct gt_softc *)arg; 519 u_int32_t cause; 520 u_int32_t addr; 521 unsigned int mask; 522 int i; 523 524 cause = gt_read(gt, GT_CommUnitIntr_Cause); 525 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 526 addr = gt_read(gt, GT_CommUnitIntr_ErrAddr); 527 528 printf("%s: Comm Unit irpt, cause %#x addr %#x\n", 529 gt->gt_dev.dv_xname, cause, addr); 530 531 cause &= GT_CommUnitIntr_DFLT; 532 if (cause == 0) 533 return 0; 534 535 mask = 0x7; 536 for (i=0; i<7; i++) { 537 if (cause & mask) { 538 printf("%s: Comm Unit %s:", gt->gt_dev.dv_xname, 539 gt_comm_subunit_name[i]); 540 if (cause & 1) 541 printf(" AddrMiss"); 542 if (cause & 2) 543 printf(" AccProt"); 544 if (cause & 4) 545 printf(" WrProt"); 546 printf("\n"); 547 } 548 cause >>= 4; 549 } 550 return 1; 551 } 552 553 /* 554 * gt_comm_intr_init - enable GT-64260 Comm Unit interrupts 555 */ 556 static void 557 gt_comm_intr_enb(struct gt_softc *gt) 558 { 559 u_int32_t cause; 560 561 cause = gt_read(gt, GT_CommUnitIntr_Cause); 562 if (cause) 563 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 564 gt_write(gt, GT_CommUnitIntr_Mask, GT_CommUnitIntr_DFLT); 565 (void)gt_read(gt, GT_CommUnitIntr_ErrAddr); 566 567 intr_establish(IRQ_COMM, IST_LEVEL, IPL_GTERR, gt_comm_intr, gt); 568 printf("%s: Comm Unit irpt at %d\n", gt->gt_dev.dv_xname, IRQ_COMM); 569 } 570 571 #ifdef GT_ECC 572 static char *gt_ecc_intr_str[4] = { 573 "(none)", 574 "single bit", 575 "double bit", 576 "(reserved)" 577 }; 578 579 static int 580 gt_ecc_intr(void *arg) 581 { 582 struct gt_softc *gt = (struct gt_softc *)arg; 583 u_int32_t addr; 584 u_int32_t dlo; 585 u_int32_t dhi; 586 u_int32_t rec; 587 u_int32_t calc; 588 u_int32_t count; 589 int err; 590 591 count = gt_read(gt, GT_ECC_Count); 592 dlo = gt_read(gt, GT_ECC_Data_Lo); 593 dhi = gt_read(gt, GT_ECC_Data_Hi); 594 rec = gt_read(gt, GT_ECC_Rec); 595 calc = gt_read(gt, GT_ECC_Calc); 596 addr = gt_read(gt, GT_ECC_Addr); /* read last! */ 597 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 598 599 err = addr & 0x3; 600 601 printf("%s: ECC error: %s: " 602 "addr %#x data %#x.%#x rec %#x calc %#x cnt %#x\n", 603 gt->gt_dev.dv_xname, gt_ecc_intr_str[err], 604 addr, dhi, dlo, rec, calc, count); 605 606 if (err == 2) 607 panic("ecc"); 608 609 return (err == 1); 610 } 611 612 /* 613 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts 614 */ 615 static void 616 gt_ecc_intr_enb(struct gt_softc *gt) 617 { 618 u_int32_t ctl; 619 620 ctl = gt_read(gt, GT_ECC_Ctl); 621 ctl |= 1 << 16; /* XXX 1-bit threshold == 1 */ 622 gt_write(gt, GT_ECC_Ctl, ctl); 623 (void)gt_read(gt, GT_ECC_Data_Lo); 624 (void)gt_read(gt, GT_ECC_Data_Hi); 625 (void)gt_read(gt, GT_ECC_Rec); 626 (void)gt_read(gt, GT_ECC_Calc); 627 (void)gt_read(gt, GT_ECC_Addr); /* read last! */ 628 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 629 630 intr_establish(IRQ_ECC, IST_LEVEL, IPL_GTERR, gt_ecc_intr, gt); 631 printf("%s: ECC irpt at %d\n", gt->gt_dev.dv_xname, IRQ_ECC); 632 } 633 #endif /* GT_ECC */ 634 635 636 #ifndef GT_MPP_WATCHDOG 637 void 638 gt_watchdog_init(struct gt_softc *gt) 639 { 640 u_int32_t r; 641 unsigned int omsr; 642 643 omsr = extintr_disable(); 644 645 printf("%s: watchdog", gt->gt_dev.dv_xname); 646 647 /* 648 * handle case where firmware started watchdog 649 */ 650 r = gt_read(gt, GT_WDOG_Config); 651 printf(" status %#x,%#x:", 652 r, gt_read(gt, GT_WDOG_Value)); 653 if ((r & 0x80000000) != 0) { 654 gt_watchdog_sc = gt; /* enabled */ 655 gt_watchdog_state = 1; 656 printf(" firmware-enabled\n"); 657 gt_watchdog_service(); 658 return; 659 } else { 660 printf(" firmware-disabled\n"); 661 } 662 663 extintr_restore(omsr); 664 } 665 666 #else /* GT_MPP_WATCHDOG */ 667 668 void 669 gt_watchdog_init(struct gt_softc *gt) 670 { 671 u_int32_t mpp_watchdog = GT_MPP_WATCHDOG; /* from config */ 672 u_int32_t r; 673 u_int32_t cfgbits; 674 u_int32_t mppbits; 675 u_int32_t mppmask=0; 676 u_int32_t regoff; 677 unsigned int omsr; 678 679 printf("%s: watchdog", gt->gt_dev.dv_xname); 680 681 if (mpp_watchdog == 0) { 682 printf(" not configured\n"); 683 return; 684 } 685 686 #if 0 687 if (afw_wdog_ctl == 1) { 688 printf(" admin disabled\n"); 689 return; 690 } 691 #endif 692 693 omsr = extintr_disable(); 694 695 /* 696 * if firmware started watchdog, we disable and start 697 * from scratch to get it in a known state. 698 * 699 * on GT-64260A we always see 0xffffffff 700 * in both the GT_WDOG_Config_Enb and GT_WDOG_Value regsiters. 701 * Use AFW-supplied flag to determine run state. 702 */ 703 r = gt_read(gt, GT_WDOG_Config); 704 if (r != ~0) { 705 if ((r & GT_WDOG_Config_Enb) != 0) { 706 gt_write(gt, GT_WDOG_Config, 707 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 708 gt_write(gt, GT_WDOG_Config, 709 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 710 } 711 } else { 712 #if 0 713 if (afw_wdog_state == 1) { 714 gt_write(gt, GT_WDOG_Config, 715 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 716 gt_write(gt, GT_WDOG_Config, 717 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 718 } 719 #endif 720 } 721 722 /* 723 * "the watchdog timer can be activated only after 724 * configuring two MPP pins to act as WDE and WDNMI" 725 */ 726 mppbits = 0; 727 cfgbits = 0x3; 728 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) { 729 if ((mpp_watchdog & cfgbits) == cfgbits) { 730 mppbits = 0x99; 731 mppmask = 0xff; 732 break; 733 } 734 cfgbits <<= 2; 735 if ((mpp_watchdog & cfgbits) == cfgbits) { 736 mppbits = 0x9900; 737 mppmask = 0xff00; 738 break; 739 } 740 cfgbits <<= 6; /* skip unqualified bits */ 741 } 742 if (mppbits == 0) { 743 printf(" config error\n"); 744 extintr_restore(omsr); 745 return; 746 } 747 748 r = gt_read(gt, regoff); 749 r &= ~mppmask; 750 r |= mppbits; 751 gt_write(gt, regoff, r); 752 printf(" mpp %#x %#x", regoff, mppbits); 753 754 gt_write(gt, GT_WDOG_Value, GT_WDOG_NMI_DFLT); 755 756 gt_write(gt, GT_WDOG_Config, 757 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 758 gt_write(gt, GT_WDOG_Config, 759 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 760 761 762 r = gt_read(gt, GT_WDOG_Config), 763 printf(" status %#x,%#x: %s", 764 r, gt_read(gt, GT_WDOG_Value), 765 ((r & GT_WDOG_Config_Enb) != 0) ? "enabled" : "botch"); 766 767 if ((r & GT_WDOG_Config_Enb) != 0) { 768 register_t hid0; 769 770 gt_watchdog_sc = gt; /* enabled */ 771 gt_watchdog_state = 1; 772 773 /* 774 * configure EMCP in HID0 in case it's not already set 775 */ 776 __asm volatile("sync"); 777 hid0 = mfspr(SPR_HID0); 778 if ((hid0 & HID0_EMCP) == 0) { 779 hid0 |= HID0_EMCP; 780 __asm volatile("sync"); mtspr(SPR_HID0, hid0); 781 __asm volatile("sync"); hid0 = mfspr(SPR_HID0); 782 printf(", EMCP set"); 783 } 784 } 785 printf("\n"); 786 787 extintr_restore(omsr); 788 } 789 #endif /* GT_MPP_WATCHDOG */ 790 791 #ifdef DEBUG 792 u_int32_t hid0_print(void); 793 u_int32_t 794 hid0_print() 795 { 796 u_int32_t hid0; 797 __asm volatile("sync; mfspr %0,1008;" : "=r"(hid0)); 798 printf("hid0: %#x\n", hid0); 799 return hid0; 800 } 801 #endif 802 803 void 804 gt_watchdog_enable(void) 805 { 806 struct gt_softc *gt; 807 unsigned int omsr; 808 809 omsr = extintr_disable(); 810 gt = gt_watchdog_sc; 811 if ((gt != NULL) && (gt_watchdog_state == 0)) { 812 gt_watchdog_state = 1; 813 814 gt_write(gt, GT_WDOG_Config, 815 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 816 gt_write(gt, GT_WDOG_Config, 817 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 818 } 819 extintr_restore(omsr); 820 } 821 822 void 823 gt_watchdog_disable(void) 824 { 825 struct gt_softc *gt; 826 unsigned int omsr; 827 828 omsr = extintr_disable(); 829 gt = gt_watchdog_sc; 830 if ((gt != NULL) && (gt_watchdog_state != 0)) { 831 gt_watchdog_state = 0; 832 833 gt_write(gt, GT_WDOG_Config, 834 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 835 gt_write(gt, GT_WDOG_Config, 836 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 837 } 838 extintr_restore(omsr); 839 } 840 841 #ifdef DEBUG 842 int inhibit_watchdog_service = 0; 843 #endif 844 void 845 gt_watchdog_service(void) 846 { 847 struct gt_softc *gt = gt_watchdog_sc; 848 849 if ((gt == NULL) || (gt_watchdog_state == 0)) 850 return; /* not enabled */ 851 #ifdef DEBUG 852 if (inhibit_watchdog_service) 853 return; 854 #endif 855 856 gt_write(gt, GT_WDOG_Config, 857 (GT_WDOG_Config_Ctl2a | GT_WDOG_Preset_DFLT)); 858 gt_write(gt, GT_WDOG_Config, 859 (GT_WDOG_Config_Ctl2b | GT_WDOG_Preset_DFLT)); 860 } 861 862 /* 863 * gt_watchdog_reset - force a watchdog reset using Preset_VAL=0 864 */ 865 void 866 gt_watchdog_reset() 867 { 868 struct gt_softc *gt = gt_watchdog_sc; 869 u_int32_t r; 870 871 (void)extintr_disable(); 872 r = gt_read(gt, GT_WDOG_Config); 873 gt_write(gt, GT_WDOG_Config, (GT_WDOG_Config_Ctl1a | 0)); 874 gt_write(gt, GT_WDOG_Config, (GT_WDOG_Config_Ctl1b | 0)); 875 if ((r & GT_WDOG_Config_Enb) != 0) { 876 /* 877 * was enabled, we just toggled it off, toggle on again 878 */ 879 gt_write(gt, GT_WDOG_Config, 880 (GT_WDOG_Config_Ctl1a | 0)); 881 gt_write(gt, GT_WDOG_Config, 882 (GT_WDOG_Config_Ctl1b | 0)); 883 } 884 for(;;); 885 } 886 887 static int 888 gt_devbus_intr(void *arg) 889 { 890 struct gt_softc *gt = (struct gt_softc *)arg; 891 u_int32_t cause; 892 u_int32_t addr; 893 894 cause = gt_read(gt, GT_DEVBUS_ICAUSE); 895 addr = gt_read(gt, GT_DEVBUS_ERR_ADDR); 896 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear irpt */ 897 898 if (cause & GT_DEVBUS_DBurstErr) { 899 printf("%s: Device Bus error: burst violation", 900 gt->gt_dev.dv_xname); 901 if ((cause & GT_DEVBUS_Sel) == 0) 902 printf(", addr %#x", addr); 903 printf("\n"); 904 } 905 if (cause & GT_DEVBUS_DRdyErr) { 906 printf("%s: Device Bus error: ready timer expired", 907 gt->gt_dev.dv_xname); 908 if ((cause & GT_DEVBUS_Sel) != 0) 909 printf(", addr %#x\n", addr); 910 printf("\n"); 911 } 912 913 return (cause != 0); 914 } 915 916 /* 917 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts 918 */ 919 static void 920 gt_devbus_intr_enb(struct gt_softc *gt) 921 { 922 gt_write(gt, GT_DEVBUS_IMASK, 923 GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr); 924 (void)gt_read(gt, GT_DEVBUS_ERR_ADDR); /* clear addr */ 925 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 926 927 intr_establish(IRQ_DEV, IST_LEVEL, IPL_GTERR, gt_devbus_intr, gt); 928 printf("%s: Device Bus Error irpt at %d\n", 929 gt->gt_dev.dv_xname, IRQ_DEV); 930 } 931 932 933 int 934 gt_mii_read( 935 struct device *child, 936 struct device *parent, 937 int phy, 938 int reg) 939 { 940 struct gt_softc * const gt = (struct gt_softc *) parent; 941 uint32_t data; 942 int count = 10000; 943 944 do { 945 DELAY(10); 946 data = gt_read(gt, ETH_ESMIR); 947 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 948 949 if (count == 0) { 950 printf("%s: mii read for phy %d reg %d busied out\n", 951 child->dv_xname, phy, reg); 952 return ETH_ESMIR_Value_GET(data); 953 } 954 955 gt_write(gt, ETH_ESMIR, ETH_ESMIR_READ(phy, reg)); 956 957 count = 10000; 958 do { 959 DELAY(10); 960 data = gt_read(gt, ETH_ESMIR); 961 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 962 963 if (count == 0) 964 printf("%s: mii read for phy %d reg %d timed out\n", 965 child->dv_xname, phy, reg); 966 #if defined(GTMIIDEBUG) 967 printf("%s: mii_read(%d, %d): %#x data %#x\n", 968 child->dv_xname, phy, reg, 969 data, ETH_ESMIR_Value_GET(data)); 970 #endif 971 return ETH_ESMIR_Value_GET(data); 972 } 973 974 void 975 gt_mii_write ( 976 struct device *child, 977 struct device *parent, 978 int phy, int reg, 979 int value) 980 { 981 struct gt_softc * const gt = (struct gt_softc *) parent; 982 uint32_t data; 983 int count = 10000; 984 985 do { 986 DELAY(10); 987 data = gt_read(gt, ETH_ESMIR); 988 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 989 990 if (count == 0) { 991 printf("%s: mii write for phy %d reg %d busied out (busy)\n", 992 child->dv_xname, phy, reg); 993 return; 994 } 995 996 gt_write(gt, ETH_ESMIR, 997 ETH_ESMIR_WRITE(phy, reg, value)); 998 999 count = 10000; 1000 do { 1001 DELAY(10); 1002 data = gt_read(gt, ETH_ESMIR); 1003 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 1004 1005 if (count == 0) 1006 printf("%s: mii write for phy %d reg %d timed out\n", 1007 child->dv_xname, phy, reg); 1008 #if defined(GTMIIDEBUG) 1009 printf("%s: mii_write(%d, %d, %#x)\n", 1010 child->dv_xname, phy, reg, value); 1011 #endif 1012 } 1013 1014 /* 1015 * Since the memory and pci spaces are mapped 1:1 we just need 1016 * to return unity here 1017 */ 1018 bus_addr_t 1019 gt_dma_phys_to_bus_mem(bus_dma_tag_t t, bus_addr_t a) 1020 { 1021 return a; 1022 } 1023 bus_addr_t 1024 gt_dma_bus_mem_to_phys(bus_dma_tag_t t, bus_addr_t a) 1025 { 1026 return a; 1027 } 1028