1 /* $NetBSD: sbreg.h,v 1.21 1997/05/23 21:20:18 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1991-1993 Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the Computer Systems 18 * Engineering Group at Lawrence Berkeley Laboratory. 19 * 4. Neither the name of the University nor of the Laboratory may be used 20 * to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: Header: sbreg.h,v 1.3 93/07/18 14:07:28 mccanne Exp (LBL) 36 */ 37 38 /* 39 * SoundBlaster register definitions. 40 * See "The Developer Kit for Sound Blaster Series, User's Guide" for more 41 * complete information (avialable from Creative Labs, Inc.). We refer 42 * to this documentation as "SBK". 43 * 44 * We handle two types of cards: the basic SB version 2.0+, and 45 * the SB PRO. There are several distinct pieces of the hardware: 46 * 47 * joystick port (independent of I/O base address) 48 * FM synth (stereo on PRO) 49 * mixer (PRO only) 50 * DSP (sic) 51 * CD-ROM (PRO only) 52 * 53 * The MIDI capabilities are handled by the DSP unit. 54 */ 55 56 /* 57 * Address map. The SoundBlaster can be configured (via jumpers) for 58 * either base I/O address 0x220 or 0x240. The encodings below give 59 * the offsets to specific SB ports. SBP stands for SB port offset. 60 */ 61 #define SBP_LFM_STATUS 0 /* R left FM status port */ 62 #define SBP_LFM_ADDR 0 /* W left FM address register */ 63 #define SBP_LFM_DATA 1 /* RW left FM data port */ 64 #define SBP_RFM_STATUS 2 /* R right FM status port */ 65 #define SBP_RFM_ADDR 2 /* W right FM address register */ 66 #define SBP_RFM_DATA 3 /* RW right FM data port */ 67 68 #define SBP_FM_STATUS 8 /* R FM status port */ 69 #define SBP_FM_ADDR 8 /* W FM address register */ 70 #define SBP_FM_DATA 9 /* RW FM data port */ 71 #define SBP_MIXER_ADDR 4 /* W mixer address register */ 72 #define SBP_MIXER_DATA 5 /* RW mixer data port */ 73 74 #define SBP_MIX_RESET 0x00 /* mixer reset port, value */ 75 #define SBP_1335_MASTER_VOL 0x02 76 #define SBP_1335_MIDI_VOL 0x06 77 #define SBP_1335_CD_VOL 0x08 78 #define SBP_1335_VOICE_VOL 0x0A 79 80 #define SBP_VOICE_VOL 0x04 81 #define SBP_MIC_VOL 0x0A /* warning: only one channel of volume... */ 82 #define SBP_MASTER_VOL 0x22 83 #define SBP_MIDI_VOL 0x26 84 #define SBP_CD_VOL 0x28 85 #define SBP_LINE_VOL 0x2E 86 87 #define SBP_RECORD_SOURCE 0x0C 88 #define SBP_STEREO 0x0E 89 #define SBP_PLAYMODE_STEREO 0x2 90 #define SBP_PLAYMODE_MONO 0x0 91 #define SBP_PLAYMODE_MASK 0x2 92 #define SBP_OUTFILTER 0x0E 93 #define SBP_INFILTER 0x0C 94 95 #define SBP_RECORD_FROM(src, filteron, high) ((src) | (filteron) | (high)) 96 #define SBP_FILTER_ON 0x0 97 #define SBP_FILTER_OFF 0x20 98 #define SBP_IFILTER_MASK 0x28 99 #define SBP_OFILTER_MASK 0x20 100 #define SBP_IFILTER_LOW 0 101 #define SBP_IFILTER_HIGH 0x08 102 #define SBP_FROM_MIC 0x00 103 #define SBP_FROM_CD 0x02 104 #define SBP_FROM_LINE 0x06 105 106 #define SBP_SET_IRQ 0x80 /* Soft-configured irq (SB16-) */ 107 #define SBP_SET_DRQ 0x81 /* Soft-configured drq (SB16-) */ 108 #define SBP_IRQ_STATUS 0x82 /* Pending IRQ status (SB16-) */ 109 #define SBP_IRQ_MPU401 0x04 110 #define SBP_IRQ_DMA16 0x02 111 #define SBP_IRQ_DMA8 0x01 112 113 #define SB16P_MASTER_L 0x30 114 #define SB16P_VOICE_L 0x32 115 #define SB16P_MIDI_L 0x34 116 #define SB16P_CD_L 0x36 117 #define SB16P_LINE_L 0x38 118 #define SB16P_MIC_L 0x3a 119 #define SB16P_PCSPEAKER 0x3b 120 #define SB16P_INPUT_GAIN_L 0x3f 121 #define SB16P_OUTPUT_GAIN_L 0x41 122 #define SB16P_TREBLE_L 0x44 123 #define SB16P_BASS_L 0x46 124 #define SB16P_L_TO_R(l) ((l)+1) 125 126 #define SB16P_AGC 0x43 127 128 #define SBP_RECORD_SOURCE_L 0x3d 129 #define SBP_RECORD_SOURCE_R 0x3e 130 #define SBP_MIDI_SRC_R 0x20 131 #define SBP_LINE_SRC_R 0x08 132 #define SBP_CD_SRC_R 0x02 133 #define SBP_MIC_SRC 0x01 134 #define SB_SRC_R_TO_L(x) ((x) << 1) 135 136 #define SB_STEREO_GAIN(left, right) ((left) | ((right) >> 4)) 137 #define SB_MIC_GAIN(v) ((v) >> 5) 138 #define SB_ADJUST_MIC_GAIN(sc, x) (ISSB16CLASS(sc) ? (x) & 0xf8 : (x) & 0xc0) 139 #define SB_ADJUST_GAIN(sc, x) (ISSB16CLASS(sc) ? (x) & 0xf8 : (x) & 0xe0) 140 #define SB_ADJUST_2_GAIN(sc, x) (x & 0xc0) 141 #define SB_1335_GAIN(x) ((x) >> 4) 142 #define SB_1335_MASTER_GAIN(x) ((x) >> 5) 143 144 #define SBP_DSP_RESET 6 /* W reset port */ 145 #define SB_MAGIC 0xaa /* card outputs on successful reset */ 146 #define SBP_DSP_READ 10 /* R read port */ 147 #define SBP_DSP_WRITE 12 /* W write port */ 148 #define SBP_DSP_WSTAT 12 /* R write status */ 149 #define SBP_DSP_RSTAT 14 /* R read status */ 150 #define SB_DSP_BUSY 0x80 151 #define SB_DSP_READY 0x80 152 #define SBP_DSP_IRQACK8 14 /* R acknowledge DSP IRQ, 8-bit */ 153 #define SBP_DSP_IRQACK16 15 /* R acknowledge DSP IRQ, 16-bit */ 154 #define SBP_CDROM_DATA 16 /* RW send cmds/recv data */ 155 #define SBP_CDROM_STATUS 17 /* R status port */ 156 #define SBP_CDROM_RESET 18 /* W reset register */ 157 #define SBP_CDROM_ENABLE 19 /* W enable register */ 158 159 #define SBP_NPORT 24 160 #define SB_NPORT 16 161 162 /* 163 * DSP commands. This unit handles MIDI and audio capabilities. 164 * The DSP can be reset, data/commands can be read or written to it, 165 * and it can generate interrupts. Interrupts are generated for MIDI 166 * input or DMA completion. They seem to have neglected the fact 167 * that it would be nice to have a MIDI transmission complete interrupt. 168 * Worse, the DMA engine is half-duplex. This means you need to do 169 * (timed) programmed I/O to be able to record and play simulataneously. 170 */ 171 #define SB_DSP_DACWRITE 0x10 /* programmed I/O write to DAC */ 172 #define SB_DSP_WDMA 0x14 /* begin 8-bit linear DMA output */ 173 #define SB_DSP_WDMA_2 0x16 /* begin 2-bit ADPCM DMA output */ 174 #define SB_DSP_WDMA_LOOP 0x1C /* begin 8-bit linear DMA output loop */ 175 #define SB_DSP_ADCREAD 0x20 /* programmed I/O read from ADC */ 176 #define SB_DSP_RDMA 0x24 /* begin 8-bit linear DMA input */ 177 #define SB_DSP_RDMA_LOOP 0x2C /* begin 8-bit linear DMA input loop */ 178 #define SB_MIDI_POLL 0x30 /* initiate a polling read for MIDI */ 179 #define SB_MIDI_READ 0x31 /* read a MIDI byte on recv intr */ 180 #define SB_MIDI_UART_POLL 0x34 /* enter UART mode w/ read polling */ 181 #define SB_MIDI_UART_INTR 0x35 /* enter UART mode w/ read intrs */ 182 #define SB_MIDI_WRITE 0x38 /* write a MIDI byte (non-UART mode) */ 183 #define SB_DSP_TIMECONST 0x40 /* set ADAC time constant */ 184 #define SB_DSP16_OUTPUTRATE 0x41 /* set ADAC output rate */ 185 #define SB_DSP16_INPUTRATE 0x42 /* set ADAC input rate */ 186 #define SB_DSP_BLOCKSIZE 0x48 /* set blk size for high speed xfer */ 187 #define SB_DSP_WDMA_4 0x74 /* begin 4-bit ADPCM DMA output */ 188 #define SB_DSP_WDMA_2_6 0x76 /* begin 2.6-bit ADPCM DMA output */ 189 #define SB_DSP_SILENCE 0x80 /* send a block of silence */ 190 #define SB_DSP_HS_OUTPUT 0x90 /* set high speed mode for wdma */ 191 #define SB_DSP_HS_INPUT 0x98 /* set high speed mode for rdma */ 192 #define SB_DSP_RECORD_MONO 0xA0 /* set mono recording */ 193 #define SB_DSP_RECORD_STEREO 0xA8 /* set stereo recording */ 194 #define SB_DSP16_WDMA_16 0xB6 /* begin 16-bit linear output */ 195 #define SB_DSP16_RDMA_16 0xBE /* begin 16-bit linear input */ 196 #define SB_DSP16_WDMA_8 0xC6 /* begin 8-bit linear output */ 197 #define SB_DSP16_RDMA_8 0xCE /* begin 8-bit linear input */ 198 #define SB_DSP_HALT 0xd0 /* temporarilty suspend DMA */ 199 #define SB_DSP_SPKR_ON 0xd1 /* turn speaker on */ 200 #define SB_DSP_SPKR_OFF 0xd3 /* turn speaker off */ 201 #define SB_DSP_CONT 0xd4 /* continue suspended DMA */ 202 #define SB_DSP_RD_SPKR 0xd8 /* get speaker status */ 203 #define SB_SPKR_OFF 0x00 204 #define SB_SPKR_ON 0xff 205 #define SB_DSP_VERSION 0xe1 /* get version number */ 206 207 /* Some of these come from linux driver (It serves as convenient unencumbered 208 documentation) */ 209 #define JAZZ16_READ_VER 0xFA /* 0x12 means ProSonic/Jazz16? */ 210 #define JAZZ16_VER_JAZZ 0x12 211 #define JAZZ16_SET_DMAINTR 0xFB 212 213 #define JAZZ16_CONFIG_PORT 0x201 214 #define JAZZ16_WAKEUP 0xAF 215 #define JAZZ16_SETBASE 0x50 216 217 #define JAZZ16_RECORD_STEREO 0xAC /* 16-bit record */ 218 #define JAZZ16_RECORD_MONO 0xA4 /* 16-bit record */ 219 220 /* 221 * These come from Jazz16 chipset documentation, which doesn't include 222 * full register details, alas. Their source code CD-ROM probably includes 223 * details, but it has an NDA attached. 224 */ 225 #define JAZZ16_DIR_PB 0x10 226 #define JAZZ16_SINGLE_PB 0x14 227 #define JAZZ16_SINGLE_ALAW_PB 0x17 228 #define JAZZ16_CONT_PB 0x1C 229 #define JAZZ16_CONT_ALAW_PB 0x1F 230 #define JAZZ16_DIR_PCM_REC 0x20 231 #define JAZZ16_SINGLE_REC 0x24 232 #define JAZZ16_SINGLE_ALAW_REC 0x27 233 #define JAZZ16_CONT_REC 0x2C 234 #define JAZZ16_CONT_ALAW_REC 0x2F 235 #define JAZZ16_SINGLE_ADPCM_PB 0x74 236 #define JAZZ16_SINGLE_MULAW_PB 0x77 237 #define JAZZ16_CONT_ADPCM_PB 0x7C 238 #define JAZZ16_SINGLE_ADPCM_REC 0x84 239 #define JAZZ16_SINGLE_MULAW_REC 0x87 240 #define JAZZ16_CONT_ADPCM_REC 0x8C 241 #define JAZZ16_CONT_MULAW_REC 0x8F 242 #define JAZZ16_CONT_PB_XX 0x90 243 #define JAZZ16_SINGLE_PB_XX 0x91 244 #define JAZZ16_SINGLE_REC_XX 0x98 245 #define JAZZ16_CONT_REC_XX 0x99 246 247 248 /* 249 * The ADPCM encodings are differential, meaning each sample represents 250 * a difference to add to a running sum. The inital value is called the 251 * reference, or reference byte. Any of the ADPCM DMA transfers can specify 252 * that the given transfer begins with a reference byte by or'ing 253 * in the bit below. 254 */ 255 #define SB_DSP_REFERENCE 1 256 257 /* 258 * Macros to detect valid hardware configuration data. 259 */ 260 #define SBP_IRQ_VALID(irq) ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10) 261 #define SB_IRQ_VALID(irq) ((irq) == 3 || (irq) == 5 || (irq) == 7 || (irq) == 9) 262 263 #define SB16_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3 || \ 264 (chan) == 5 || (chan) == 6 || (chan) == 7) 265 #define SBP_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3) 266 #define SB_DRQ_VALID(chan) ((chan) == 1) 267 268 #define SB_BASE_VALID(base) ((base) == 0x220 || (base) == 0x240) 269 270 #define SB_INPUT_RATE 0 271 #define SB_OUTPUT_RATE 1 272 273