1 /* $NetBSD: sbreg.h,v 1.8 1995/02/28 21:47:47 brezak Exp $ */ 2 3 /* 4 * Copyright (c) 1991-1993 Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the Computer Systems 18 * Engineering Group at Lawrence Berkeley Laboratory. 19 * 4. Neither the name of the University nor of the Laboratory may be used 20 * to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: Header: sbreg.h,v 1.3 93/07/18 14:07:28 mccanne Exp (LBL) 36 * $Id: sbreg.h,v 1.8 1995/02/28 21:47:47 brezak Exp $ 37 */ 38 39 /* 40 * SoundBlaster register definitions. 41 * See "The Developer Kit for Sound Blaster Series, User's Guide" for more 42 * complete information (avialable from Creative Labs, Inc.). We refer 43 * to this documentation as "SBK". 44 * 45 * We handle two types of cards: the basic SB version 2.0+, and 46 * the SB PRO. There are several distinct pieces of the hardware: 47 * 48 * joystick port (independent of I/O base address) 49 * FM synth (stereo on PRO) 50 * mixer (PRO only) 51 * DSP (sic) 52 * CD-ROM (PRO only) 53 * 54 * The MIDI capabilities are handled by the DSP unit. 55 */ 56 57 /* 58 * Address map. The SoundBlaster can be configured (via jumpers) for 59 * either base I/O address 0x220 or 0x240. The encodings below give 60 * the offsets to specific SB ports. SBP stands for SB port offset. 61 */ 62 #define SBP_LFM_STATUS 0 /* R left FM status port */ 63 #define SBP_LFM_ADDR 0 /* W left FM address register */ 64 #define SBP_LFM_DATA 1 /* RW left FM data port */ 65 #define SBP_RFM_STATUS 2 /* R right FM status port */ 66 #define SBP_RFM_ADDR 2 /* W right FM address register */ 67 #define SBP_RFM_DATA 3 /* RW right FM data port */ 68 69 #define SBP_FM_STATUS 8 /* R FM status port */ 70 #define SBP_FM_ADDR 8 /* W FM address register */ 71 #define SBP_FM_DATA 9 /* RW FM data port */ 72 #define SBP_MIXER_ADDR 4 /* W mixer address register */ 73 #define SBP_MIXER_DATA 5 /* RW mixer data port */ 74 #define SBP_MIX_RESET 0 /* mixer reset port, value */ 75 #define SBP_MASTER_VOL 0x22 76 #define SBP_FM_VOL 0x26 77 #define SBP_CD_VOL 0x28 78 #define SBP_LINE_VOL 0x2E 79 #define SBP_DAC_VOL 0x04 80 #define SBP_MIC_VOL 0x0A /* warning: only one channel of 81 volume... */ 82 #define SBP_SPEAKER_VOL 0x42 83 #define SBP_TREBLE_EQ 0x44 84 #define SBP_BASS_EQ 0x46 85 86 #define SBP_RECORD_SOURCE 0x0C 87 #define SBP_STEREO 0x0E 88 #define SBP_PLAYMODE_STEREO 0x2 89 #define SBP_PLAYMODE_MONO 0x0 90 #define SBP_PLAYMODE_MASK 0x2 91 #define SBP_OUTFILTER 0x0E 92 #define SBP_INFILTER 0x0C 93 94 #define SBP_RECORD_FROM(src, filteron, high) ((src) | (filteron) | (high)) 95 #define SBP_FILTER_ON 0x0 96 #define SBP_FILTER_OFF 0x20 97 #define SBP_FILTER_MASK 0x20 98 #define SBP_FILTER_LOW 0 99 #define SBP_FILTER_HIGH 0x08 100 #define SBP_FROM_MIC 0x00 101 #define SBP_FROM_CD 0x02 102 #define SBP_FROM_LINE 0x06 103 #define sbdsp_stereo_vol(left, right) (((left) << 4) | (right)) 104 #define SBP_MAXVOL 0xf /* per channel */ 105 #define SBP_MINVOL 0x0 /* per channel */ 106 #define SBP_AGAIN_TO_SBGAIN(again) ((again) >> 4) /* per channel */ 107 #define SBP_AGAIN_TO_MICGAIN(again) ((again) >> 5) /* mic has only 3 bits, 108 sorry! */ 109 #define SBP_LEFTGAIN(sbgain) (sbgain & 0xf0) /* left channel */ 110 #define SBP_RIGHTGAIN(sbgain) ((sbgain & 0xf) << 4) /* right channel */ 111 #define SBP_SBGAIN_TO_AGAIN(sbgain) SBP_LEFTGAIN(sbgain) 112 #define SBP_MICGAIN_TO_AGAIN(micgain) (micgain << 5) 113 #define SBP_DSP_RESET 6 /* W reset port */ 114 #define SB_MAGIC 0xaa /* card outputs on successful reset */ 115 #define SBP_DSP_READ 10 /* R read port */ 116 #define SBP_DSP_WRITE 12 /* W write port */ 117 #define SBP_DSP_WSTAT 12 /* R write status */ 118 #define SBP_DSP_RSTAT 14 /* R read status */ 119 #define SB_DSP_BUSY 0x80 120 #define SB_DSP_READY 0x80 121 #define SBP_CDROM_DATA 16 /* RW send cmds/recv data */ 122 #define SBP_CDROM_STATUS 17 /* R status port */ 123 #define SBP_CDROM_RESET 18 /* W reset register */ 124 #define SBP_CDROM_ENABLE 19 /* W enable register */ 125 126 #define SBP_NPORT 24 127 #define SB_NPORT 16 128 129 /* 130 * DSP commands. This unit handles MIDI and audio capabilities. 131 * The DSP can be reset, data/commands can be read or written to it, 132 * and it can generate interrupts. Interrupts are generated for MIDI 133 * input or DMA completion. They seem to have neglected the fact 134 * that it would be nice to have a MIDI transmission complete interrupt. 135 * Worse, the DMA engine is half-duplex. This means you need to do 136 * (timed) programmed I/O to be able to record and play simulataneously. 137 */ 138 #define SB_DSP_DACWRITE 0x10 /* programmed I/O write to DAC */ 139 #define SB_DSP_WDMA 0x14 /* begin 8-bit linear DMA output */ 140 #define SB_DSP_WDMA_2 0x16 /* begin 2-bit ADPCM DMA output */ 141 #define SB_DSP_ADCREAD 0x20 /* programmed I/O read from ADC */ 142 #define SB_DSP_RDMA 0x24 /* begin 8-bit linear DMA input */ 143 #define SB_MIDI_POLL 0x30 /* initiate a polling read for MIDI */ 144 #define SB_MIDI_READ 0x31 /* read a MIDI byte on recv intr */ 145 #define SB_MIDI_UART_POLL 0x34 /* enter UART mode w/ read polling */ 146 #define SB_MIDI_UART_INTR 0x35 /* enter UART mode w/ read intrs */ 147 #define SB_MIDI_WRITE 0x38 /* write a MIDI byte (non-UART mode) */ 148 #define SB_DSP_TIMECONST 0x40 /* set ADAC time constant */ 149 #define SB_DSP_BLOCKSIZE 0x48 /* set blk size for high speed xfer */ 150 #define SB_DSP_WDMA_4 0x74 /* begin 4-bit ADPCM DMA output */ 151 #define SB_DSP_WDMA_2_6 0x76 /* begin 2.6-bit ADPCM DMA output */ 152 #define SB_DSP_SILENCE 0x80 /* send a block of silence */ 153 #define SB_DSP_HS_OUTPUT 0x91 /* set high speed mode for wdma */ 154 #define SB_DSP_HS_INPUT 0x99 /* set high speed mode for rdma */ 155 #define SB_DSP_RECORD_MONO 0xA0 /* set mono recording */ 156 #define SB_DSP_RECORD_STEREO 0xA8 /* set stereo recording */ 157 #define SB_DSP_HALT 0xd0 /* temporarilty suspend DMA */ 158 #define SB_DSP_SPKR_ON 0xd1 /* turn speaker on */ 159 #define SB_DSP_SPKR_OFF 0xd3 /* turn speaker off */ 160 #define SB_DSP_CONT 0xd4 /* continue suspended DMA */ 161 #define SB_DSP_RD_SPKR 0xd8 /* get speaker status */ 162 #define SB_SPKR_OFF 0x00 163 #define SB_SPKR_ON 0xff 164 #define SB_DSP_VERSION 0xe1 /* get version number */ 165 166 /* 167 * The ADPCM encodings are differential, meaning each sample represents 168 * a difference to add to a running sum. The inital value is called the 169 * reference, or reference byte. Any of the ADPCM DMA transfers can specify 170 * that the given transfer begins with a reference byte by or'ing 171 * in the bit below. 172 */ 173 #define SB_DSP_REFERENCE 1 174 175 /* 176 * Macros to detect valid hardware configuration data. 177 */ 178 #define SBP_IRQ_VALID(irq) ((irq) == 2 || (irq) == 5 || (irq) == 7 || (irq) == 10) 179 #define SB_IRQ_VALID(irq) ((irq) == 2 || (irq) == 3 || (irq) == 5 || (irq) == 7) 180 181 #define SBP_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3) 182 #define SB_DRQ_VALID(chan) ((chan) == 1) 183 184 #define SB_BASE_VALID(base) ((base) == 0x220 || (base) == 0x240) 185 186 #define SB_INPUT_RATE 0 187 #define SB_OUTPUT_RATE 1 188 189