1 /* $NetBSD: isadma.c,v 1.58 2008/04/28 20:23:52 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the ISA on-board DMA controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: isadma.c,v 1.58 2008/04/28 20:23:52 martin Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/proc.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 46 #include <sys/bus.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <dev/isa/isareg.h> 51 #include <dev/isa/isavar.h> 52 #include <dev/isa/isadmavar.h> 53 #include <dev/isa/isadmareg.h> 54 55 struct isa_mem *isa_mem_head; 56 57 /* 58 * High byte of DMA address is stored in this DMAPG register for 59 * the Nth DMA channel. 60 */ 61 static int dmapageport[2][4] = { 62 {0x7, 0x3, 0x1, 0x2}, 63 {0xf, 0xb, 0x9, 0xa} 64 }; 65 66 static u_int8_t dmamode[] = { 67 /* write to device/read from device */ 68 DMA37MD_READ | DMA37MD_SINGLE, 69 DMA37MD_WRITE | DMA37MD_SINGLE, 70 71 /* write to device/read from device */ 72 DMA37MD_READ | DMA37MD_DEMAND, 73 DMA37MD_WRITE | DMA37MD_DEMAND, 74 75 /* write to device/read from device - DMAMODE_LOOP */ 76 DMA37MD_READ | DMA37MD_SINGLE | DMA37MD_LOOP, 77 DMA37MD_WRITE | DMA37MD_SINGLE | DMA37MD_LOOP, 78 79 /* write to device/read from device - DMAMODE_LOOPDEMAND */ 80 DMA37MD_READ | DMA37MD_DEMAND | DMA37MD_LOOP, 81 DMA37MD_WRITE | DMA37MD_DEMAND | DMA37MD_LOOP, 82 }; 83 84 static inline void _isa_dmaunmask(struct isa_dma_state *, int); 85 static inline void _isa_dmamask(struct isa_dma_state *, int); 86 87 static inline void 88 _isa_dmaunmask(ids, chan) 89 struct isa_dma_state *ids; 90 int chan; 91 { 92 int ochan = chan & 3; 93 94 ISA_DMA_MASK_CLR(ids, chan); 95 96 /* 97 * If DMA is frozen, don't unmask it now. It will be 98 * unmasked when DMA is thawed again. 99 */ 100 if (ids->ids_frozen) 101 return; 102 103 /* set dma channel mode, and set dma channel mode */ 104 if ((chan & 4) == 0) 105 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 106 DMA1_SMSK, ochan | DMA37SM_CLEAR); 107 else 108 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 109 DMA2_SMSK, ochan | DMA37SM_CLEAR); 110 } 111 112 static inline void 113 _isa_dmamask(ids, chan) 114 struct isa_dma_state *ids; 115 int chan; 116 { 117 int ochan = chan & 3; 118 119 ISA_DMA_MASK_SET(ids, chan); 120 121 /* 122 * XXX Should we avoid masking the channel if DMA is 123 * XXX frozen? It seems like what we're doing should 124 * XXX be safe, and we do need to reset FFC... 125 */ 126 127 /* set dma channel mode, and set dma channel mode */ 128 if ((chan & 4) == 0) { 129 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 130 DMA1_SMSK, ochan | DMA37SM_SET); 131 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 132 DMA1_FFC, 0); 133 } else { 134 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 135 DMA2_SMSK, ochan | DMA37SM_SET); 136 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 137 DMA2_FFC, 0); 138 } 139 } 140 141 /* 142 * _isa_dmainit(): Initialize the isa_dma_state for this chipset. 143 */ 144 void 145 _isa_dmainit(ids, bst, dmat, dev) 146 struct isa_dma_state *ids; 147 bus_space_tag_t bst; 148 bus_dma_tag_t dmat; 149 struct device *dev; 150 { 151 int chan; 152 153 ids->ids_dev = dev; 154 155 if (ids->ids_initialized) { 156 /* 157 * Some systems may have e.g. `ofisa' (OpenFirmware 158 * configuration of ISA bus) and a regular `isa'. 159 * We allow both to call the initialization function, 160 * and take the device name from the last caller 161 * (assuming it will be the indirect ISA bus). Since 162 * `ofisa' and `isa' are the same bus with different 163 * configuration mechanisms, the space and dma tags 164 * must be the same! 165 */ 166 if (ids->ids_bst != bst || ids->ids_dmat != dmat) 167 panic("_isa_dmainit: inconsistent ISA tags"); 168 } else { 169 ids->ids_bst = bst; 170 ids->ids_dmat = dmat; 171 172 /* 173 * Map the registers used by the ISA DMA controller. 174 */ 175 if (bus_space_map(ids->ids_bst, IO_DMA1, DMA1_IOSIZE, 0, 176 &ids->ids_dma1h)) 177 panic("_isa_dmainit: unable to map DMA controller #1"); 178 if (bus_space_map(ids->ids_bst, IO_DMA2, DMA2_IOSIZE, 0, 179 &ids->ids_dma2h)) 180 panic("_isa_dmainit: unable to map DMA controller #2"); 181 if (bus_space_map(ids->ids_bst, IO_DMAPG, 0xf, 0, 182 &ids->ids_dmapgh)) 183 panic("_isa_dmainit: unable to map DMA page registers"); 184 185 /* 186 * All 8 DMA channels start out "masked". 187 */ 188 ids->ids_masked = 0xff; 189 190 /* 191 * Initialize the max transfer size for each channel, if 192 * it is not initialized already (i.e. by a bus-dependent 193 * front-end). 194 */ 195 for (chan = 0; chan < 8; chan++) { 196 if (ids->ids_maxsize[chan] == 0) 197 ids->ids_maxsize[chan] = 198 ISA_DMA_MAXSIZE_DEFAULT(chan); 199 } 200 201 ids->ids_initialized = 1; 202 203 /* 204 * DRQ 4 is used to chain the two 8237s together; make 205 * sure it's always cascaded, and that it will be unmasked 206 * when DMA is thawed. 207 */ 208 _isa_dmacascade(ids, 4); 209 } 210 } 211 212 /* 213 * _isa_dmacascade(): program 8237 DMA controller channel to accept 214 * external dma control by a board. 215 */ 216 int 217 _isa_dmacascade(ids, chan) 218 struct isa_dma_state *ids; 219 int chan; 220 { 221 int ochan = chan & 3; 222 223 if (chan < 0 || chan > 7) { 224 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 225 return (EINVAL); 226 } 227 228 if (ISA_DMA_DRQ_ISFREE(ids, chan) == 0) { 229 printf("%s: DRQ %d is not free\n", device_xname(ids->ids_dev), 230 chan); 231 return (EAGAIN); 232 } 233 234 ISA_DMA_DRQ_ALLOC(ids, chan); 235 236 /* set dma channel mode, and set dma channel mode */ 237 if ((chan & 4) == 0) 238 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 239 DMA1_MODE, ochan | DMA37MD_CASCADE); 240 else 241 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 242 DMA2_MODE, ochan | DMA37MD_CASCADE); 243 244 _isa_dmaunmask(ids, chan); 245 return (0); 246 } 247 248 int 249 _isa_drq_alloc(ids, chan) 250 struct isa_dma_state *ids; 251 int chan; 252 { 253 if (ISA_DMA_DRQ_ISFREE(ids, chan) == 0) 254 return EBUSY; 255 ISA_DMA_DRQ_ALLOC(ids, chan); 256 return 0; 257 } 258 259 int 260 _isa_drq_free(ids, chan) 261 struct isa_dma_state *ids; 262 int chan; 263 { 264 if (ISA_DMA_DRQ_ISFREE(ids, chan)) 265 return EINVAL; 266 ISA_DMA_DRQ_FREE(ids, chan); 267 return 0; 268 } 269 270 bus_size_t 271 _isa_dmamaxsize(ids, chan) 272 struct isa_dma_state *ids; 273 int chan; 274 { 275 276 if (chan < 0 || chan > 7) { 277 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 278 return (0); 279 } 280 281 return (ids->ids_maxsize[chan]); 282 } 283 284 int 285 _isa_dmamap_create(ids, chan, size, flags) 286 struct isa_dma_state *ids; 287 int chan; 288 bus_size_t size; 289 int flags; 290 { 291 int error; 292 293 if (chan < 0 || chan > 7) { 294 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 295 return (EINVAL); 296 } 297 298 if (size > ids->ids_maxsize[chan]) 299 return (EINVAL); 300 301 error = bus_dmamap_create(ids->ids_dmat, size, 1, size, 302 ids->ids_maxsize[chan], flags, &ids->ids_dmamaps[chan]); 303 304 return (error); 305 } 306 307 void 308 _isa_dmamap_destroy(ids, chan) 309 struct isa_dma_state *ids; 310 int chan; 311 { 312 313 if (chan < 0 || chan > 7) { 314 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 315 goto lose; 316 } 317 318 bus_dmamap_destroy(ids->ids_dmat, ids->ids_dmamaps[chan]); 319 return; 320 321 lose: 322 panic("_isa_dmamap_destroy"); 323 } 324 325 /* 326 * _isa_dmastart(): program 8237 DMA controller channel and set it 327 * in motion. 328 */ 329 int 330 _isa_dmastart(ids, chan, addr, nbytes, p, flags, busdmaflags) 331 struct isa_dma_state *ids; 332 int chan; 333 void *addr; 334 bus_size_t nbytes; 335 struct proc *p; 336 int flags; 337 int busdmaflags; 338 { 339 bus_dmamap_t dmam; 340 bus_addr_t dmaaddr; 341 int waport; 342 int ochan = chan & 3; 343 int error; 344 345 if (chan < 0 || chan > 7) { 346 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 347 goto lose; 348 } 349 350 #ifdef ISADMA_DEBUG 351 printf("_isa_dmastart: drq %d, addr %p, nbytes 0x%lx, p %p, " 352 "flags 0x%x, dmaflags 0x%x\n", 353 chan, addr, nbytes, p, flags, busdmaflags); 354 #endif 355 356 if (ISA_DMA_DRQ_ISFREE(ids, chan)) { 357 printf("%s: dma start on free channel %d\n", 358 device_xname(ids->ids_dev), chan); 359 goto lose; 360 } 361 362 if (chan & 4) { 363 if (nbytes > (1 << 17) || nbytes & 1 || (u_long)addr & 1) { 364 printf("%s: drq %d, nbytes 0x%lx, addr %p\n", 365 device_xname(ids->ids_dev), chan, 366 (unsigned long) nbytes, addr); 367 goto lose; 368 } 369 } else { 370 if (nbytes > (1 << 16)) { 371 printf("%s: drq %d, nbytes 0x%lx\n", 372 device_xname(ids->ids_dev), chan, 373 (unsigned long) nbytes); 374 goto lose; 375 } 376 } 377 378 dmam = ids->ids_dmamaps[chan]; 379 if (dmam == NULL) 380 panic("_isa_dmastart: no DMA map for chan %d", chan); 381 382 error = bus_dmamap_load(ids->ids_dmat, dmam, addr, nbytes, 383 p, busdmaflags | 384 ((flags & DMAMODE_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 385 if (error) 386 return (error); 387 388 #ifdef ISADMA_DEBUG 389 __asm(".globl isa_dmastart_afterload ; isa_dmastart_afterload:"); 390 #endif 391 392 if (flags & DMAMODE_READ) { 393 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 394 BUS_DMASYNC_PREREAD); 395 ids->ids_dmareads |= (1 << chan); 396 } else { 397 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 398 BUS_DMASYNC_PREWRITE); 399 ids->ids_dmareads &= ~(1 << chan); 400 } 401 402 dmaaddr = dmam->dm_segs[0].ds_addr; 403 404 #ifdef ISADMA_DEBUG 405 printf(" dmaaddr 0x%lx\n", dmaaddr); 406 407 __asm(".globl isa_dmastart_aftersync ; isa_dmastart_aftersync:"); 408 #endif 409 410 ids->ids_dmalength[chan] = nbytes; 411 412 _isa_dmamask(ids, chan); 413 ids->ids_dmafinished &= ~(1 << chan); 414 415 if ((chan & 4) == 0) { 416 /* set dma channel mode */ 417 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, DMA1_MODE, 418 ochan | dmamode[flags]); 419 420 /* send start address */ 421 waport = DMA1_CHN(ochan); 422 bus_space_write_1(ids->ids_bst, ids->ids_dmapgh, 423 dmapageport[0][ochan], (dmaaddr >> 16) & 0xff); 424 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport, 425 dmaaddr & 0xff); 426 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport, 427 (dmaaddr >> 8) & 0xff); 428 429 /* send count */ 430 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1, 431 (--nbytes) & 0xff); 432 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1, 433 (nbytes >> 8) & 0xff); 434 } else { 435 /* set dma channel mode */ 436 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, DMA2_MODE, 437 ochan | dmamode[flags]); 438 439 /* send start address */ 440 waport = DMA2_CHN(ochan); 441 bus_space_write_1(ids->ids_bst, ids->ids_dmapgh, 442 dmapageport[1][ochan], (dmaaddr >> 16) & 0xff); 443 dmaaddr >>= 1; 444 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport, 445 dmaaddr & 0xff); 446 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport, 447 (dmaaddr >> 8) & 0xff); 448 449 /* send count */ 450 nbytes >>= 1; 451 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2, 452 (--nbytes) & 0xff); 453 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2, 454 (nbytes >> 8) & 0xff); 455 } 456 457 _isa_dmaunmask(ids, chan); 458 return (0); 459 460 lose: 461 panic("_isa_dmastart"); 462 } 463 464 void 465 _isa_dmaabort(ids, chan) 466 struct isa_dma_state *ids; 467 int chan; 468 { 469 470 if (chan < 0 || chan > 7) { 471 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 472 panic("_isa_dmaabort"); 473 } 474 475 _isa_dmamask(ids, chan); 476 bus_dmamap_unload(ids->ids_dmat, ids->ids_dmamaps[chan]); 477 ids->ids_dmareads &= ~(1 << chan); 478 } 479 480 bus_size_t 481 _isa_dmacount(ids, chan) 482 struct isa_dma_state *ids; 483 int chan; 484 { 485 int waport; 486 bus_size_t nbytes; 487 int ochan = chan & 3; 488 489 if (chan < 0 || chan > 7) { 490 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 491 panic("isa_dmacount"); 492 } 493 494 _isa_dmamask(ids, chan); 495 496 /* 497 * We have to shift the byte count by 1. If we're in auto-initialize 498 * mode, the count may have wrapped around to the initial value. We 499 * can't use the TC bit to check for this case, so instead we compare 500 * against the original byte count. 501 * If we're not in auto-initialize mode, then the count will wrap to 502 * -1, so we also handle that case. 503 */ 504 if ((chan & 4) == 0) { 505 waport = DMA1_CHN(ochan); 506 nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma1h, 507 waport + 1) + 1; 508 nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma1h, 509 waport + 1) << 8; 510 nbytes &= 0xffff; 511 } else { 512 waport = DMA2_CHN(ochan); 513 nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma2h, 514 waport + 2) + 1; 515 nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma2h, 516 waport + 2) << 8; 517 nbytes <<= 1; 518 nbytes &= 0x1ffff; 519 } 520 521 if (nbytes == ids->ids_dmalength[chan]) 522 nbytes = 0; 523 524 _isa_dmaunmask(ids, chan); 525 return (nbytes); 526 } 527 528 int 529 _isa_dmafinished(ids, chan) 530 struct isa_dma_state *ids; 531 int chan; 532 { 533 534 if (chan < 0 || chan > 7) { 535 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 536 panic("_isa_dmafinished"); 537 } 538 539 /* check that the terminal count was reached */ 540 if ((chan & 4) == 0) 541 ids->ids_dmafinished |= bus_space_read_1(ids->ids_bst, 542 ids->ids_dma1h, DMA1_SR) & 0x0f; 543 else 544 ids->ids_dmafinished |= (bus_space_read_1(ids->ids_bst, 545 ids->ids_dma2h, DMA2_SR) & 0x0f) << 4; 546 547 return ((ids->ids_dmafinished & (1 << chan)) != 0); 548 } 549 550 void 551 _isa_dmadone(ids, chan) 552 struct isa_dma_state *ids; 553 int chan; 554 { 555 bus_dmamap_t dmam; 556 557 if (chan < 0 || chan > 7) { 558 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 559 panic("_isa_dmadone"); 560 } 561 562 dmam = ids->ids_dmamaps[chan]; 563 564 _isa_dmamask(ids, chan); 565 566 if (_isa_dmafinished(ids, chan) == 0) 567 printf("%s: _isa_dmadone: channel %d not finished\n", 568 device_xname(ids->ids_dev), chan); 569 570 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 571 (ids->ids_dmareads & (1 << chan)) ? BUS_DMASYNC_POSTREAD : 572 BUS_DMASYNC_POSTWRITE); 573 574 bus_dmamap_unload(ids->ids_dmat, dmam); 575 ids->ids_dmareads &= ~(1 << chan); 576 } 577 578 void 579 _isa_dmafreeze(ids) 580 struct isa_dma_state *ids; 581 { 582 int s; 583 584 s = splhigh(); 585 586 if (ids->ids_frozen == 0) { 587 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 588 DMA1_MASK, 0x0f); 589 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 590 DMA2_MASK, 0x0f); 591 } 592 593 ids->ids_frozen++; 594 if (ids->ids_frozen < 1) 595 panic("_isa_dmafreeze: overflow"); 596 597 splx(s); 598 } 599 600 void 601 _isa_dmathaw(ids) 602 struct isa_dma_state *ids; 603 { 604 int s; 605 606 s = splhigh(); 607 608 ids->ids_frozen--; 609 if (ids->ids_frozen < 0) 610 panic("_isa_dmathaw: underflow"); 611 612 if (ids->ids_frozen == 0) { 613 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 614 DMA1_MASK, ids->ids_masked & 0x0f); 615 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 616 DMA2_MASK, (ids->ids_masked >> 4) & 0x0f); 617 } 618 619 splx(s); 620 } 621 622 int 623 _isa_dmamem_alloc(ids, chan, size, addrp, flags) 624 struct isa_dma_state *ids; 625 int chan; 626 bus_size_t size; 627 bus_addr_t *addrp; 628 int flags; 629 { 630 bus_dma_segment_t seg; 631 int error, boundary, rsegs; 632 633 if (chan < 0 || chan > 7) { 634 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 635 panic("_isa_dmamem_alloc"); 636 } 637 638 boundary = (chan & 4) ? (1 << 17) : (1 << 16); 639 640 size = round_page(size); 641 642 error = bus_dmamem_alloc(ids->ids_dmat, size, PAGE_SIZE, boundary, 643 &seg, 1, &rsegs, flags); 644 if (error) 645 return (error); 646 647 *addrp = seg.ds_addr; 648 return (0); 649 } 650 651 void 652 _isa_dmamem_free(ids, chan, addr, size) 653 struct isa_dma_state *ids; 654 int chan; 655 bus_addr_t addr; 656 bus_size_t size; 657 { 658 bus_dma_segment_t seg; 659 660 if (chan < 0 || chan > 7) { 661 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 662 panic("_isa_dmamem_free"); 663 } 664 665 seg.ds_addr = addr; 666 seg.ds_len = size; 667 668 bus_dmamem_free(ids->ids_dmat, &seg, 1); 669 } 670 671 int 672 _isa_dmamem_map(ids, chan, addr, size, kvap, flags) 673 struct isa_dma_state *ids; 674 int chan; 675 bus_addr_t addr; 676 bus_size_t size; 677 void **kvap; 678 int flags; 679 { 680 bus_dma_segment_t seg; 681 682 if (chan < 0 || chan > 7) { 683 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 684 panic("_isa_dmamem_map"); 685 } 686 687 seg.ds_addr = addr; 688 seg.ds_len = size; 689 690 return (bus_dmamem_map(ids->ids_dmat, &seg, 1, size, kvap, flags)); 691 } 692 693 void 694 _isa_dmamem_unmap(ids, chan, kva, size) 695 struct isa_dma_state *ids; 696 int chan; 697 void *kva; 698 size_t size; 699 { 700 701 if (chan < 0 || chan > 7) { 702 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 703 panic("_isa_dmamem_unmap"); 704 } 705 706 bus_dmamem_unmap(ids->ids_dmat, kva, size); 707 } 708 709 paddr_t 710 _isa_dmamem_mmap(ids, chan, addr, size, off, prot, flags) 711 struct isa_dma_state *ids; 712 int chan; 713 bus_addr_t addr; 714 bus_size_t size; 715 off_t off; 716 int prot, flags; 717 { 718 bus_dma_segment_t seg; 719 720 if (chan < 0 || chan > 7) { 721 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 722 panic("_isa_dmamem_mmap"); 723 } 724 725 if (off < 0) 726 return (-1); 727 728 seg.ds_addr = addr; 729 seg.ds_len = size; 730 731 return (bus_dmamem_mmap(ids->ids_dmat, &seg, 1, off, prot, flags)); 732 } 733 734 int 735 _isa_drq_isfree(ids, chan) 736 struct isa_dma_state *ids; 737 int chan; 738 { 739 740 if (chan < 0 || chan > 7) { 741 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 742 panic("_isa_drq_isfree"); 743 } 744 745 return ISA_DMA_DRQ_ISFREE(ids, chan); 746 } 747 748 void * 749 _isa_malloc(ids, chan, size, pool, flags) 750 struct isa_dma_state *ids; 751 int chan; 752 size_t size; 753 struct malloc_type *pool; 754 int flags; 755 { 756 bus_addr_t addr; 757 void *kva; 758 int bflags; 759 struct isa_mem *m; 760 761 bflags = flags & M_WAITOK ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT; 762 763 if (_isa_dmamem_alloc(ids, chan, size, &addr, bflags)) 764 return 0; 765 if (_isa_dmamem_map(ids, chan, addr, size, &kva, bflags)) { 766 _isa_dmamem_free(ids, chan, addr, size); 767 return 0; 768 } 769 m = malloc(sizeof(*m), pool, flags); 770 if (m == 0) { 771 _isa_dmamem_unmap(ids, chan, kva, size); 772 _isa_dmamem_free(ids, chan, addr, size); 773 return 0; 774 } 775 m->ids = ids; 776 m->chan = chan; 777 m->size = size; 778 m->addr = addr; 779 m->kva = kva; 780 m->next = isa_mem_head; 781 isa_mem_head = m; 782 return (void *)kva; 783 } 784 785 void 786 _isa_free(addr, pool) 787 void *addr; 788 struct malloc_type *pool; 789 { 790 struct isa_mem **mp, *m; 791 void *kva = (void *)addr; 792 793 for(mp = &isa_mem_head; *mp && (*mp)->kva != kva; 794 mp = &(*mp)->next) 795 ; 796 m = *mp; 797 if (!m) { 798 printf("_isa_free: freeing unallocted memory\n"); 799 return; 800 } 801 *mp = m->next; 802 _isa_dmamem_unmap(m->ids, m->chan, kva, m->size); 803 _isa_dmamem_free(m->ids, m->chan, m->addr, m->size); 804 free(m, pool); 805 } 806 807 paddr_t 808 _isa_mappage(mem, off, prot) 809 void *mem; 810 off_t off; 811 int prot; 812 { 813 struct isa_mem *m; 814 815 for(m = isa_mem_head; m && m->kva != (void *)mem; m = m->next) 816 ; 817 if (!m) { 818 printf("_isa_mappage: mapping unallocted memory\n"); 819 return -1; 820 } 821 return _isa_dmamem_mmap(m->ids, m->chan, m->addr, 822 m->size, off, prot, BUS_DMA_WAITOK); 823 } 824