xref: /netbsd-src/sys/dev/isa/isa.c (revision 38023541164cff097d5fadec63134189b1453b8c)
1 /*-
2  * Copyright (c) 1991 The Regents of the University of California.
3  * All rights reserved.
4  *
5  * This code is derived from software contributed to Berkeley by
6  * William Jolitz.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by the University of
19  *	California, Berkeley and its contributors.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  *	from: @(#)isa.c	7.2 (Berkeley) 5/13/91
37  *	$Id: isa.c,v 1.29 1993/11/05 23:18:04 cgd Exp $
38  */
39 
40 /*
41  * code to manage AT bus
42  *
43  * 92/08/18  Frank P. MacLachlan (fpm@crash.cts.com):
44  * Fixed uninitialized variable problem and added code to deal
45  * with DMA page boundaries in isa_dmarangecheck().  Fixed word
46  * mode DMA count compution and reorganized DMA setup code in
47  * isa_dmastart()
48  */
49 
50 #include "param.h"
51 #include "systm.h"
52 #include "conf.h"
53 #include "file.h"
54 #include "buf.h"
55 #include "uio.h"
56 #include "syslog.h"
57 #include "malloc.h"
58 #include "machine/segments.h"
59 #include "machine/cpufunc.h"
60 #include "vm/vm.h"
61 #include "i386/isa/isa_device.h"
62 #include "i386/isa/isa.h"
63 #include "i386/isa/icu.h"
64 #include "i386/isa/ic/i8237.h"
65 #include "i386/isa/ic/i8042.h"
66 #include "i386/isa/timerreg.h"
67 #include "i386/isa/spkr_reg.h"
68 
69 /* sorry, has to be here, no place else really suitable */
70 #include "machine/pc/display.h"
71 u_short *Crtat = (u_short *)MONO_BUF;
72 
73 /*
74 **  Register definitions for DMA controller 1 (channels 0..3):
75 */
76 #define	DMA1_CHN(c)	(IO_DMA1 + 1*(2*(c)))	/* addr reg for channel c */
77 #define	DMA1_SMSK	(IO_DMA1 + 1*10)	/* single mask register */
78 #define	DMA1_MODE	(IO_DMA1 + 1*11)	/* mode register */
79 #define	DMA1_FFC	(IO_DMA1 + 1*12)	/* clear first/last FF */
80 
81 /*
82 **  Register definitions for DMA controller 2 (channels 4..7):
83 */
84 #define	DMA2_CHN(c)	(IO_DMA1 + 2*(2*(c)))	/* addr reg for channel c */
85 #define	DMA2_SMSK	(IO_DMA2 + 2*10)	/* single mask register */
86 #define	DMA2_MODE	(IO_DMA2 + 2*11)	/* mode register */
87 #define	DMA2_FFC	(IO_DMA2 + 2*12)	/* clear first/last FF */
88 
89 int config_isadev(struct isa_device *, u_int *);
90 void config_attach(struct isa_driver *, struct isa_device *);
91 static void sysbeepstop(int);
92 
93 /*
94  * Configure all ISA devices
95  */
96 void
97 isa_configure() {
98 	struct isa_device *dvp;
99 	struct isa_driver *dp;
100 
101 	enable_intr();
102 	splhigh();
103 	INTREN(IRQ_SLAVE);
104 	for (dvp = isa_devtab_tty; config_isadev(dvp,&ttymask); dvp++)
105 		;
106 	for (dvp = isa_devtab_bio; config_isadev(dvp,&biomask); dvp++)
107 		;
108 	for (dvp = isa_devtab_net; config_isadev(dvp,&netmask); dvp++)
109 		;
110 	for (dvp = isa_devtab_null; config_isadev(dvp, (u_int *) NULL); dvp++)
111 		;
112 
113 	impmask = ttymask | netmask;
114 
115 	/* and the problem is... if netmask == 0, then the loopback
116 	 * code can do some really ugly things.
117 	 * workaround for this: if netmask == 0, set it to 0x8000, which
118 	 * is the value used by splsoftclock.  this is nasty, but it
119 	 * should work until this interrupt system goes away. -- cgd
120 	 */
121 	if (netmask == 0)
122 		netmask = 0x8000;	/* same as for softclock.  XXX */
123 
124 	/* biomask |= ttymask ;  can some tty devices use buffers? */
125 	printf("biomask %x ttymask %x netmask %x impmask %x\n",
126 	       biomask, ttymask, netmask, impmask);
127 	splnone();	/* XXX -- probably shouldn't use 'splnone()' */
128 }
129 
130 /*
131  * Configure an ISA device.
132  */
133 int
134 config_isadev(isdp, mp)
135 	struct isa_device *isdp;
136 	u_int *mp;
137 {
138 	struct isa_driver *dp;
139 
140 	if (dp = isdp->id_driver) {
141 		if (isdp->id_maddr) {
142 			extern u_int atdevbase;
143 
144 			isdp->id_maddr -= 0xa0000; /* XXX should be a define */
145 			isdp->id_maddr += atdevbase;
146 		}
147 		isdp->id_alive = (*dp->probe)(isdp);
148 		if (isdp->id_irq == (u_short)-1)
149 			isdp->id_alive = 0;
150 		/*
151 		 * Only print the I/O address range if id_alive != -1
152 		 * Right now this is a temporary fix just for the new
153 		 * NPX code so that if it finds a 486 that can use trap
154 		 * 16 it will not report I/O addresses.
155 		 * Rod Grimes 04/26/94
156 		 *
157 		 * XXX -- cgd
158 		 */
159 		if (isdp->id_alive) {
160 			printf("%s%d", dp->name, isdp->id_unit);
161 			if (isdp->id_iobase) {
162 				printf(" at 0x%x", isdp->id_iobase);
163 				if ((isdp->id_iobase + isdp->id_alive - 1) !=
164 				    isdp->id_iobase)
165 					printf("-0x%x", isdp->id_iobase +
166 					    isdp->id_alive - 1);
167 			}
168 			if (isdp->id_irq != 0)
169 				printf(" irq %d", ffs(isdp->id_irq)-1);
170 			if (isdp->id_drq != -1)
171 				printf(" drq %d", isdp->id_drq);
172 			if (isdp->id_maddr != 0)
173 				printf(" maddr 0x%x", kvtop(isdp->id_maddr));
174 			if (isdp->id_msize != 0)
175 				printf("-0x%x", kvtop(isdp->id_maddr) +
176 					isdp->id_msize - 1);
177 			if (isdp->id_flags != 0)
178 				printf(" flags 0x%x", isdp->id_flags);
179 			printf(" on isa\n");
180 
181 			config_attach(dp, isdp);
182 
183 			if (isdp->id_irq) {
184 				int intrno;
185 
186 				intrno = ffs(isdp->id_irq)-1;
187 				setidt(ICU_OFFSET+intrno, isdp->id_intr,
188 					 SDT_SYS386IGT, SEL_KPL);
189 				if(mp)
190 					INTRMASK(*mp,isdp->id_irq);
191 				INTREN(isdp->id_irq);
192 			}
193 		}
194 		return (1);
195 	} else	return(0);
196 }
197 
198 void
199 config_attach(struct isa_driver *dp, struct isa_device *isdp)
200 {
201 	extern struct isa_device isa_subdev[];
202 	struct isa_device *dvp;
203 
204 	if(isdp->id_masunit==-1) {
205 		(void)(*dp->attach)(isdp);
206 		return;
207 	}
208 
209 	if(isdp->id_masunit==0) {
210 		for(dvp = isa_subdev; dvp->id_driver; dvp++) {
211 			if (dvp->id_driver != dp)
212 				continue;
213 			if (dvp->id_masunit != isdp->id_unit)
214 				continue;
215 			if (dvp->id_physid == -1)
216 				continue;
217 			dvp->id_alive = (*dp->attach)(dvp);
218 		}
219 		for(dvp = isa_subdev; dvp->id_driver; dvp++) {
220 			if (dvp->id_driver != dp)
221 				continue;
222 			if (dvp->id_masunit != isdp->id_unit)
223 				continue;
224 			if (dvp->id_physid != -1)
225 				continue;
226 			dvp->id_alive = (*dp->attach)(dvp);
227 		}
228 		return;
229 	}
230 	printf("id_masunit has weird value\n");
231 }
232 
233 
234 #define	IDTVEC(name)	__CONCAT(X,name)
235 /* default interrupt vector table entries */
236 extern	IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
237 	IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
238 	IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
239 	IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
240 
241 static *defvec[16] = {
242 	&IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
243 	&IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
244 	&IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
245 	&IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15) };
246 
247 /* out of range default interrupt vector gate entry */
248 extern	IDTVEC(intrdefault);
249 
250 /*
251  * Fill in default interrupt table (in case of spuruious interrupt
252  * during configuration of kernel, setup interrupt control unit
253  */
254 void
255 isa_defaultirq() {
256 	int i;
257 
258 	/* icu vectors */
259 	for (i = NRSVIDT ; i < NRSVIDT+ICU_LEN ; i++)
260 		setidt(i, defvec[i],  SDT_SYS386IGT, SEL_KPL);
261 
262 	/* out of range vectors */
263 	for (i = NRSVIDT; i < NIDT; i++)
264 		setidt(i, &IDTVEC(intrdefault), SDT_SYS386IGT, SEL_KPL);
265 
266 	/* initialize 8259's */
267 	outb(IO_ICU1, 0x11);		/* reset; program device, four bytes */
268 	outb(IO_ICU1+1, NRSVIDT);	/* starting at this vector index */
269 	outb(IO_ICU1+1, 1<<2);		/* slave on line 2 */
270 #ifdef AUTO_EOI_1
271 	outb(IO_ICU1+1, 2 | 1);		/* auto EOI, 8086 mode */
272 #else
273 	outb(IO_ICU1+1, 1);		/* 8086 mode */
274 #endif
275 	outb(IO_ICU1+1, 0xff);		/* leave interrupts masked */
276 	outb(IO_ICU1, 0x0a);		/* default to IRR on read */
277 #ifdef REORDER_IRQ
278 	outb(IO_ICU1, 0xc0 | (3 - 1));	/* pri order 3-7, 0-2 (com2 first) */
279 #endif
280 
281 	outb(IO_ICU2, 0x11);		/* reset; program device, four bytes */
282 	outb(IO_ICU2+1, NRSVIDT+8);	/* staring at this vector index */
283 	outb(IO_ICU2+1,2);		/* my slave id is 2 */
284 #ifdef AUTO_EOI_2
285 	outb(IO_ICU2+1, 2 | 1);		/* auto EOI, 8086 mode */
286 #else
287 	outb(IO_ICU2+1,1);		/* 8086 mode */
288 #endif
289 	outb(IO_ICU2+1, 0xff);		/* leave interrupts masked */
290 	outb(IO_ICU2, 0x0a);		/* default to IRR on read */
291 }
292 
293 /* region of physical memory known to be contiguous */
294 vm_offset_t isaphysmem;
295 static caddr_t dma_bounce[8];		/* XXX */
296 static char bounced[8];		/* XXX */
297 #define MAXDMASZ 512		/* XXX */
298 
299 /* high byte of address is stored in this port for i-th dma channel */
300 static short dmapageport[8] =
301 	{ 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
302 
303 /*
304  * isa_dmacascade(): program 8237 DMA controller channel to accept
305  * external dma control by a board.
306  */
307 void
308 isa_dmacascade(unsigned chan)
309 {
310 	if (chan > 7)
311 		panic("isa_dmacascade: impossible request");
312 
313 	/* set dma channel mode, and set dma channel mode */
314 	if ((chan & 4) == 0) {
315 		outb(DMA1_MODE, DMA37MD_CASCADE | chan);
316 		outb(DMA1_SMSK, chan);
317 	} else {
318 		outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
319 		outb(DMA2_SMSK, chan & 3);
320 	}
321 }
322 
323 /*
324  * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
325  * problems by using a bounce buffer.
326  */
327 void
328 isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
329 {	vm_offset_t phys;
330 	int waport;
331 	caddr_t newaddr;
332 
333 	if (    chan > 7
334 	    || (chan < 4 && nbytes > (1<<16))
335 	    || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1)))
336 		panic("isa_dmastart: impossible request");
337 
338 	if (isa_dmarangecheck(addr, nbytes, chan)) {
339 		if (dma_bounce[chan] == 0)
340 			dma_bounce[chan] =
341 				/*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
342 				(caddr_t) isaphysmem + NBPG*chan;
343 		bounced[chan] = 1;
344 		newaddr = dma_bounce[chan];
345 		*(int *) newaddr = 0;	/* XXX */
346 
347 		/* copy bounce buffer on write */
348 		if (!(flags & B_READ))
349 			bcopy(addr, newaddr, nbytes);
350 		addr = newaddr;
351 	}
352 
353 	/* translate to physical */
354 	phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
355 
356 	if ((chan & 4) == 0) {
357 		/*
358 		 * Program one of DMA channels 0..3.  These are
359 		 * byte mode channels.
360 		 */
361 		/* set dma channel mode, and reset address ff */
362 		if (flags & B_READ)
363 			outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
364 		else
365 			outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
366 		outb(DMA1_FFC, 0);
367 
368 		/* send start address */
369 		waport =  DMA1_CHN(chan);
370 		outb(waport, phys);
371 		outb(waport, phys>>8);
372 		outb(dmapageport[chan], phys>>16);
373 
374 		/* send count */
375 		outb(waport + 1, --nbytes);
376 		outb(waport + 1, nbytes>>8);
377 
378 		/* unmask channel */
379 		outb(DMA1_SMSK, chan);
380 	} else {
381 		/*
382 		 * Program one of DMA channels 4..7.  These are
383 		 * word mode channels.
384 		 */
385 		/* set dma channel mode, and reset address ff */
386 		if (flags & B_READ)
387 			outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
388 		else
389 			outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
390 		outb(DMA2_FFC, 0);
391 
392 		/* send start address */
393 		waport = DMA2_CHN(chan - 4);
394 		outb(waport, phys>>1);
395 		outb(waport, phys>>9);
396 		outb(dmapageport[chan], phys>>16);
397 
398 		/* send count */
399 		nbytes >>= 1;
400 		outb(waport + 2, --nbytes);
401 		outb(waport + 2, nbytes>>8);
402 
403 		/* unmask channel */
404 		outb(DMA2_SMSK, chan & 3);
405 	}
406 }
407 
408 void
409 isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
410 {
411 
412 	/* copy bounce buffer on read */
413 	/*if ((flags & (B_PHYS|B_READ)) == (B_PHYS|B_READ))*/
414 	if (bounced[chan]) {
415 		bcopy(dma_bounce[chan], addr, nbytes);
416 		bounced[chan] = 0;
417 	}
418 }
419 
420 /*
421  * Check for problems with the address range of a DMA transfer
422  * (non-contiguous physical pages, outside of bus address space,
423  * crossing DMA page boundaries).
424  * Return true if special handling needed.
425  */
426 
427 int
428 isa_dmarangecheck(caddr_t va, unsigned length, unsigned chan) {
429 	vm_offset_t phys, priorpage = 0, endva;
430 	u_int dma_pgmsk = (chan & 4) ?  ~(128*1024-1) : ~(64*1024-1);
431 
432 	endva = (vm_offset_t)round_page(va + length);
433 	for (; va < (caddr_t) endva ; va += NBPG) {
434 		phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va));
435 #define ISARAM_END	RAM_END
436 		if (phys == 0)
437 			panic("isa_dmacheck: no physical page present");
438 		if (phys > ISARAM_END)
439 			return (1);
440 		if (priorpage) {
441 			if (priorpage + NBPG != phys)
442 				return (1);
443 			/* check if crossing a DMA page boundary */
444 			if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
445 				return (1);
446 		}
447 		priorpage = phys;
448 	}
449 	return (0);
450 }
451 
452 /* head of queue waiting for physmem to become available */
453 struct buf isa_physmemq;
454 
455 /* blocked waiting for resource to become free for exclusive use */
456 static isaphysmemflag;
457 /* if waited for and call requested when free (B_CALL) */
458 static void (*isaphysmemunblock)(); /* needs to be a list */
459 
460 /*
461  * Allocate contiguous physical memory for transfer, returning
462  * a *virtual* address to region. May block waiting for resource.
463  * (assumed to be called at splbio())
464  */
465 caddr_t
466 isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) {
467 
468 	isaphysmemunblock = func;
469 	while (isaphysmemflag & B_BUSY) {
470 		isaphysmemflag |= B_WANTED;
471 		sleep((caddr_t)&isaphysmemflag, PRIBIO);
472 	}
473 	isaphysmemflag |= B_BUSY;
474 
475 	return((caddr_t)isaphysmem);
476 }
477 
478 /*
479  * Free contiguous physical memory used for transfer.
480  * (assumed to be called at splbio())
481  */
482 void
483 isa_freephysmem(caddr_t va, unsigned length) {
484 
485 	isaphysmemflag &= ~B_BUSY;
486 	if (isaphysmemflag & B_WANTED) {
487 		isaphysmemflag &= B_WANTED;
488 		wakeup((caddr_t)&isaphysmemflag);
489 		if (isaphysmemunblock)
490 			(*isaphysmemunblock)();
491 	}
492 }
493 
494 /*
495  * Handle a NMI, possibly a machine check.
496  * return true to panic system, false to ignore.
497  */
498 int
499 isa_nmi(cd) {
500 
501 	log(LOG_CRIT, "\nNMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70));
502 	return(0);
503 }
504 
505 /*
506  * Caught a stray interrupt, notify
507  */
508 void
509 isa_strayintr(d) {
510 
511 	/* DON'T BOTHER FOR NOW! */
512 	/* for some reason, we get bursts of intr #7, even if not enabled! */
513 	/*
514 	 * Well the reason you got bursts of intr #7 is because someone
515 	 * raised an interrupt line and dropped it before the 8259 could
516 	 * prioritize it.  This is documented in the intel data book.  This
517 	 * means you have BAD hardware!  I have changed this so that only
518 	 * the first 5 get logged, then it quits logging them, and puts
519 	 * out a special message. rgrimes 3/25/1993
520 	 */
521 	extern u_long intrcnt_stray;
522 
523 	intrcnt_stray++;
524 	if (intrcnt_stray <= 5)
525 		log(LOG_ERR,"ISA strayintr %x\n", d);
526 	if (intrcnt_stray == 5)
527 		log(LOG_CRIT,"Too many ISA strayintr not logging any more\n");
528 }
529 
530 /*
531  * Wait "n" microseconds.
532  * Relies on timer 1 counting down from (TIMER_FREQ / hz) at
533  * (1 * TIMER_FREQ) Hz.
534  * Note: timer had better have been programmed before this is first used!
535  * (Note that we use `rate generator' mode, which counts at 1:1; `square
536  * wave' mode counts at 2:1).
537  */
538 #define       CF              (1 * TIMER_FREQ)
539 
540 extern int hz;                        /* XXX - should be elsewhere */
541 
542 void
543 DELAY(n)
544 	int n;
545 {
546 	int counter_limit;
547 	int prev_tick;
548 	int tick;
549 	int ticks_left;
550 	int sec;
551 	int usec;
552 
553 #ifdef DELAYDEBUG
554 	int gettick_calls = 1;
555 	int n1;
556 	static int state = 0;
557 
558 	if (state == 0) {
559 		state = 1;
560 		for (n1 = 1; n1 <= 10000000; n1 *= 10)
561 			DELAY(n1);
562 		state = 2;
563 	}
564 	if (state == 1)
565 		printf("DELAY(%d)...", n);
566 #endif
567 
568 	/*
569 	 * Read the counter first, so that the rest of the setup overhead is
570 	 * counted.  Guess the initial overhead is 20 usec (on most systems it
571 	 * takes about 1.5 usec for each of the i/o's in gettick().  The loop
572 	 * takes about 6 usec on a 486/33 and 13 usec on a 386/20.  The
573 	 * multiplications and divisions to scale the count take a while).
574 	 */
575 	prev_tick = gettick();
576 	n -= 20;
577 
578 	/*
579 	 * Calculate (n * (CF / 1e6)) without using floating point and without
580 	 * any avoidable overflows.
581 	 */
582 	sec = n / 1000000;
583 	usec = n - sec * 1000000;
584 	ticks_left = sec * CF
585 		+ usec * (CF / 1000000)
586 		+ usec * ((CF % 1000000) / 1000) / 1000
587 		+ usec * (CF % 1000) / 1000000;
588 
589 	counter_limit = TIMER_FREQ / hz;
590 	while (ticks_left > 0) {
591 		tick = gettick();
592 #ifdef DELAYDEBUG
593 		++gettick_calls;
594 #endif
595 		if (tick > prev_tick)
596 			ticks_left -= prev_tick - (tick - counter_limit);
597 		else
598 			ticks_left -= prev_tick - tick;
599 		prev_tick = tick;
600 	}
601 #ifdef DELAYDEBUG
602 	if (state == 1)
603 		printf(" %d calls to gettick() at %d usec each\n",
604 			gettick_calls, (n + 5) / gettick_calls);
605 #endif
606 }
607 
608 int
609 gettick() {
610 	int high;
611 	int low;
612 
613 	/*
614 	 * Protect ourself against interrupts.
615 	 */
616 	disable_intr();
617 	/*
618 	 * Latch the count for 'timer' (cc00xxxx, c = counter, x = any).
619 	 */
620 	outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
621 	low = inb(TIMER_CNTR0);
622 	high = inb(TIMER_CNTR0);
623 	enable_intr();
624 	return ((high << 8) | low);
625 }
626 
627 static beeping;
628 static void
629 sysbeepstop(int f)
630 {
631 	int s = splhigh();
632 
633 	/* disable counter 2 */
634 	disable_intr();
635 	outb(PITAUX_PORT, inb(PITAUX_PORT) & ~PIT_SPKR);
636 	enable_intr();
637 	if (f)
638 		timeout((timeout_t)sysbeepstop, (caddr_t)0, f);
639 	else
640 		beeping = 0;
641 
642 	splx(s);
643 }
644 
645 void
646 sysbeep(int pitch, int period)
647 {
648 	int s = splhigh();
649 	static int last_pitch, last_period;
650 
651 	if (beeping) {
652 		untimeout((timeout_t)sysbeepstop, (caddr_t)(last_period/2));
653 		untimeout((timeout_t)sysbeepstop, (caddr_t)0);
654 	}
655 	if (!beeping || last_pitch != pitch) {
656 		/*
657 	 	* XXX - move timer stuff to clock.c.
658 	 	*/
659 		disable_intr();
660 		outb(TIMER_MODE, TIMER_SEL2|TIMER_16BIT|TIMER_SQWAVE);
661 		outb(TIMER_CNTR2, TIMER_DIV(pitch)%256);
662 		outb(TIMER_CNTR2, TIMER_DIV(pitch)/256);
663 		outb(PITAUX_PORT, inb(PITAUX_PORT) | PIT_SPKR);	/* enable counter 2 */
664 		enable_intr();
665 	}
666 	last_pitch = pitch;
667 	beeping = last_period = period;
668 	timeout((timeout_t)sysbeepstop, (caddr_t)(period/2), period);
669 
670 	splx(s);
671 }
672 
673 /*
674  * Pass command to keyboard controller (8042)
675  */
676 unsigned
677 kbc_8042cmd(int val)
678 {
679 	while (inb(KBSTATP)&KBS_IBF);
680 	if (val) outb(KBCMDP, val);
681 	while (inb(KBSTATP)&KBS_IBF);
682 	return (inb(KBDATAP));
683 }
684 
685 /*
686  * find an ISA device in a given isa_devtab_* table, given
687  * the table to search, the expected id_driver entry, and the unit number.
688  *
689  * this function is defined in isa_device.h, and this location is debatable;
690  * i put it there because it's useless w/o, and directly operates on
691  * the other stuff in that file.
692  *
693  */
694 
695 struct isa_device *find_isadev(table, driverp, unit)
696 	struct isa_device *table;
697 	struct isa_driver *driverp;
698 	int unit;
699 {
700 	if (driverp == NULL) /* sanity check */
701 		return NULL;
702 
703 	while ((table->id_driver != driverp) || (table->id_unit != unit)) {
704 		if (table->id_driver == 0)
705 			return NULL;
706 
707 		table++;
708         }
709 
710 	return table;
711 }
712 
713 /*
714  * Return nonzero if a (masked) irq is pending for a given device.
715  */
716 int
717 isa_irq_pending(dvp)
718 	struct isa_device *dvp;
719 {
720 	unsigned id_irq;
721 
722 	id_irq = (unsigned short) dvp->id_irq;	/* XXX silly type in struct */
723 	if (id_irq & 0xff)
724 		return (inb(IO_ICU1) & id_irq);
725 	return (inb(IO_ICU2) & (id_irq >> 8));
726 }
727